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GET /api/1.1/patches/2231726/?format=api
{ "id": 2231726, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231726/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-29-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260501101505.3485916-29-peter.maydell@linaro.org>", "date": "2026-05-01T10:15:05", "name": "[PULL,28/28] hvf: arm: enable vGIC by default for virt-11.1 and later", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "93b41e5b1c04b321788a3484cfe8bde2f56ea023", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-29-peter.maydell@linaro.org/mbox/", "series": [ { "id": 502437, "url": "http://patchwork.ozlabs.org/api/1.1/series/502437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502437", "date": "2026-05-01T10:14:41", "name": "[PULL,01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231726/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231726/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nNn3rHR6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6RnD18cGz1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 01 May 2026 20:17:52 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIkuT-00048q-1s; Fri, 01 May 2026 06:15:49 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuO-000469-LJ\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:44 -0400", "from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuM-0000M9-Ph\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:44 -0400", "by mail-wm1-x32f.google.com with SMTP id\n 5b1f17b1804b1-483487335c2so19480145e9.2\n for <qemu-devel@nongnu.org>; Fri, 01 May 2026 03:15:42 -0700 (PDT)", "from lanath.. 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helo=mail-wm1-x32f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nSave states are incompatible between kernel-irqchip=on and off on HVF due to opaque vGIC state.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>\nMessage-id: 20260429190532.26538-16-mohamed@unpredictable.fr\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n accel/hvf/hvf-all.c | 11 +++++++++++\n hw/arm/virt.c | 15 +++++++++++++++\n include/hw/arm/virt.h | 2 ++\n include/hw/core/boards.h | 1 +\n include/system/hvf_int.h | 1 +\n 5 files changed, 30 insertions(+)", "diff": "diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c\nindex da29aa3aa3..946dbca59d 100644\n--- a/accel/hvf/hvf-all.c\n+++ b/accel/hvf/hvf-all.c\n@@ -25,6 +25,7 @@\n bool hvf_allowed;\n bool hvf_kernel_irqchip;\n bool hvf_nested_virt;\n+bool hvf_kernel_irqchip_override;\n \n void hvf_nested_virt_enable(bool nested_virt)\n {\n@@ -204,6 +205,13 @@ static int hvf_accel_init(AccelState *as, MachineState *ms)\n }\n }\n \n+ if (mc->get_kernel_irqchip_default) {\n+ bool kernel_irqchip_default = mc->get_kernel_irqchip_default(ms);\n+ if (!hvf_kernel_irqchip_override) {\n+ hvf_kernel_irqchip = kernel_irqchip_default;\n+ }\n+ }\n+\n ret = hvf_arch_vm_create(ms, (uint32_t)pa_range);\n if (ret == HV_DENIED) {\n error_report(\"Could not access HVF. Is the executable signed\"\n@@ -230,6 +238,8 @@ static void hvf_set_kernel_irqchip(Object *obj, Visitor *v,\n Error **errp)\n {\n OnOffSplit mode;\n+\n+ hvf_kernel_irqchip_override = true;\n if (!visit_type_OnOffSplit(v, name, &mode, errp)) {\n return;\n }\n@@ -269,6 +279,7 @@ static void hvf_accel_class_init(ObjectClass *oc, const void *data)\n ac->init_machine = hvf_accel_init;\n ac->allowed = &hvf_allowed;\n ac->gdbstub_supported_sstep_flags = hvf_gdbstub_sstep_flags;\n+ hvf_kernel_irqchip_override = false;\n hvf_kernel_irqchip = false;\n object_class_property_add(oc, \"kernel-irqchip\", \"on|off|split\",\n NULL, hvf_set_kernel_irqchip,\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ad0a459987..fe19030886 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -3769,6 +3769,17 @@ static int virt_get_physical_address_range(MachineState *ms,\n return requested_ipa_size;\n }\n \n+static bool get_kernel_irqchip_default(const MachineState *ms)\n+{\n+ VirtMachineState *vms = VIRT_MACHINE(ms);\n+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);\n+ if (hvf_allowed) {\n+ return !vmc->hvf_no_kernel_irqchip_default;\n+ } else {\n+ return true;\n+ }\n+}\n+\n static const char *virt_get_default_cpu_type(const MachineState *ms)\n {\n return tcg_enabled() ? ARM_CPU_TYPE_NAME(\"cortex-a15\")\n@@ -3835,6 +3846,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;\n mc->kvm_type = virt_kvm_type;\n mc->get_physical_address_range = virt_get_physical_address_range;\n+ mc->get_kernel_irqchip_default = get_kernel_irqchip_default;\n assert(!mc->get_hotplug_handler);\n mc->get_hotplug_handler = virt_machine_get_hotplug_handler;\n hc->pre_plug = virt_machine_device_pre_plug_cb;\n@@ -4079,8 +4091,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(11, 1)\n \n static void virt_machine_11_0_options(MachineClass *mc)\n {\n+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));\n+\n virt_machine_11_1_options(mc);\n compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);\n+ vmc->hvf_no_kernel_irqchip_default = true;\n }\n DEFINE_VIRT_MACHINE(11, 0)\n \ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex fc7950da85..13e135a460 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -138,6 +138,8 @@ struct VirtMachineClass {\n bool no_tcg_lpa2;\n bool no_ns_el2_virt_timer_irq;\n bool no_nested_smmu;\n+ /* HVF specific: support for kernel-irqchip=on introduced in QEMU 11.1 */\n+ bool hvf_no_kernel_irqchip_default;\n };\n \n struct VirtMachineState {\ndiff --git a/include/hw/core/boards.h b/include/hw/core/boards.h\nindex ca63304c95..29c68931d8 100644\n--- a/include/hw/core/boards.h\n+++ b/include/hw/core/boards.h\n@@ -280,6 +280,7 @@ struct MachineClass {\n int (*kvm_type)(MachineState *machine, const char *arg);\n int (*get_physical_address_range)(MachineState *machine,\n int default_ipa_size, int max_ipa_size);\n+ bool (*get_kernel_irqchip_default) (const MachineState *machine);\n \n BlockInterfaceType block_default_type;\n int units_per_default_bus;\ndiff --git a/include/system/hvf_int.h b/include/system/hvf_int.h\nindex 2621164cb2..ad7d375109 100644\n--- a/include/system/hvf_int.h\n+++ b/include/system/hvf_int.h\n@@ -112,4 +112,5 @@ bool hvf_arch_cpu_realize(CPUState *cpu, Error **errp);\n uint32_t hvf_arch_get_default_ipa_bit_size(void);\n uint32_t hvf_arch_get_max_ipa_bit_size(void);\n \n+extern bool hvf_kernel_irqchip_override;\n #endif\n", "prefixes": [ "PULL", "28/28" ] }