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GET /api/1.1/patches/2231721/?format=api
{ "id": 2231721, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231721/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-22-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260501101505.3485916-22-peter.maydell@linaro.org>", "date": "2026-05-01T10:14:58", "name": "[PULL,21/28] hvf: arm: allow exposing minimal PMU for kernel-irqchip=on", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "10538611a4e2b4f8e564e15cd57ebd4decaeb2c5", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.1/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260501101505.3485916-22-peter.maydell@linaro.org/mbox/", "series": [ { "id": 502437, "url": "http://patchwork.ozlabs.org/api/1.1/series/502437/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502437", "date": "2026-05-01T10:14:41", "name": "[PULL,01/28] hw/arm/fsl-imx8mp: Do not create redundant unimplemented devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502437/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231721/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231721/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=EPfgCyv5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6Rmq4sz4z1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 01 May 2026 20:17:31 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIkuK-00043V-53; Fri, 01 May 2026 06:15:40 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuH-000421-8x\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:37 -0400", "from mail-wm1-x335.google.com ([2a00:1450:4864:20::335])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wIkuF-0000Cy-4t\n for qemu-devel@nongnu.org; Fri, 01 May 2026 06:15:36 -0400", "by mail-wm1-x335.google.com with SMTP id\n 5b1f17b1804b1-488a9033b2cso16032825e9.2\n for <qemu-devel@nongnu.org>; Fri, 01 May 2026 03:15:34 -0700 (PDT)", "from lanath.. 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[81.2.115.145])\n by smtp.gmail.com with ESMTPSA id\n 5b1f17b1804b1-48a8fede418sm12863335e9.6.2026.05.01.03.15.32\n for <qemu-devel@nongnu.org>\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 01 May 2026 03:15:32 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777630533; x=1778235333; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:from:to:cc:subject:date:message-id\n :reply-to; bh=PWDJWe2AZnBQY7IEBTYHtAZi/b84KqQOngZk5MTLZWU=;\n b=EPfgCyv530SKKZqhAfto+zEIYx/DSem6+rcMRqSkWVIiiPACDwSnFXFs0r9tgVhJoA\n nTHhkjZyw5vzHEF/WQIkj/6uZHVHu/6L+o2vV+lOf9EOdSCxfV/aKc9crGwseEDujjgy\n N/5k+6IeHVB4XOd1BdQbxT2ZOWE0tLFV34QV5W+pAwitR4NUK276juXK907J/VDKC7lM\n +FUqFV3cB5htvIVyuDejcn4ssS9CaTi4WTfs5AJ5yrMTTk3hCB76kkDKaNdI06W/bdmW\n NHTchkGlef3FL48g71nX2e+EzYNVRaNKxCiH26SsYi+2/sZNiRNkvpLgJp8AJglrckbS\n O8Sw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777630533; x=1778235333;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to\n :cc:subject:date:message-id:reply-to;\n bh=PWDJWe2AZnBQY7IEBTYHtAZi/b84KqQOngZk5MTLZWU=;\n b=Z/ByJ2N18CyGbxWliPhqCsbRL/cWPc6crW2+I5F9Q7iglbZOtsXymxQnv7N+FCqDbj\n HlXJZ2325O+5g4gguyCU+FbTgTX/ns+9neDEN2AFsTLFXJhi/9WBp7Kx803zxuoAlOvA\n z1sJBnh+obhlLOmK/IwoAqCA7wmeP8o6vo3LmbiUPZixcoesLeo2+zjzPdXoUHuHtYfn\n BBly6V1BJGSu7zS6FNkkLKNRJZgAVncVCXvQnf+j6F+v6OUn1g9+ZZLQ22JR9WGEYnnB\n tx1ccgd4R3j6GHpvlC4khSwAtjxVfq5BGhej92OPnlVfbsDYRhw0QGjKGSxuYr+3uCYt\n /p+Q==", "X-Gm-Message-State": "AOJu0YyHes8JJL+R54uNqsyl5O42CkY+JeDpdjOFbz8TG7mYfQv0bpCL\n z9OATjTQEJgEBYO615ckIsCx0yF/VY1PMbEkfH0aaOUGjI1gjiC0+hkPKT61OVEOoOhPhoES2C5\n qrthj", "X-Gm-Gg": "AeBDietVYsm5O9QEBin1V8bAZ0Gxvom2c47fXzEMAaPiVzEkmeAQR6xQ0JFWHbhDA9L\n onvABjdn+BOYlu9dGgeYr1980Q1gCNS8XmEiqAjKIetF5WKvxqnk4FwuiDCIfeRwV9orBHhGK3z\n FQg9g+QNXggrVSSKuKE9LX0sQ7Z6pHc9A77bj/zfaD43CaXnkdRmZWcXQ3OE4fVyGWZc0TIY2jM\n 06pRYw/gdEfMYFtbv9oUFhIzcwUwvpBkQ3TfIo5xbNpL5hWgxoZYBdI6O6E4qwv9eqI4waspPdQ\n 3GG4l5dnJnCRpdUCgkm5crMC/UFGNdMyZLWerGninAlFijRX9dl2xzCwDcZIWRTsy1wRYAjvDXw\n Xmub+WJ1JM180dAxjNgX9JZPOX8X8jfupb5uheHDK2WTW3iX9rDhiy+9MoQJ99oh3ICAw5CCbIc\n Eha4qu/gD3fLf/p4FBg/ctkEA24M0sjbUyTxRrnmtm9ujlPxDh4jk4gDhV2DwW3c0J6AFDJk0Tl\n qdd4m0erIznEnsYJff0A3vwnJOs9uRVEmh0ofZVbA==", "X-Received": "by 2002:a05:600c:8719:b0:489:1f97:6b1d with SMTP id\n 5b1f17b1804b1-48a8ebaa93cmr39418675e9.28.1777630533518;\n Fri, 01 May 2026 03:15:33 -0700 (PDT)", "From": "Peter Maydell <peter.maydell@linaro.org>", "To": "qemu-devel@nongnu.org", "Subject": "[PULL 21/28] hvf: arm: allow exposing minimal PMU for\n kernel-irqchip=on", "Date": "Fri, 1 May 2026 11:14:58 +0100", "Message-ID": "<20260501101505.3485916-22-peter.maydell@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "References": "<20260501101505.3485916-1-peter.maydell@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::335;\n envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Mohamed Mediouni <mohamed@unpredictable.fr>\n\nWhen running with the Apple vGIC, a minimum PMU is exposed by Hypervisor.framework\nif a valid PMUVer register value is set. That PMU isn't exposed otherwise.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-id: 20260429190532.26538-9-mohamed@unpredictable.fr\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n target/arm/hvf/hvf.c | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 9d64f2e1a5..390a3529ff 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -1145,6 +1145,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n \n clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);\n \n+ /*\n+ * Windows wants at least the PMU's cycles counter to be available.\n+ *\n+ * With kernel-irqchip=off, we \"emulate\" the cycles counter\n+ * in reference to time in QEMU. Having that, even with\n+ * ID_AA64DFR0_EL1.PMUVer = 0 is enough to make Windows happy.\n+ *\n+ * As it's a very inaccurate implementation with its only purpose\n+ * being making Windows boot, expose ID_AA64DFR0_EL1.PMUVer = 0\n+ * when kernel-irqchip=off.\n+ *\n+ * When kernel-irqchip=on *and* ID_AA64DFR0_EL1.PMUVer = 1,\n+ * the OS provides its own PMU emulation, which is currently\n+ * a cycles counter only emulation.\n+ */\n+ if (hvf_irqchip_in_kernel()) {\n+ FIELD_DP64_IDREG(&host_isar, ID_AA64DFR0, PMUVER, 0x1);\n+ }\n+\n ahcf->isar = host_isar;\n \n /*\n", "prefixes": [ "PULL", "21/28" ] }