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GET /api/1.1/patches/2231665/?format=api
{ "id": 2231665, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/c4eb7b2b-5576-46c9-a20e-e0b73f808c09@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<c4eb7b2b-5576-46c9-a20e-e0b73f808c09@oss.qualcomm.com>", "date": "2026-05-01T04:12:32", "name": "[to-be-committed,PR,target/124559,RISC-V] Improve RISC-V constant synthesis for some HImode constants", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8415badf073d25cbeda4c85f75f1f69f0ed4f0de", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/c4eb7b2b-5576-46c9-a20e-e0b73f808c09@oss.qualcomm.com/mbox/", "series": [ { "id": 502421, "url": "http://patchwork.ozlabs.org/api/1.1/series/502421/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502421", "date": "2026-05-01T04:12:32", "name": "[to-be-committed,PR,target/124559,RISC-V] Improve RISC-V constant synthesis for some HImode constants", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502421/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231665/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231665/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=iFtIaIr1;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ANykKo2Y;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------JHtor7OQp58oa7lRAspPxLOZ\"", "Message-ID": "<c4eb7b2b-5576-46c9-a20e-e0b73f808c09@oss.qualcomm.com>", "Date": "Thu, 30 Apr 2026 22:12:32 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "Subject": "[to-be-committed][PR target/124559][RISC-V] Improve RISC-V constant\n synthesis for some HImode constants", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTAxMDAzNiBTYWx0ZWRfX8GJ9ilGEqxwV\n FxgIqQr6U58a3RO/VDkOyutONvec0f7nilFx/yQMmxmwGmgSyI8EGvAEedsSZRnBsS4g9N6GCEs\n nvn/TbL8LPtgaAi1F6wGvSn+C6kwDUErKoNrDMe9mb07nmZ9varyR5K9ZBCUavaFisggQzGjnBp\n iHS4dmf1iOFxsLJBPwYVxrCH2MqN+nnvVT3yxccmb9itCpAbioim5tzqk+C6W8QC3JQGHLBaMhz\n xBnVW452wl88UjIfwbUZ0zTKp3z5pF9W+62e9T9IBYsn7nODAFzhPbiJ95VR0b+m8dxBnMSMpIo\n hcXDUa1YMxStTrEA+j7aEAA0WE6L/a8vbS33ye//2QAEY+QGXEMmL3UTKDaRIuxBl3X6mn3VmyU\n n0ksnALEF93n6DjZIJGBkLnqL8RMzpwMIGAEk/OTIisxoJ2lQiZW+BFzyl3gBzsnyzryNxxZ+N5\n XQrOGrj9hXAz/zkZAFg==", "X-Authority-Analysis": "v=2.4 cv=DP+/JSNb c=1 sm=1 tr=0 ts=69f42834 cx=c_pps\n a=Uww141gWH0fZj/3QKPojxA==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=vFzgyzLtmaUEubHP3GAA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=eMAwN-m84tZRz3EOXYAA:9 a=B2y7HmGcmWMA:10 a=PxkB5W3o20Ba91AHUih5:22", "X-Proofpoint-ORIG-GUID": "YL-7rd3csUr_FGLKQEFCMMRNb_L5AIJZ", "X-Proofpoint-GUID": "YL-7rd3csUr_FGLKQEFCMMRNb_L5AIJZ", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-01_01,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0\n adultscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 bulkscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605010036", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "So this is a trivial little bug we found doing some comparisons against \nLLVM.\n\nFor the function sub2 in load-immediate.c we get this code:\n\n li a5,-32768\n sh a5,0(a0)\n xori a5,a5,-1\n sh a5,0(a1)\n\nNote carefully that li+xori. There's a slightly better sequence here \nfrom an encoding standpoint. Instead of using xori we can adjust the \nsynthesis sequence to target an \"addi\" for that statement and in doing \nso we can save two code bytes of space.\n\nThe xori sequence was used because we can't do this in gcc:\n\n\n(set (dest:HI) (const_int 0x8000))\n\nWe're in HI mode so the constant must be sign extended from bit 15 to a \nHOST_WIDE_INT.\n\nFixing this isn't hard. The key is realizing the vast majority of the \ntime we really don't want/need to load in HImode and in fact we're \ntypically going to be generating objects in word_mode. So instead of \npassing in the pre-promoted mode, pass in the post-promoted mode.\n\nThat's fine and good with one caveat. CSE fails to use NEG/NOT to \nderive a new constant from an older constant, even if the cost is \nsmaller, which caused a code quality regression elsewhere on the RISC-V \nport. So this patch adjusts CSE ever-so-slightly to allow it to derive \nconstants from a previous constant using NOT/NEG in a fairly obvious way.\n\nThis has been in my tester for a while, so it's been through the usual \nbootstrap & regression test on the Pioneer, BPI, x86 and aarch64 and \nothers as well as testing across the various embedded targets.\n\nWaiting on pre-commit testing to do its thing.\n\nJeff\n* config/riscv/riscv-protos.h (riscv_move_integer): Drop mode argument. Pass\n\tmode after promotions to riscv_build_integer.\n\tAll callers changed.\n\t* config/riscv/riscv.md: Corresponding changes.\n\t* cse.cc (cse_insn): Try to derive one constant from another using NOT/NEG.", "diff": "diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h\nindex dd029c704133..494feb4458de 100644\n--- a/gcc/config/riscv/riscv-protos.h\n+++ b/gcc/config/riscv/riscv-protos.h\n@@ -119,7 +119,7 @@ extern rtx riscv_emit_move (rtx, rtx);\n extern bool riscv_split_symbol (rtx, rtx, machine_mode, rtx *);\n extern bool riscv_split_symbol_type (enum riscv_symbol_type);\n extern rtx riscv_unspec_address (rtx, enum riscv_symbol_type);\n-extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT, machine_mode);\n+extern void riscv_move_integer (rtx, rtx, HOST_WIDE_INT);\n extern bool riscv_legitimize_move (machine_mode, rtx, rtx);\n extern rtx riscv_subword (rtx, bool);\n extern bool riscv_split_64bit_move_p (rtx, rtx);\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 282cf71ad61c..6142a452b6df 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -1733,15 +1733,15 @@ riscv_split_integer (HOST_WIDE_INT val, machine_mode mode)\n bool eq_neg = (loval == hival) && ((loval & 0x80000000) != 0);\n \n if (eq_neg)\n- riscv_move_integer (lo, lo, ~loval & 0xffffffff, mode);\n+ riscv_move_integer (lo, lo, ~loval & 0xffffffff);\n else\n- riscv_move_integer (lo, lo, loval, mode);\n+ riscv_move_integer (lo, lo, loval);\n \n if (loval == hival)\n hi = gen_rtx_ASHIFT (mode, lo, GEN_INT (32));\n else\n {\n- riscv_move_integer (hi, hi, hival, mode);\n+ riscv_move_integer (hi, hi, hival);\n hi = gen_rtx_ASHIFT (mode, hi, GEN_INT (32));\n }\n \n@@ -3272,8 +3272,7 @@ riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,\n is the original src mode before promotion. */\n \n void\n-riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,\n-\t\t machine_mode orig_mode)\n+riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value)\n {\n struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS];\n machine_mode mode;\n@@ -3281,9 +3280,10 @@ riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value,\n rtx x = NULL_RTX;\n \n mode = GET_MODE (dest);\n- /* We use the original mode for the riscv_build_integer call, because HImode\n- values are given special treatment. */\n- num_ops = riscv_build_integer (codes, value, orig_mode, can_create_pseudo_p ());\n+ /* This originally passed in a mode prior to promotions, but what we really\n+ need to do is pass in the mode of the destination, that's what ultimately\n+ determines how a constant needs to be canonicalized. */\n+ num_ops = riscv_build_integer (codes, value, mode, can_create_pseudo_p ());\n \n if (can_create_pseudo_p () && num_ops > 2 /* not a simple constant */\n && num_ops >= riscv_split_integer_cost (value))\n@@ -3380,7 +3380,7 @@ riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src)\n /* Split moves of big integers into smaller pieces. */\n if (splittable_const_int_operand (src, mode))\n {\n- riscv_move_integer (dest, dest, INTVAL (src), mode);\n+ riscv_move_integer (dest, dest, INTVAL (src));\n return;\n }\n \n@@ -3967,7 +3967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)\n \t if (splittable_const_int_operand (src, mode))\n \t {\n \t reg = gen_reg_rtx (promoted_mode);\n-\t riscv_move_integer (reg, reg, INTVAL (src), mode);\n+\t riscv_move_integer (reg, reg, INTVAL (src));\n \t }\n \t else\n \t reg = force_reg (promoted_mode, src);\ndiff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md\nindex 3fe0ad0ccdf4..7bb338eb6d35 100644\n--- a/gcc/config/riscv/riscv.md\n+++ b/gcc/config/riscv/riscv.md\n@@ -2464,8 +2464,7 @@ (define_split\n \"\"\n [(const_int 0)]\n {\n- riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]),\n-\t\t <GPR:MODE>mode);\n+ riscv_move_integer (operands[2], operands[0], INTVAL (operands[1]));\n DONE;\n })\n \n@@ -2498,8 +2497,7 @@ (define_insn_and_split \"*mvconst_internal\"\n \"&& 1\"\n [(const_int 0)]\n {\n- riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]),\n- <MODE>mode);\n+ riscv_move_integer (operands[0], operands[0], INTVAL (operands[1]));\n DONE;\n }\n [(set_attr \"type\" \"move\")])\ndiff --git a/gcc/cse.cc b/gcc/cse.cc\nindex e5fa88f9de50..8ac45245b9d4 100644\n--- a/gcc/cse.cc\n+++ b/gcc/cse.cc\n@@ -4962,6 +4962,34 @@ cse_insn (rtx_insn *insn)\n \t }\n \t}\n \n+ /* If SRC_EQV is a CONST_INT, try looking up some related\n+\t constants (logical and arithmetic negation). Those may\n+\t ultimately be cheaper to re-use. */\n+ if (GET_CODE (src) != CONST_INT\n+\t && GET_CODE (src) != REG\n+\t && GET_CODE (src) != SUBREG\n+\t && src_const\n+\t && GET_CODE (src_const) == CONST_INT)\n+\t{\n+\t rtx trial_rtx = GEN_INT (~UINTVAL (src_const));\n+\t struct table_elt *tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode);\n+\t rtx_code code = NOT;\n+\t if (!tmp)\n+\t {\n+\t trial_rtx = GEN_INT (-UINTVAL (src_const));\n+\t tmp = lookup (trial_rtx, HASH (trial_rtx, mode), mode);\n+\t code = NEG;\n+\t }\n+\n+\t if (tmp)\n+\t {\n+\t src_related = gen_rtx_fmt_e (code, mode, tmp->first_same_value->exp);\n+\t src_eqv_here = src_related;\n+\t src_related_is_const_anchor = true;\n+\t }\n+\n+\t}\n+\n /* See if a MEM has already been loaded with a widening operation;\n \t if it has, we can use a subreg of that. Many CISC machines\n \t also have such operations, but this is only likely to be\n", "prefixes": [ "to-be-committed", "PR", "target/124559", "RISC-V" ] }