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GET /api/1.1/patches/2231657/?format=api
{ "id": 2231657, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231657/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/737b4d77-8df9-42dd-8c79-f862baac4e71@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<737b4d77-8df9-42dd-8c79-f862baac4e71@oss.qualcomm.com>", "date": "2026-05-01T03:48:13", "name": "[to-be-committed,RISC-V,PR,tree-optimization/109038] Recognize shifts+rotate as simple shift in some cases", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6799b851a6e3ff17760c002769d21f6c7c2ce55b", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/737b4d77-8df9-42dd-8c79-f862baac4e71@oss.qualcomm.com/mbox/", "series": [ { "id": 502419, "url": "http://patchwork.ozlabs.org/api/1.1/series/502419/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502419", "date": "2026-05-01T03:48:13", "name": "[to-be-committed,RISC-V,PR,tree-optimization/109038] Recognize shifts+rotate as simple shift in some cases", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502419/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231657/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231657/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=MPnZNHW6;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=JtNSH4Ze;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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boundary=\"------------WEKlF5YQkFlyZ0eQLAn1nWDB\"", "Message-ID": "<737b4d77-8df9-42dd-8c79-f862baac4e71@oss.qualcomm.com>", "Date": "Thu, 30 Apr 2026 21:48:13 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Content-Language": "en-US", "Subject": "[to-be-committed][RISC-V][PR tree-optimization/109038] Recognize\n shifts+rotate as simple shift in some cases", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "X-Proofpoint-GUID": "R4lEINM_S-h4hqtXyf2ogF86nykqYkNv", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNTAxMDAzMCBTYWx0ZWRfX45ZlQzTmjgdi\n wZhXjpmXhUcMkYpn1uraO8VknT/eeD0zGVFveCv79/v3itJgFhwMggu1nhjohJcg9OiSFgZ2yXn\n Z5g77Ujxn07wQOrNociE2aezRxVrmuTvd+44BTkwtAXOrUKLC+wL7Y+BwyfM2FQnP2A5Sf79bXj\n /ulTa8yClPtnXaMhPqWRDh4QqqgHElNMfhlZohplMTfwvITlRO9FfxQVmypZb86DEY9ounWPQXb\n vUFh2VbQz6XX++BRkElcaghNgVj5bwNt+CpOfpMeHB7bYrdZBCTwWFxV/YqW0rBhwUNfvskGoop\n 0IuBaSM/abT3L/psZdT2lLDuKCfAi7s/NHFGj6HoHfm9ktfgMtvblFbvhqFun6ryJ7s6x4d8qnS\n yvi+wgocBQiv4+M7FO2kS8hV9NC1djsdCiqvCH3KHQB2fBov0gjN3QEDdtMO2514mVztntk98+x\n bgeL3XZRU8PBS4oE1LA==", "X-Authority-Analysis": "v=2.4 cv=UcxhjqSN c=1 sm=1 tr=0 ts=69f42281 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=wrwi2iGPzoTy54-3hUkA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=7HWjmwRNFuBC6MNrEPoA:9 a=B2y7HmGcmWMA:10 a=scEy_gLbYbu1JhEsrz4S:22", "X-Proofpoint-ORIG-GUID": "R4lEINM_S-h4hqtXyf2ogF86nykqYkNv", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-01_01,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0\n impostorscore=0 adultscore=0 spamscore=0 phishscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605010030", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Consider this test from pr109038:\n\nunsigned\nfoo (unsigned int a)\n{\n unsigned int b = a & 0x00FFFFFF;\n unsigned int c = ((b & 0x000000FF) << 8\n | (b & 0x0000FF00) << 8\n | (b & 0x00FF0000) << 8\n | (b & 0xFF000000) >> 24);\n return c;\n}\n\nWe currently generate something like this for rv64gcbv:\n\n slli a0,a0,40\n srli a0,a0,40\n roriw a0,a0,24\n ret\n\nTwo key points. The first two shifts clear the upper 40 bits. The roriw \nis a rotation of the low 32 bits by 24 positions with a sign extension \nfrom bit 31 into bits 32..63.\n\nSo we're going to have bit 31 defining bits 32..63 after the rotation \nand the low 8 bits will be clear. So we can just do\n\n slliw a0,a0,8\n\n\n\nNote that doesn't even strictly need bitmanip, though the original \nsequence did. The mask is always going to be a consecutive run of on \nbits including bits 31..63. The number of bits off in the mask must be \n32 - rotate count. Put it all together and you get a nice slliw.\n\nEssentially it's a 3->1 combination, so a define_insn is sufficient.\n\nAn earlier version of this patch has been in my tester for weeks, so the \nusual testing has been performed. But that version was meaningfully \ndifferent (left a trailing andi and was impemented as a splitter). So I \nconsider most of that testing invalid. This version did go through \nriscv32-elf and riscv64-elf without regressions and I'll be waiting on \nthe upstream pre-commit to render a verdict.\n\nJeff", "diff": "diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex c9561b0b6228..30046e1fb69e 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1441,3 +1441,25 @@ (define_split\n [(set (match_dup 4) (and:X (not:X (match_dup 2)) (match_dup 1)))\n (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n \n+\n+;; This would typically be a 3 instruction sequence. Two shifts plus\n+;; the rotate. But with bits 32..63 defined by value in bit 31, we can\n+;; use the sign extending shifts/rotates. And with the number of low bits\n+;; masked off by the AND matching the final shift count we can turn this mess\n+;; into simple \"w\" mode left shift.\n+(define_insn \"rotate_with_masking_to_shift\"\n+ [(set (match_operand:DI 0 \"register_operand\" \"=r\")\n+ (sign_extend:DI (and:SI (rotatert:SI (match_operand:SI 1 \"register_operand\" \"r\")\n+ (match_operand 2 \"const_int_operand\" \"i\"))\n+ (match_operand 3 \"consecutive_bits_operand\" \"i\"))))]\n+ \"(TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)\n+ && INTVAL (operands[2]) < 32\n+ && (INTVAL (operands[3]) & HOST_WIDE_INT_C (0xffffffff80000000)) == HOST_WIDE_INT_C (0xffffffff80000000)\n+ && ctz_hwi (INTVAL (operands[3])) == 32 - INTVAL (operands[2]))\"\n+{\n+ operands[2] = GEN_INT (32 - INTVAL (operands[2]));\n+ return \"slliw\\t%0,%1,%2\";\n+}\n+ [(set_attr \"type\" \"shift\")\n+ (set_attr \"mode\" \"DI\")])\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr109038.c b/gcc/testsuite/gcc.target/riscv/pr109038.c\nnew file mode 100644\nindex 000000000000..6a4e82673fb9\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr109038.c\n@@ -0,0 +1,21 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+unsigned\n+foo (unsigned int a)\n+{\n+ unsigned int b = a & 0x00FFFFFF;\n+ unsigned int c = ((b & 0x000000FF) << 8\n+ | (b & 0x0000FF00) << 8\n+ | (b & 0x00FF0000) << 8\n+ | (b & 0xFF000000) >> 24);\n+ return c;\n+}\n+\n+/* These don't have the trailing \"w\" so that they work for\n+ both rv32 and rv64. */\n+/* { dg-final { scan-assembler-not \"srli\" } } */\n+/* { dg-final { scan-assembler-not \"rori\" } } */\n+/* { dg-final { scan-assembler-times \"sll\" 1 } } */\n", "prefixes": [ "to-be-committed", "RISC-V", "PR", "tree-optimization/109038" ] }