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GET /api/1.1/patches/2231600/?format=api
{ "id": 2231600, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231600/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/d4db1216-a833-4a77-b3eb-b8b292eb4779@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<d4db1216-a833-4a77-b3eb-b8b292eb4779@oss.qualcomm.com>", "date": "2026-04-30T22:27:03", "name": "[to-be-committed,V3,RISC-V,PR,rtl-optimization/96692] Improve xor+xor+ior sequence when possible", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dabd42050682760def0ecd5870ea1fbe09d2f797", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/d4db1216-a833-4a77-b3eb-b8b292eb4779@oss.qualcomm.com/mbox/", "series": [ { "id": 502400, "url": "http://patchwork.ozlabs.org/api/1.1/series/502400/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502400", "date": "2026-04-30T22:27:03", "name": "[to-be-committed,V3,RISC-V,PR,rtl-optimization/96692] Improve xor+xor+ior sequence when possible", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502400/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231600/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231600/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Qib+OHxP;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=EfcM2IPs;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------LvPNzZW0flX0cCf0CGMEvJzd\"", "Message-ID": "<d4db1216-a833-4a77-b3eb-b8b292eb4779@oss.qualcomm.com>", "Date": "Thu, 30 Apr 2026 16:27:03 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Subject": "[to-be-committed][V3][RISC-V][PR rtl-optimization/96692] Improve\n xor+xor+ior sequence when possible", "X-Authority-Analysis": "v=2.4 cv=bJcm5v+Z c=1 sm=1 tr=0 ts=69f3d73a cx=c_pps\n a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=AOjzq2pRDEudCHpJCioA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=dchKkLRZ2pBP7s9pDGoA:9 a=B2y7HmGcmWMA:10 a=vBUdepa8ALXHeOFLBtFW:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDMwMDIzMiBTYWx0ZWRfXzh+KJjVQ44LZ\n Xaz5CvcG3doKKykUKghXgY4i0N2GKw87a42zrdGKtFUzmmmIOR+eLfQ1FbSQShXTPOui6rB1Yw5\n ad7IvBNpvzoPyqm7K5LAZPBFilhsN/3SXILSIMfLDV5LqwIgZJS8PK598wORVg2p28ps3QGphFs\n bKYwRGxUAfajnHo0DZQLUUkVjvRTnFDyaj39UX4oj3AuHnoKcraXjUIGD5hG7blJt9OTZvGFk9I\n 297/6vsktZRQz984cjbyK/J5307g5LD7Sg+3BIaoFbIV0CQ4ILgCGOOjqloxhW5BAWLRJwgKzpj\n HuC824D0T70p8rUzDSmkzMJZ+1b9hnGQt1tGt7vLmOVZb4o6/EJNUJIxdfVJkKuEyIcdxGCJ19S\n DEhqmAImXNe3SwXt7YxNZkSKyFVsGCSWB4NWda45a2Bo+Uo8jO7pMf86vidn1d0Gygaex95mrqz\n UwlGQjr8vZdRanbrF6A==", "X-Proofpoint-GUID": "0XXNOFowxpda2eork8HlM2_W2iQwBzxM", "X-Proofpoint-ORIG-GUID": "0XXNOFowxpda2eork8HlM2_W2iQwBzxM", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-30_06,2026-04-30_02,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 bulkscore=0 clxscore=1015 suspectscore=0 adultscore=0\n lowpriorityscore=0 impostorscore=0 phishscore=0 malwarescore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604300232", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "So the V2 patch landed in the pre-commit system at a point where it had \na failing baseline build; as a result no tests were run. Sigh. I'd \nrather have the system hold the patch until it had a valid baseline \nbuild, but it is what it is. So no changes, just reposting to get it \nrunning in the pre-commit CI system.\n\n--\n\n\nConsider this code:\n\nint f(int a, int b, int c)\n{\n return (a ^ b) ^ (a | c);\n}\n\n\nFor RISC-V we generate something like this:\n\n xor a1,a0,a1\n or a0,a0,a2\n xor a0,a1,a0\n\nBut this would be better:\n\n andn a0,a2,a0\n xor a0,a0,a1\n\nIt looks like Roger tackled this earlier with splitters for x86. I'd \nhave leaned more towards simplify-rtx, but there may be secondary \nconcerns at play. So I'll attack in the RISC-V target files in a \nsimilar manner.\n\nThe patch, but not the testcase, have been in my tester for a while, so \nit's been bootstrapped and regression tested on the Pioneer and BPI-F3 \nboard and regression tested on riscv32-elf and riscv64-elf. Obviously \nI'll wait for pre-commit CI before moving forward.\nPR rtl-optimization/96692\ngcc/\n\t* config/riscv/bitmanip.md (xor+xor+ior splitters): New splitters\n\tthat ultimately generate andn+xor when possible.\n\ngcc/testsuite\n\n\t* gcc.target/riscv/pr96692.c: New test.", "diff": "diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex c9561b0b622..79ab17b6a60 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1441,3 +1441,26 @@ (define_split\n operands[3] = gen_lowpart (DImode, operands[3]);\n operands[6] = gen_lowpart (SImode, operands[5]);\n })\n+\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+ (xor:X (xor:X (ior:X (match_operand:X 1 \"register_operand\")\n+ (match_operand:X 2 \"register_operand\"))\n+ (match_dup 1))\n+ (match_operand:X 3 \"register_operand\")))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"TARGET_ZBB || TARGET_ZBKB\"\n+ [(set (match_dup 4) (and:X (not:X (match_dup 1)) (match_dup 2)))\n+ (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n+\n+(define_split\n+ [(set (match_operand:X 0 \"register_operand\")\n+ (xor:X (xor:X (ior:X (match_operand:X 1 \"register_operand\")\n+ (match_operand:X 2 \"register_operand\"))\n+ (match_dup 2))\n+ (match_operand:X 3 \"register_operand\")))\n+ (clobber (match_operand:X 4 \"register_operand\"))]\n+ \"TARGET_ZBB || TARGET_ZBKB\"\n+ [(set (match_dup 4) (and:X (not:X (match_dup 2)) (match_dup 1)))\n+ (set (match_dup 0) (xor:X (match_dup 4) (match_dup 3)))])\n+\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr96692.c b/gcc/testsuite/gcc.target/riscv/pr96692.c\nnew file mode 100644\nindex 00000000000..650f4f0f80d\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr96692.c\n@@ -0,0 +1,12 @@\n+/* { dg-do compile } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" { target rv64 } } */\n+/* { dg-additional-options \"-march=rv32gcb_zicond -mabi=ilp32\" { target rv32 } } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" } } */\n+\n+int f(int a, int b, int c)\n+{\n+ return (a ^ b) ^ (a | c);\n+}\n+\n+/* { dg-final { scan-assembler-times \"xor\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"andn\\t\" 1 } } */\n", "prefixes": [ "to-be-committed", "V3", "RISC-V", "PR", "rtl-optimization/96692" ] }