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GET /api/1.1/patches/2231057/?format=api
{ "id": 2231057, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231057/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430095202.1167651-3-amhetre@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/1.1/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260430095202.1167651-3-amhetre@nvidia.com>", "date": "2026-04-30T09:52:01", "name": "[V3,2/3] memory: tegra: Wire up system sleep PM ops", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ea1ac3faf12eb2bd608352253f1730c3e29a0630", "submitter": { "id": 75198, "url": "http://patchwork.ozlabs.org/api/1.1/people/75198/?format=api", "name": "Ashish Mhetre", "email": "amhetre@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260430095202.1167651-3-amhetre@nvidia.com/mbox/", "series": [ { "id": 502262, "url": "http://patchwork.ozlabs.org/api/1.1/series/502262/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=502262", "date": "2026-04-30T09:52:01", "name": "memory: tegra: Restore MC state on system resume", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502262/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231057/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231057/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-tegra+bounces-14084-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=ZWAlNLm5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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pr=C", "From": "Ashish Mhetre <amhetre@nvidia.com>", "To": "<krzk@kernel.org>, <thierry.reding@kernel.org>, <jonathanh@nvidia.com>", "CC": "<ketanp@nvidia.com>, <linux-kernel@vger.kernel.org>,\n\t<linux-tegra@vger.kernel.org>, Ashish Mhetre <amhetre@nvidia.com>", "Subject": "[PATCH V3 2/3] memory: tegra: Wire up system sleep PM ops", "Date": "Thu, 30 Apr 2026 09:52:01 +0000", "Message-ID": "<20260430095202.1167651-3-amhetre@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260430095202.1167651-1-amhetre@nvidia.com>", "References": "<20260430095202.1167651-1-amhetre@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH1PEPF0000A348:EE_|CH1PPF2C6B99E0C:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5b30edf5-43ad-43a6-1fa4-08dea69e3667", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|376014|36860700016|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tJLIoAJuqxNpN8jqCxZyQsFO7e/1zv8+PLBxJbsXAGxMvBImzmfOBbdoC50qh67nTNCD7zeQi3qCW7kAY3hzrC1S7GUF06dz9Db828F2q+Xl2ZMPSMsfuDHgw78OvvgItIBZeKHPIOIZiicraN3NYpzqIeQVGaun5vvEORUzxYJxiMvmxDQI6Y0QYa7vPpq3+8O3BMYwrzwujS4dtxF98UVJLaYM1jHGVkpn4MFOfSZIgnYZVjnGc1h3h2P169YBWPow8g0bQ2O2qGivdB/ejaQ5+k2HmrxUwCK3kv0Mk6dEp5TkdhSqYjreZbeMq23PJPLYv743W1qPPsMg3DAYNQj51qWVp8UXvz6aXRbMWNKv035Uh7uk4WPo2X72gNcmdf/BA+lBSvkQiArHnpBSCrOZKA1PLkyOOjmPRezIxkNHxg9ocXIh404YY7/7dtTZW+8E77R4lzE8WrPinAOnOfQFENnTxwCDBlhDAQlllGTQ2G0fXwmRbMMD2/UW2/GxCKpBFmOi/G3OIEwPvB0Pi13VGTJCRTUx8CjTR3CTaQhtNTjPvHbGrdnbKsY6b2pg//Hq9VW36g1RwyWcuQGD7FmajpAJAW8Usdbz8/e84BiiwZXTQcSBs9Sgdavx16ZBcFFq6BpDql7wca965aLLYZ5Cd7XlGkMbDMgKpYHVfpClP2BIyi/VDuALm2FL36caNp3Mn3o8xcw2rAZtz+UKUV5D2/Z9mbbNrjkeY4/mgpzTV4HQWbhGWGHmuV3dKzb1DkbItBPS6QN8CpCJ6B7oadQ==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700016)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tgI/aLRME8VufWqKSsNoE217NGZpIveWhxj0TWpLLDMj4RHxJLtRauonCERDDXcxUzUbJoEjP3zat4DN/m0nYr1pCHTt2uH0y7+41xTJEzpryt/OATHvyxgUzatFSneJjvUyX1buDhdGvpCN76+kow1Fdk8rJq+oCYF1VWKOqr+jQwPVF8SINle8FTpunqF+mZiwZkkeqL+A34aTezAt+OsSV+E9yeJ9lkTS3teH/66LfrYUv3XYbkcQlxcxA2S/CqCZRjjgaYf+WQqaF4esd6YLLyY3lUFd1WmgGZ5INmAzR5w/Qi5GkJ+8jMlZvM2mPnGqkGiZNCMVBJOIExZRbEX2WL0/MxpMFaN534ZvwS+GCAOtxZutmk0Nz9+TV9+2tn607Srzb0LkbzaKp+IAPEmtIduZ6dmbkGtMcuJnT2bPthAH0V04FJZZcszpQLQyO", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2026 09:52:37.9361\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5b30edf5-43ad-43a6-1fa4-08dea69e3667", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tCH1PEPF0000A348.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH1PPF2C6B99E0C" }, "content": "The tegra-mc platform driver does not register any dev_pm_ops, so the\nSoC-specific ->resume() is never invoked (e.g. tegra186_mc_resume) on\nsystem wake. On Tegra186 and later this means MC client Stream-ID\noverride registers are not reprogrammed, and clients behind the ARM\nSMMU fault on the first DMA after resume.\n\nRegister a dev_pm_ops on the tegra-mc driver and route the system\nresume callback into mc->soc->ops->resume() so the existing SID\nrestore path runs again on wake.\n\nNo suspend callback is needed as the resume path reprograms all MC\nstate from the static SoC tables, so there is nothing to save.\n\nFixes: fe3b082a6eb8 (\"memory: tegra: Add SID override programming for MC clients\")\nSigned-off-by: Ashish Mhetre <amhetre@nvidia.com>\n---\n drivers/memory/tegra/mc.c | 14 ++++++++++++++\n 1 file changed, 14 insertions(+)", "diff": "diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c\nindex d620660da331..64e41338cdf2 100644\n--- a/drivers/memory/tegra/mc.c\n+++ b/drivers/memory/tegra/mc.c\n@@ -13,6 +13,7 @@\n #include <linux/of.h>\n #include <linux/of_platform.h>\n #include <linux/platform_device.h>\n+#include <linux/pm.h>\n #include <linux/slab.h>\n #include <linux/sort.h>\n #include <linux/tegra-icc.h>\n@@ -1010,10 +1011,23 @@ static void tegra_mc_sync_state(struct device *dev)\n \t\ticc_sync_state(dev);\n }\n \n+static int tegra_mc_resume(struct device *dev)\n+{\n+\tstruct tegra_mc *mc = dev_get_drvdata(dev);\n+\n+\tif (mc->soc->ops && mc->soc->ops->resume)\n+\t\tmc->soc->ops->resume(mc);\n+\n+\treturn 0;\n+}\n+\n+static DEFINE_SIMPLE_DEV_PM_OPS(tegra_mc_pm_ops, NULL, tegra_mc_resume);\n+\n static struct platform_driver tegra_mc_driver = {\n \t.driver = {\n \t\t.name = \"tegra-mc\",\n \t\t.of_match_table = tegra_mc_of_match,\n+\t\t.pm = pm_sleep_ptr(&tegra_mc_pm_ops),\n \t\t.suppress_bind_attrs = true,\n \t\t.sync_state = tegra_mc_sync_state,\n \t},\n", "prefixes": [ "V3", "2/3" ] }