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GET /api/1.1/patches/2231056/?format=api
{ "id": 2231056, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2231056/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260430-952netc-v1-1-9a0b2641a56c@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260430-952netc-v1-1-9a0b2641a56c@nxp.com>", "date": "2026-04-30T10:04:10", "name": "[v3] net: fsl_enetc: Add support for i.MX952", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "94b2baaf4ba0fcf83c9b07f4b3a8ca1eef7fb5ff", "submitter": { "id": 80695, "url": "http://patchwork.ozlabs.org/api/1.1/people/80695/?format=api", "name": "Alice Guo (OSS)", "email": "alice.guo@oss.nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260430-952netc-v1-1-9a0b2641a56c@nxp.com/mbox/", "series": [ { "id": 502261, "url": "http://patchwork.ozlabs.org/api/1.1/series/502261/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502261", "date": "2026-04-30T10:04:10", "name": "[v3] net: fsl_enetc: Add support for i.MX952", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502261/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231056/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231056/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=NXP1.onmicrosoft.com header.i=@NXP1.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector1-NXP1-onmicrosoft-com\n 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Schulz <quentin.schulz@cherry.de>,\n Christian Marangi <ansuelsmth@gmail.com>, Ye Li <ye.li@nxp.com>,\n Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>, Yao Zi <me@ziyao.cc>,\n Robert Marko <robert.marko@sartura.hr>, Peng Fan <peng.fan@nxp.com>,\n Heiko Thiery <heiko.thiery@gmail.com>,\n Marek Vasut <marek.vasut+renesas@mailbox.org>,\n Thomas Schaefer <thomas.schaefer@kontron.com>,\n Andrew Goodbody <andrew.goodbody@linaro.org>, Jacky Bai <ping.bai@nxp.com>,\n Alice Guo <alice.guo@nxp.com>", "X-Mailer": "b4 0.15.2", "X-ClientProxiedBy": "MA5PR01CA0013.INDPRD01.PROD.OUTLOOK.COM\n (2603:1096:a01:177::17) To PAXPR04MB9644.eurprd04.prod.outlook.com\n (2603:10a6:102:242::11)", "MIME-Version": "1.0", "X-MS-Exchange-MessageSentRepresentingType": "1", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PAXPR04MB9644:EE_|VI0PR04MB12156:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3340217f-fb3f-40ea-3835-08dea69f792e", "X-MS-Exchange-SharedMailbox-RoutingAgent-Processed": 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"X-OriginatorOrg": "oss.nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3340217f-fb3f-40ea-3835-08dea69f792e", "X-MS-Exchange-CrossTenant-AuthSource": "PAXPR04MB9644.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "30 Apr 2026 10:01:39.8171 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n pGVQEs8gl7dGq92jUXpL7RuPx2GcXpxN6wqEzPcMhivsz79rIPJSrjuEkVx3g1ziD5YAFnEPTiB02skusIw+IQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "VI0PR04MB12156", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Ye Li <ye.li@nxp.com>\n\nExtend ENETC driver to support i.MX952 platform where 2 ENETC\ncontrollers are located on different PCIe buses.\n\nKey changes:\n- Add enetc_dev_id_imx() to derive device ID from device tree \"reg\"\n property for i.MX952, mapping bus_devfn values 0x0 and 0x100 to device\n IDs 0 and 1 respectively\n- Implement imx952_netcmix_init() to configure MII protocol and PCS\n settings based on PHY mode parsed from device tree\n- Add i.MX952 to FSL_ENETC_NETC_BLK_CTRL Kconfig dependencies\n\nSigned-off-by: Ye Li <ye.li@nxp.com>\nSigned-off-by: Alice Guo <alice.guo@nxp.com>\nReviewed-by: Peng Fan <peng.fan@nxp.com>\n---\nThis is a resend of the v3 patch series with the first one patch\nremoved.\n\nThere are no other changes compared to the previous v3 submission.\n---\n drivers/net/Kconfig | 4 +-\n drivers/net/fsl_enetc.c | 28 +++++++++++++-\n drivers/net/fsl_enetc_netc_blk_ctrl.c | 72 +++++++++++++++++++++++++++++++++++\n 3 files changed, 101 insertions(+), 3 deletions(-)\n\n\n---\nbase-commit: 4433253ecf2041f9362a763bb6cb79960921ac7e\nchange-id: 20260430-952netc-168485943bab\n\nBest regards,\n-- \nAlice Guo <alice.guo@nxp.com>", "diff": "diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig\nindex 666618681df..f2e838b84de 100644\n--- a/drivers/net/Kconfig\n+++ b/drivers/net/Kconfig\n@@ -1018,8 +1018,8 @@ config FSL_ENETC\n config FSL_ENETC_NETC_BLK_CTRL\n \tbool \"NXP ENETC NETC blocks control driver\"\n \tdepends on FSL_ENETC\n-\tdepends on IMX95 || IMX94\n-\tdefault y if IMX95 || IMX94\n+\tdepends on IMX95 || IMX94 || IMX952\n+\tdefault y if IMX95 || IMX94 || IMX952\n \thelp\n \t This driver configures Integrated Endpoint Register Block (IERB) and\n \t Privileged Register Block (PRB) of NETC. For i.MX platforms, it also\ndiff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c\nindex 206f1a381bb..2e0683e8f34 100644\n--- a/drivers/net/fsl_enetc.c\n+++ b/drivers/net/fsl_enetc.c\n@@ -74,10 +74,36 @@ static int enetc_is_ls1028a(struct udevice *dev)\n \t pplat->vendor == PCI_VENDOR_ID_FREESCALE;\n }\n \n+static int enetc_dev_id_imx(struct udevice *dev)\n+{\n+\tif (IS_ENABLED(CONFIG_IMX952)) {\n+\t\tint bus_devfn;\n+\t\tu32 reg[5];\n+\t\tint error;\n+\n+\t\terror = dev_read_u32_array(dev, \"reg\", reg, ARRAY_SIZE(reg));\n+\t\tif (error)\n+\t\t\treturn error;\n+\n+\t\tbus_devfn = (reg[0] >> 8) & 0xffff;\n+\n+\t\tswitch (bus_devfn) {\n+\t\tcase 0:\n+\t\t\treturn 0;\n+\t\tcase 0x100:\n+\t\t\treturn 1;\n+\t\tdefault:\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn PCI_DEV(pci_get_devfn(dev)) >> 3;\n+}\n+\n static int enetc_dev_id(struct udevice *dev)\n {\n \tif (enetc_is_imx95(dev))\n-\t\treturn PCI_DEV(pci_get_devfn(dev)) >> 3;\n+\t\treturn enetc_dev_id_imx(dev);\n \tif (enetc_is_ls1028a(dev))\n \t\treturn PCI_FUNC(pci_get_devfn(dev));\n \ndiff --git a/drivers/net/fsl_enetc_netc_blk_ctrl.c b/drivers/net/fsl_enetc_netc_blk_ctrl.c\nindex 8577bb75632..0c87d80ea5c 100644\n--- a/drivers/net/fsl_enetc_netc_blk_ctrl.c\n+++ b/drivers/net/fsl_enetc_netc_blk_ctrl.c\n@@ -35,6 +35,7 @@\n #define MII_PROT_RGMII\t\t\t0x2\n #define MII_PROT_SERIAL\t\t0x3\n #define MII_PROT(port, prot)\t\t(((prot) & 0xf) << ((port) << 2))\n+#define MII_PROT_GET(reg, port)\t(((reg) >> ((port) << 2)) & 0xf)\n \n #define IMX95_CFG_LINK_PCS_PROT(a)\t(0x8 + (a) * 4)\n #define PCS_PROT_1G_SGMII\t\tBIT(0)\n@@ -97,6 +98,9 @@\n #define IMX94_TIMER1_ID\t\t\t1\n #define IMX94_TIMER2_ID\t\t\t2\n \n+#define IMX952_ENETC0_BUS_DEVFN\t\t0x0\n+#define IMX952_ENETC1_BUS_DEVFN\t\t0x100\n+\n /* Flags for different platforms */\n #define NETC_HAS_NETCMIX\t\tBIT(0)\n \n@@ -567,6 +571,69 @@ static int netc_prb_check_error(struct netc_blk_ctrl *priv)\n \treturn 0;\n }\n \n+static int imx952_netcmix_init(struct udevice *dev)\n+{\n+\tstruct netc_blk_ctrl *priv = dev_get_priv(dev);\n+\tofnode child, gchild;\n+\tphy_interface_t interface;\n+\tint bus_devfn, mii_proto;\n+\tu32 val;\n+\n+\t/* Default setting */\n+\tval = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII);\n+\n+\t/* Update the link MII protocol through parsing phy-mode */\n+\tdev_for_each_subnode(child, dev) {\n+\t\tif (!ofnode_is_enabled(child))\n+\t\t\tcontinue;\n+\n+\t\tofnode_for_each_subnode(gchild, child) {\n+\t\t\tif (!ofnode_is_enabled(gchild))\n+\t\t\t\tcontinue;\n+\n+\t\t\tif (!ofnode_device_is_compatible(gchild, \"pci1131,e101\"))\n+\t\t\t\tcontinue;\n+\n+\t\t\tbus_devfn = netc_of_pci_get_bus_devfn(gchild);\n+\t\t\tif (bus_devfn < 0)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tinterface = ofnode_read_phy_mode(gchild);\n+\t\t\tif (interface == -1)\n+\t\t\t\tcontinue;\n+\n+\t\t\tmii_proto = netc_get_link_mii_protocol(interface);\n+\t\t\tif (mii_proto < 0)\n+\t\t\t\treturn -EINVAL;\n+\n+\t\t\tswitch (bus_devfn) {\n+\t\t\tcase IMX952_ENETC0_BUS_DEVFN:\n+\t\t\t\tval &= ~CFG_LINK_MII_PORT_0;\n+\t\t\t\tval |= FIELD_PREP(CFG_LINK_MII_PORT_0, mii_proto);\n+\t\t\t\tbreak;\n+\t\t\tcase IMX952_ENETC1_BUS_DEVFN:\n+\t\t\t\tval &= ~CFG_LINK_MII_PORT_1;\n+\t\t\t\tval |= FIELD_PREP(CFG_LINK_MII_PORT_1, mii_proto);\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\tif (MII_PROT_GET(val, 1) == MII_PROT_SERIAL) {\n+\t\t/* Configure Link I/O variant */\n+\t\tnetc_reg_write(priv->netcmix, IMX95_CFG_LINK_IO_VAR,\n+\t\t\t IO_VAR(1, IO_VAR_16FF_16G_SERDES));\n+\t\t/* Configure Link 2 PCS protocol */\n+\t\tnetc_reg_write(priv->netcmix, IMX95_CFG_LINK_PCS_PROT(1),\n+\t\t\t PCS_PROT_2500M_SGMII);\n+\t}\n+\tnetc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);\n+\n+\treturn 0;\n+}\n+\n static const struct netc_devinfo imx95_devinfo = {\n \t.netcmix_init = imx95_netcmix_init,\n \t.ierb_init = imx95_ierb_init,\n@@ -578,9 +645,14 @@ static const struct netc_devinfo imx94_devinfo = {\n \t.xpcs_port_init = imx94_netc_xpcs_port_init,\n };\n \n+static const struct netc_devinfo imx952_devinfo = {\n+\t.netcmix_init = imx952_netcmix_init,\n+};\n+\n static const struct udevice_id netc_blk_ctrl_match[] = {\n \t{ .compatible = \"nxp,imx95-netc-blk-ctrl\", .data = (ulong)&imx95_devinfo },\n \t{ .compatible = \"nxp,imx94-netc-blk-ctrl\", .data = (ulong)&imx94_devinfo },\n+\t{ .compatible = \"nxp,imx952-netc-blk-ctrl\", .data = (ulong)&imx952_devinfo },\n \t{},\n };\n \n", "prefixes": [ "v3" ] }