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GET /api/1.1/patches/2230990/?format=api
{ "id": 2230990, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230990/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-6-biju.das.jz@bp.renesas.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430093422.74812-6-biju.das.jz@bp.renesas.com>", "date": "2026-04-30T09:34:10", "name": "[v4,5/7] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f4bf6fa2978f5eb3a7a4dc89fbf09136f5b4da01", "submitter": { "id": 87968, "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api", "name": "Biju", "email": "biju.das.au@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-6-biju.das.jz@bp.renesas.com/mbox/", "series": [ { "id": 502254, "url": "http://patchwork.ozlabs.org/api/1.1/series/502254/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254", "date": "2026-04-30T09:34:06", "name": "Add Renesas RZ/G3L PINCONTROL support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502254/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230990/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230990/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35855-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com 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"X-Google-Original-From": "Biju <biju.das.jz@bp.renesas.com>", "To": "Geert Uytterhoeven <geert+renesas@glider.be>,\n\tLinus Walleij <linusw@kernel.org>,\n\tMagnus Damm <magnus.damm@gmail.com>", "Cc": "Biju Das <biju.das.jz@bp.renesas.com>,\n\tlinux-renesas-soc@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tPrabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,\n\tBiju Das <biju.das.au@gmail.com>", "Subject": "[PATCH v4 5/7] pinctrl: renesas: rzg2l: Add support for RZ/G3L SoC", "Date": "Thu, 30 Apr 2026 10:34:10 +0100", "Message-ID": "<20260430093422.74812-6-biju.das.jz@bp.renesas.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260430093422.74812-1-biju.das.jz@bp.renesas.com>", "References": "<20260430093422.74812-1-biju.das.jz@bp.renesas.com>", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "From: Biju Das <biju.das.jz@bp.renesas.com>\n\nAdd pinctrl driver support for RZ/G3L SoC.\n\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv3->v4:\n * Dropped extra white spaces in SD0_CLK and SD0_DATA0 entries.\n * Renamed SD0_DATA* → SD0_DAT* to match the pin function spreadsheet.\n * Renamed SCIF_{RXD,TXD} → SCIF0_{RXD,TXD} to match the pin function\n spreadsheet.\n * .pin_to_oen_bit = rzg2l_pin_to_oen_bit() and dropped oen_max_port from\n rzg3l_hwcfg.\nv2->v3:\n * Updated r9a08g046_gpio_configs[] by replacing the typo AWO->ISO.\n * Added PIN_CFG_PUPD to RZG3L_MPXED_ETH_PIN_FUNCS macro\n * Replaced RZG2L_MPXED_COMMON_PIN_FUNCS->RZG3L_MPXED_PIN_FUNCS in \n RZG3L_MPXED_PIN_FUNCS_POC macro for setting power source for pins.\nv1->v2:\n * No change\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 228 ++++++++++++++++++++++++\n 1 file changed, 228 insertions(+)", "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 2a46ba7b3709..004096d5d1d1 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -26,6 +26,7 @@\n #include <linux/pinctrl/pinctrl.h>\n #include <linux/pinctrl/pinmux.h>\n \n+#include <dt-bindings/pinctrl/renesas,r9a08g046-pinctrl.h>\n #include <dt-bindings/pinctrl/renesas,r9a09g047-pinctrl.h>\n #include <dt-bindings/pinctrl/renesas,r9a09g057-pinctrl.h>\n #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>\n@@ -93,6 +94,18 @@\n \n #define RZG2L_MPXED_ETH_PIN_FUNCS(x)\t((x) | PIN_CFG_NF)\n \n+#define RZG3L_MPXED_ETH_PIN_FUNCS(ether) \\\n+\t\t\t\t\t(PIN_CFG_IO_VMC_##ether | \\\n+\t\t\t\t\t PIN_CFG_IOLH_C | \\\n+\t\t\t\t\t PIN_CFG_PUPD | \\\n+\t\t\t\t\t PIN_CFG_NF)\n+\n+#define RZG3L_MPXED_PIN_FUNCS(group)\t(RZG2L_MPXED_COMMON_PIN_FUNCS(group) | \\\n+\t\t\t\t\t PIN_CFG_SOFT_PS)\n+\n+#define RZG3L_MPXED_PIN_FUNCS_POC(grp, poc) (RZG2L_MPXED_COMMON_PIN_FUNCS(grp) | \\\n+\t\t\t\t\t PIN_CFG_PVDD1833_OTH_##poc##_POC)\n+\n #define PIN_CFG_PIN_MAP_MASK\t\tGENMASK_ULL(61, 54)\n #define PIN_CFG_PIN_REG_MASK\t\tGENMASK_ULL(53, 46)\n #define PIN_CFG_MASK\t\t\tGENMASK_ULL(31, 0)\n@@ -230,6 +243,7 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {\n * @eth_poc: ETH_POC register offset\n * @oen: OEN register offset\n * @qspi: QSPI register offset\n+ * @other_poc: OTHER_POC register offset\n */\n struct rzg2l_register_offsets {\n \tu16 pwpr;\n@@ -237,6 +251,7 @@ struct rzg2l_register_offsets {\n \tu16 eth_poc;\n \tu16 oen;\n \tu16 qspi;\n+\tu16 other_poc;\n };\n \n /**\n@@ -337,6 +352,7 @@ struct rzg2l_pinctrl_pin_settings {\n * @nod: NOD registers cache\n * @sd_ch: SD_CH registers cache\n * @eth_poc: ET_POC registers cache\n+ * @other_poc: OTHER_POC register cache\n * @oen: Output Enable register cache\n * @qspi: QSPI registers cache\n */\n@@ -354,6 +370,7 @@ struct rzg2l_pinctrl_reg_cache {\n \tu8\tsd_ch[2];\n \tu8\teth_poc[2];\n \tu8\toen;\n+\tu8 other_poc;\n \tu8\tqspi;\n };\n \n@@ -403,6 +420,60 @@ static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,\n \treturn 0;\n }\n \n+static const u64 r9a08g046_variable_pin_cfg[] = {\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PA, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0) | PIN_CFG_OEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PB, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PD, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 0, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 1, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1) | PIN_CFG_OEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 2, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 3, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 4, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 5, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 6, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PE, 7, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 0, RZG3L_MPXED_PIN_FUNCS(B)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 6, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PG, 7, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 0, RZG3L_MPXED_PIN_FUNCS(B)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 1, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 2, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 3, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 4, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PH, 5, RZG3L_MPXED_PIN_FUNCS(B) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 0, RZG3L_MPXED_PIN_FUNCS(A) | PIN_CFG_IEN),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 1, RZG3L_MPXED_PIN_FUNCS(A)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 2, RZG3L_MPXED_PIN_FUNCS(A)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 3, RZG3L_MPXED_PIN_FUNCS(A)),\n+\tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3L_PJ, 4, RZG3L_MPXED_PIN_FUNCS(A)),\n+};\n+\n static const u64 r9a09g047_variable_pin_cfg[] = {\n \tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 0, RZV2H_MPXED_PIN_FUNCS | PIN_CFG_IEN),\n \tRZG2L_VARIABLE_PIN_CFG_PACK(RZG3E_PA, 1, RZV2H_MPXED_PIN_FUNCS),\n@@ -2130,6 +2201,70 @@ static const u64 r9a09g047_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(4, 0x3c, RZV2H_MPXED_PIN_FUNCS),\t/* PS */\n };\n \n+static const char * const rzg3l_gpio_names[] = {\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"P20\", \"P21\", \"P22\", \"P23\", \"P24\", \"P25\", \"P26\", \"P27\",\n+\t\"P30\", \"P31\", \"P32\", \"P33\", \"P34\", \"P35\", \"P36\", \"P37\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"P50\", \"P51\", \"P52\", \"P53\", \"P54\", \"P55\", \"P56\", \"P57\",\n+\t\"P60\", \"P61\", \"P62\", \"P63\", \"P64\", \"P65\", \"P66\", \"P67\",\n+\t\"P70\", \"P71\", \"P72\", \"P73\", \"P74\", \"P75\", \"P76\", \"P77\",\n+\t\"P80\", \"P81\", \"P82\", \"P83\", \"P84\", \"P85\", \"P86\", \"P87\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"PA0\", \"PA1\", \"PA2\", \"PA3\", \"PA4\", \"PA5\", \"PA6\", \"PA7\",\n+\t\"PB0\", \"PB1\", \"PB2\", \"PB3\", \"PB4\", \"PB5\", \"PB6\", \"PB7\",\n+\t\"PC0\", \"PC1\", \"PC2\", \"PC3\", \"PC4\", \"PC5\", \"PC6\", \"PC7\",\n+\t\"PD0\", \"PD1\", \"PD2\", \"PD3\", \"PD4\", \"PD5\", \"PD6\", \"PD7\",\n+\t\"PE0\", \"PE1\", \"PE2\", \"PE3\", \"PE4\", \"PE5\", \"PE6\", \"PE7\",\n+\t\"PF0\", \"PF1\", \"PF2\", \"PF3\", \"PF4\", \"PF5\", \"PF6\", \"PF7\",\n+\t\"PG0\", \"PG1\", \"PG2\", \"PG3\", \"PG4\", \"PG5\", \"PG6\", \"PG7\",\n+\t\"PH0\", \"PH1\", \"PH2\", \"PH3\", \"PH4\", \"PH5\", \"PH6\", \"PH7\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"PJ0\", \"PJ1\", \"PJ2\", \"PJ3\", \"PJ4\", \"PJ5\", \"PJ6\", \"PJ7\",\n+\t\"PK0\", \"PK1\", \"PK2\", \"PK3\", \"PK4\", \"PK5\", \"PK6\", \"PK7\",\n+\t\"PL0\", \"PL1\", \"PL2\", \"PL3\", \"PL4\", \"PL5\", \"PL6\", \"PL7\",\n+\t\"PM0\", \"PM1\", \"PM2\", \"PM3\", \"PM4\", \"PM5\", \"PM6\", \"PM7\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"\", \"\", \"\", \"\", \"\", \"\", \"\", \"\",\n+\t\"PS0\", \"PS1\", \"PS2\", \"PS3\", \"PS4\", \"PS5\", \"PS6\", \"PS7\",\n+};\n+\n+static const u64 r9a08g046_gpio_configs[] = {\n+\t0x0,\n+\t0x0,\n+\tRZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN),\t/* P2 */\n+\tRZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */\n+\t0x0,\n+\tRZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */\n+\tRZG2L_GPIO_PORT_PACK(7, 0x26, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P6 */\n+\tRZG2L_GPIO_PORT_PACK(8, 0x27, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P7 */\n+\tRZG2L_GPIO_PORT_PACK(6, 0x28, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P8 */\n+\t0x0,\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2a),\t\t\t\t/* PA */\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2b),\t\t\t\t/* PB */\n+\tRZG2L_GPIO_PORT_PACK(3, 0x2c, RZG3L_MPXED_ETH_PIN_FUNCS(ETH0)),\t/* PC */\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2d),\t\t\t\t/* PD */\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x2e),\t\t\t\t/* PE */\n+\tRZG2L_GPIO_PORT_PACK(3, 0x2f, RZG3L_MPXED_ETH_PIN_FUNCS(ETH1)),\t/* PF */\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(8, 0x30),\t\t\t\t/* PG */\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(6, 0x31),\t\t\t\t/* PH */\n+\t0x0,\n+\tRZG2L_GPIO_PORT_PACK_VARIABLE(5, 0x33),\t\t\t\t/* PJ */\n+\tRZG2L_GPIO_PORT_PACK(4, 0x34, RZG3L_MPXED_PIN_FUNCS_POC(B, ISO)), /* PK */\n+\tRZG2L_GPIO_PORT_PACK(5, 0x35, RZG3L_MPXED_PIN_FUNCS(C)),\t/* PL */\n+\tRZG2L_GPIO_PORT_PACK(8, 0x36, RZG3L_MPXED_PIN_FUNCS(C)),\t/* PM */\n+\t0x0,\n+\t0x0,\n+\t0x0,\n+\t0x0,\n+\t0x0,\n+\tRZG2L_GPIO_PORT_PACK(2, 0x3c, RZG3L_MPXED_PIN_FUNCS(A)),\t/* PS */\n+};\n+\n static const char * const rzv2h_gpio_names[] = {\n \t\"P00\", \"P01\", \"P02\", \"P03\", \"P04\", \"P05\", \"P06\", \"P07\",\n \t\"P10\", \"P11\", \"P12\", \"P13\", \"P14\", \"P15\", \"P16\", \"P17\",\n@@ -2468,6 +2603,37 @@ static struct rzg2l_dedicated_configs rzg3e_dedicated_pins[] = {\n \t (PIN_CFG_IOLH_RZV2H | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n };\n \n+static const struct rzg2l_dedicated_configs rzg3l_dedicated_pins[] = {\n+\t{ \"WDTOVF_N\", RZG2L_SINGLE_PIN_PACK(0x5, 0,\n+\t (PIN_CFG_IOLH_A | PIN_CFG_WDTOVF_N_POC)) },\n+\t{ \"SCIF0_RXD\", RZG2L_SINGLE_PIN_PACK(0x6, 0,\n+\t (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },\n+\t{ \"SCIF0_TXD\", RZG2L_SINGLE_PIN_PACK(0x6, 1,\n+\t (PIN_CFG_IOLH_A | PIN_CFG_PUPD | PIN_CFG_PVDD1833_OTH_AWO_POC)) },\n+\t{ \"SD0_CLK\", RZG2L_SINGLE_PIN_PACK(0x9, 0, PIN_CFG_IOLH_B) },\n+\t{ \"SD0_CMD\", RZG2L_SINGLE_PIN_PACK(0x9, 1,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_RST#\", RZG2L_SINGLE_PIN_PACK(0x9, 2, PIN_CFG_IOLH_B) },\n+\t{ \"SD0_DS\", RZG2L_SINGLE_PIN_PACK(0x9, 5,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT0\", RZG2L_SINGLE_PIN_PACK(0x0a, 0,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT1\", RZG2L_SINGLE_PIN_PACK(0x0a, 1,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT2\", RZG2L_SINGLE_PIN_PACK(0x0a, 2,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT3\", RZG2L_SINGLE_PIN_PACK(0x0a, 3,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT4\", RZG2L_SINGLE_PIN_PACK(0x0a, 4,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT5\", RZG2L_SINGLE_PIN_PACK(0x0a, 5,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT6\", RZG2L_SINGLE_PIN_PACK(0x0a, 6,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+\t{ \"SD0_DAT7\", RZG2L_SINGLE_PIN_PACK(0x0a, 7,\n+\t (PIN_CFG_IOLH_B | PIN_CFG_IEN | PIN_CFG_PUPD)) },\n+};\n+\n static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)\n {\n \tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];\n@@ -3025,6 +3191,9 @@ static int rzg2l_pinctrl_probe(struct platform_device *pdev)\n \tBUILD_BUG_ON(ARRAY_SIZE(r9a08g045_gpio_configs) * RZG2L_PINS_PER_PORT >\n \t\t ARRAY_SIZE(rzg2l_gpio_names));\n \n+\tBUILD_BUG_ON(ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT >\n+\t\t ARRAY_SIZE(rzg3l_gpio_names));\n+\n \tBUILD_BUG_ON(ARRAY_SIZE(r9a09g047_gpio_configs) * RZG2L_PINS_PER_PORT >\n \t\t ARRAY_SIZE(rzg3e_gpio_names));\n \n@@ -3337,6 +3506,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)\n \tif (regs->qspi)\n \t\tcache->qspi = readb(pctrl->base + regs->qspi);\n \tcache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);\n+\tif (regs->other_poc)\n+\t\tcache->other_poc = readb(pctrl->base + regs->other_poc);\n \n \tif (!atomic_read(&pctrl->wakeup_path))\n \t\tclk_disable_unprepare(pctrl->clk);\n@@ -3363,6 +3534,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)\n \n \tif (regs->qspi)\n \t\twriteb(cache->qspi, pctrl->base + regs->qspi);\n+\tif (regs->other_poc)\n+\t\twriteb(cache->other_poc, pctrl->base + regs->other_poc);\n \n \traw_spin_lock_irqsave(&pctrl->lock, flags);\n \trzg2l_oen_write_with_pwpr(pctrl, cache->oen);\n@@ -3431,6 +3604,40 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {\n \t.oen_max_pin = 0,\n };\n \n+static const struct rzg2l_hwcfg rzg3l_hwcfg = {\n+\t.regs = {\n+\t\t.pwpr = 0x3000,\n+\t\t.sd_ch = 0x3004,\n+\t\t.eth_poc = 0x3010,\n+\t\t.oen = 0x3018,\n+\t\t.other_poc = OTHER_POC,\n+\t},\n+\t.iolh_groupa_ua = {\n+\t\t/* 1v8 power source */\n+\t\t[RZG2L_IOLH_IDX_1V8] = 2200, 4400, 9000, 10000,\n+\t\t/* 3v3 power source */\n+\t\t[RZG2L_IOLH_IDX_3V3] = 1900, 4000, 8000, 9000,\n+\t},\n+\t.iolh_groupb_ua = {\n+\t\t/* 1v8 power source */\n+\t\t[RZG2L_IOLH_IDX_1V8] = 7000, 8000, 9000, 10000,\n+\t\t/* 3v3 power source */\n+\t\t[RZG2L_IOLH_IDX_3V3] = 4000, 6000, 8000, 9000,\n+\t},\n+\t.iolh_groupc_ua = {\n+\t\t/* 1v8 power source */\n+\t\t[RZG2L_IOLH_IDX_1V8] = 5200, 6000, 6550, 6800,\n+\t\t/* 2v5 source */\n+\t\t[RZG2L_IOLH_IDX_2V5] = 4700, 5300, 5800, 6100,\n+\t\t/* 3v3 power source */\n+\t\t[RZG2L_IOLH_IDX_3V3] = 4500, 5200, 5700, 6050,\n+\t},\n+\t.tint_start_index = 17,\n+\t.drive_strength_ua = true,\n+\t.func_base = 0,\n+\t.oen_max_pin = 1, /* Pin 1 of P{B,E}1_ISO is the maximum OEN pin. */\n+};\n+\n static const struct rzg2l_hwcfg rzg3s_hwcfg = {\n \t.regs = {\n \t\t.pwpr = 0x3000,\n@@ -3524,6 +3731,23 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {\n \t.bias_param_to_hw = &rzg2l_bias_param_to_hw,\n };\n \n+static struct rzg2l_pinctrl_data r9a08g046_data = {\n+\t.port_pins = rzg3l_gpio_names,\n+\t.port_pin_configs = r9a08g046_gpio_configs,\n+\t.n_ports = ARRAY_SIZE(r9a08g046_gpio_configs),\n+\t.variable_pin_cfg = r9a08g046_variable_pin_cfg,\n+\t.n_variable_pin_cfg = ARRAY_SIZE(r9a08g046_variable_pin_cfg),\n+\t.dedicated_pins = rzg3l_dedicated_pins,\n+\t.n_port_pins = ARRAY_SIZE(r9a08g046_gpio_configs) * RZG2L_PINS_PER_PORT,\n+\t.n_dedicated_pins = ARRAY_SIZE(rzg3l_dedicated_pins),\n+\t.hwcfg = &rzg3l_hwcfg,\n+\t.pwpr_pfc_lock_unlock = &rzg2l_pwpr_pfc_lock_unlock,\n+\t.pmc_writeb = &rzg2l_pmc_writeb,\n+\t.pin_to_oen_bit = &rzg2l_pin_to_oen_bit,\n+\t.hw_to_bias_param = &rzg2l_hw_to_bias_param,\n+\t.bias_param_to_hw = &rzg2l_bias_param_to_hw,\n+};\n+\n static struct rzg2l_pinctrl_data r9a09g047_data = {\n \t.port_pins = rzg3e_gpio_names,\n \t.port_pin_configs = r9a09g047_gpio_configs,\n@@ -3604,6 +3828,10 @@ static const struct of_device_id rzg2l_pinctrl_of_table[] = {\n \t\t.compatible = \"renesas,r9a08g045-pinctrl\",\n \t\t.data = &r9a08g045_data,\n \t},\n+\t{\n+\t\t.compatible = \"renesas,r9a08g046-pinctrl\",\n+\t\t.data = &r9a08g046_data,\n+\t},\n \t{\n \t\t.compatible = \"renesas,r9a09g047-pinctrl\",\n \t\t.data = &r9a09g047_data,\n", "prefixes": [ "v4", "5/7" ] }