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GET /api/1.1/patches/2230983/?format=api
{ "id": 2230983, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-3-biju.das.jz@bp.renesas.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430093422.74812-3-biju.das.jz@bp.renesas.com>", "date": "2026-04-30T09:34:07", "name": "[v4,2/7] pinctrl: renesas: rzg2l: Make QSPI register handling conditional", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "63581ebefe53fd74c6a0e89aeec89d322d1f086a", "submitter": { "id": 87968, "url": "http://patchwork.ozlabs.org/api/1.1/people/87968/?format=api", "name": "Biju", "email": "biju.das.au@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430093422.74812-3-biju.das.jz@bp.renesas.com/mbox/", "series": [ { "id": 502254, "url": "http://patchwork.ozlabs.org/api/1.1/series/502254/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502254", "date": "2026-04-30T09:34:06", "name": "Add Renesas RZ/G3L PINCONTROL support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502254/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230983/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230983/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35850-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=sGHUrYnt;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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Unconditionally reading and writing this\nregister during suspend/resume on hardware that lacks it can cause\nundefined behaviour.\n\nAdd a qspi field to rzg2l_register_offsets to allow per-SoC declaration of\nthe QSPI register offset, and guard the suspend/resume accesses with a\ncheck on that field. Populate the offset only for the RZ/{G2L,G2LC,G2UL,\nFive} hardware configuration, which is where the register is known to\nexist.\n\nSigned-off-by: Biju Das <biju.das.jz@bp.renesas.com>\n---\nv4:\n * New patch.\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 11 ++++++++---\n 1 file changed, 8 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex bc2154b69514..ca9d4a3ec737 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -145,7 +145,7 @@\n #define SMT(off)\t\t(0x3400 + (off) * 8)\n #define SD_CH(off, ch)\t\t((off) + (ch) * 4)\n #define ETH_POC(off, ch)\t((off) + (ch) * 4)\n-#define QSPI\t\t\t(0x3008)\n+#define QSPI\t\t\t(0x3008) /* known on RZ/{G2L,G2LC,G2UL,Five} only */\n \n #define PVDD_2500\t\t2\t/* I/O domain voltage 2.5V */\n #define PVDD_1800\t\t1\t/* I/O domain voltage <= 1.8V */\n@@ -220,12 +220,14 @@ static const struct pin_config_item renesas_rzv2h_conf_items[] = {\n * @sd_ch: SD_CH register offset\n * @eth_poc: ETH_POC register offset\n * @oen: OEN register offset\n+ * @qspi: QSPI register offset\n */\n struct rzg2l_register_offsets {\n \tu16 pwpr;\n \tu16 sd_ch;\n \tu16 eth_poc;\n \tu16 oen;\n+\tu16 qspi;\n };\n \n /**\n@@ -3297,7 +3299,8 @@ static int rzg2l_pinctrl_suspend_noirq(struct device *dev)\n \t\t\tcache->eth_poc[i] = readb(pctrl->base + ETH_POC(regs->eth_poc, i));\n \t}\n \n-\tcache->qspi = readb(pctrl->base + QSPI);\n+\tif (regs->qspi)\n+\t\tcache->qspi = readb(pctrl->base + regs->qspi);\n \tcache->oen = readb(pctrl->base + pctrl->data->hwcfg->regs.oen);\n \n \tif (!atomic_read(&pctrl->wakeup_path))\n@@ -3323,7 +3326,8 @@ static int rzg2l_pinctrl_resume_noirq(struct device *dev)\n \t\t\treturn ret;\n \t}\n \n-\twriteb(cache->qspi, pctrl->base + QSPI);\n+\tif (regs->qspi)\n+\t\twriteb(cache->qspi, pctrl->base + regs->qspi);\n \n \traw_spin_lock_irqsave(&pctrl->lock, flags);\n \trzg2l_oen_write_with_pwpr(pctrl, cache->oen);\n@@ -3381,6 +3385,7 @@ static const struct rzg2l_hwcfg rzg2l_hwcfg = {\n \t\t.sd_ch = 0x3000,\n \t\t.eth_poc = 0x300c,\n \t\t.oen = 0x3018,\n+\t\t.qspi = QSPI,\n \t},\n \t.iolh_groupa_ua = {\n \t\t/* 3v3 power source */\n", "prefixes": [ "v4", "2/7" ] }