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GET /api/1.1/patches/2230976/?format=api
{ "id": 2230976, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230976/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430091832.1846637-2-kchiu@axiado.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430091832.1846637-2-kchiu@axiado.com>", "date": "2026-04-30T09:18:29", "name": "[v2,1/4] hw/arm: Add Axiado SoC AX3000", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e01f6de394ebe8f9f62d16ba0f9ce29a166092b0", "submitter": { "id": 92340, "url": "http://patchwork.ozlabs.org/api/1.1/people/92340/?format=api", "name": "Kuan-Jui Chiu", "email": "kchiu@axiado.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430091832.1846637-2-kchiu@axiado.com/mbox/", "series": [ { "id": 502248, "url": "http://patchwork.ozlabs.org/api/1.1/series/502248/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502248", "date": "2026-04-30T09:18:30", "name": "Add Axiado SoC AX3000 and EVK board", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502248/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230976/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230976/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=axiado.com header.i=@axiado.com header.a=rsa-sha256\n header.s=selector1 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helo=CY7PR03CU001.outbound.protection.outlook.com" ], "From": "Kuan-Jui Chiu <kchiu@axiado.com>", "To": "qemu-devel@nongnu.org", "Cc": "Kuan-Jui Chiu <kchiu@axiado.com>", "Subject": "[PATCH v2 1/4] hw/arm: Add Axiado SoC AX3000", "Date": "Thu, 30 Apr 2026 02:18:29 -0700", "Message-Id": "<20260430091832.1846637-2-kchiu@axiado.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260430091832.1846637-1-kchiu@axiado.com>", "References": "<20260430091832.1846637-1-kchiu@axiado.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH1PEPF0000A34A:EE_|LV3PR18MB6282:EE_", "Content-Type": "text/plain", "X-MS-Office365-Filtering-Correlation-Id": "bad112fc-0198-4d03-521c-08dea69978e7", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n 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bad112fc-0198-4d03-521c-08dea69978e7", "X-MS-Exchange-CrossTenant-Id": "ff2db17c-4338-408e-9036-2dee8e3e17d7", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=ff2db17c-4338-408e-9036-2dee8e3e17d7; Ip=[64.62.143.114];\n Helo=[smtp.corp.axiado.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH1PEPF0000A34A.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR18MB6282", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patch adds new model for Axiado SoC AX3000 which supports\n 4 Cortex-A53 ARM64 CPUs\n Arm Generic Interrupt Controller v3\n 4 Cadence UARTs\n 1 SDHCI controller with eMMC PHY\n\nSigned-off-by: Kuan-Jui Chiu <kchiu@axiado.com>\n---\n MAINTAINERS | 9 ++\n hw/arm/Kconfig | 8 ++\n hw/arm/ax3000-soc.c | 232 +++++++++++++++++++++++++++++++++++\n hw/arm/meson.build | 3 +\n hw/sd/Kconfig | 4 +\n hw/sd/axiado_sdhci.c | 100 +++++++++++++++\n hw/sd/meson.build | 1 +\n include/hw/arm/ax3000-soc.h | 78 ++++++++++++\n include/hw/sd/axiado_sdhci.h | 21 ++++\n 9 files changed, 456 insertions(+)\n create mode 100644 hw/arm/ax3000-soc.c\n create mode 100644 hw/sd/axiado_sdhci.c\n create mode 100644 include/hw/arm/ax3000-soc.h\n create mode 100644 include/hw/sd/axiado_sdhci.h", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 0a90204ae9..69da0df99a 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1285,6 +1285,15 @@ M: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>\n S: Maintained\n F: rust/hw/char/pl011/\n \n+Axiado SoCs and EVKs\n+M: Kuan-Jui Chiu <kchiu@axiado.com>\n+L: qemu-arm@nongnu.org\n+S: Maintained\n+F: hw/arm/ax3000*.c\n+F: hw/*/axiado*.c\n+F: include/hw/arm/ax3000*.h\n+F: include/hw/*/axiado*.h\n+\n AVR Machines\n -------------\n \ndiff --git a/hw/arm/Kconfig b/hw/arm/Kconfig\nindex 4e50fb1111..4fb23122fd 100644\n--- a/hw/arm/Kconfig\n+++ b/hw/arm/Kconfig\n@@ -691,3 +691,11 @@ config ARMSSE\n select UNIMP\n select SSE_COUNTER\n select SSE_TIMER\n+\n+config AXIADO_SOC\n+ bool\n+ depends on ARM\n+ select ARM_GIC\n+ select CADENCE # UART\n+ select AXIADO_SDHCI\n+ select UNIMP\ndiff --git a/hw/arm/ax3000-soc.c b/hw/arm/ax3000-soc.c\nnew file mode 100644\nindex 0000000000..e845a64c2a\n--- /dev/null\n+++ b/hw/arm/ax3000-soc.c\n@@ -0,0 +1,232 @@\n+/*\n+ * Axiado SoC AX3000\n+ *\n+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"system/address-spaces.h\"\n+#include \"hw/arm/bsa.h\"\n+#include \"hw/arm/ax3000-soc.h\"\n+#include \"hw/misc/unimp.h\"\n+#include \"system/system.h\"\n+#include \"qobject/qlist.h\"\n+#include \"qom/object.h\"\n+#include \"hw/core/boards.h\"\n+\n+static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size)\n+{\n+ switch (offset) {\n+ case CLKRST_CPU_PLL_POSTDIV_OFFSET:\n+ return 0x20891b;\n+ case CLKRST_CPU_PLL_STS_OFFSET:\n+ return 0x01;\n+ default:\n+ return 0x00;\n+ }\n+}\n+\n+static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)\n+{\n+ /* TBD */\n+}\n+\n+static const MemoryRegionOps pll_ops = {\n+ .read = pll_read,\n+ .write = pll_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+};\n+\n+static void ax3000_init(Object *obj)\n+{\n+ Ax3000SoCState *s = AX3000_SOC(obj);\n+ Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);\n+ int i;\n+\n+ for (i = 0; i < sc->num_cpus; i++) {\n+ g_autofree char *name = g_strdup_printf(\"cpu%d\", i);\n+ object_initialize_child(obj, name, &s->cpu[i],\n+ ARM_CPU_TYPE_NAME(\"cortex-a53\"));\n+ }\n+\n+ object_initialize_child(obj, \"gic\", &s->gic, gicv3_class_name());\n+\n+ for (i = 0; i < AX3000_NUM_UARTS; i++) {\n+ g_autofree char *name = g_strdup_printf(\"uart%d\", i);\n+ object_initialize_child(obj, name, &s->uart[i], TYPE_CADENCE_UART);\n+ }\n+\n+ object_initialize_child(obj, \"sdhci0\", &s->sdhci0, TYPE_AXIADO_SDHCI);\n+}\n+\n+static void ax3000_realize(DeviceState *dev, Error **errp)\n+{\n+ Ax3000SoCState *s = AX3000_SOC(dev);\n+ Ax3000SoCClass *sc = AX3000_SOC_GET_CLASS(s);\n+ SysBusDevice *gic_sbd = SYS_BUS_DEVICE(&s->gic);\n+ DeviceState *gic_dev = DEVICE(&s->gic);\n+ QList *redist_region_count;\n+ SysBusDevice *sdhci0_sbd;\n+ DeviceState *card;\n+ int i;\n+\n+ /* CPUs */\n+ for (i = 0; i < sc->num_cpus; i++) {\n+ object_property_set_int(OBJECT(&s->cpu[i]), \"cntfrq\", 8000000,\n+ &error_abort);\n+\n+ if (object_property_find(OBJECT(&s->cpu[i]), \"has_el3\")) {\n+ object_property_set_bool(OBJECT(&s->cpu[i]), \"has_el3\",\n+ false, &error_abort);\n+ }\n+\n+ if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {\n+ return;\n+ }\n+ }\n+\n+ /* GIC */\n+ qdev_prop_set_uint32(gic_dev, \"num-cpu\", sc->num_cpus);\n+ qdev_prop_set_uint32(gic_dev, \"num-irq\",\n+ AX3000_NUM_IRQS + GIC_INTERNAL);\n+\n+ redist_region_count = qlist_new();\n+ qlist_append_int(redist_region_count, sc->num_cpus);\n+ qdev_prop_set_array(gic_dev, \"redist-region-count\", redist_region_count);\n+\n+ if (!sysbus_realize(gic_sbd, errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(gic_sbd, 0, AX3000_GIC_DIST_BASE);\n+ sysbus_mmio_map(gic_sbd, 1, AX3000_GIC_REDIST_BASE);\n+\n+ /*\n+ * Wire the outputs from each CPU's generic timer and the GICv3\n+ * maintenance interrupt signal to the appropriate GIC PPI inputs, and\n+ * the GIC's IRQ/FIQ interrupt outputs to the CPU's inputs.\n+ */\n+ for (i = 0; i < sc->num_cpus; i++) {\n+ DeviceState *cpu_dev = DEVICE(&s->cpu[i]);\n+ int intidbase = AX3000_NUM_IRQS + i * GIC_INTERNAL;\n+ qemu_irq irq;\n+\n+ /*\n+ * Mapping from the output timer irq lines from the CPU to the\n+ * GIC PPI inputs.\n+ */\n+ static const int timer_irqs[] = {\n+ [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ,\n+ [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ,\n+ [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ,\n+ [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ\n+ };\n+\n+ for (int j = 0; j < ARRAY_SIZE(timer_irqs); j++) {\n+ irq = qdev_get_gpio_in(gic_dev, intidbase + timer_irqs[j]);\n+ qdev_connect_gpio_out(cpu_dev, j, irq);\n+ }\n+\n+ irq = qdev_get_gpio_in(gic_dev, intidbase + ARCH_GIC_MAINT_IRQ);\n+ qdev_connect_gpio_out_named(cpu_dev, \"gicv3-maintenance-interrupt\",\n+ 0, irq);\n+\n+ sysbus_connect_irq(gic_sbd, i,\n+ qdev_get_gpio_in(cpu_dev, ARM_CPU_IRQ));\n+ sysbus_connect_irq(gic_sbd, i + sc->num_cpus,\n+ qdev_get_gpio_in(cpu_dev, ARM_CPU_FIQ));\n+ sysbus_connect_irq(gic_sbd, i + 2 * sc->num_cpus,\n+ qdev_get_gpio_in(cpu_dev, ARM_CPU_VIRQ));\n+ sysbus_connect_irq(gic_sbd, i + 3 * sc->num_cpus,\n+ qdev_get_gpio_in(cpu_dev, ARM_CPU_VFIQ));\n+ }\n+\n+ /* DRAM */\n+ for (i = 0; i < AX3000_NUM_BANKS; i++) {\n+ struct {\n+ hwaddr addr;\n+ size_t size;\n+ const char *name;\n+ } dram_table[] = {\n+ { AX3000_DRAM0_BASE, AX3000_DRAM0_SIZE, \"dram0\" },\n+ { AX3000_DRAM1_BASE, AX3000_DRAM1_SIZE, \"dram1\" }\n+ };\n+\n+ memory_region_init_ram(&s->dram[i], OBJECT(s), dram_table[i].name,\n+ dram_table[i].size, &error_fatal);\n+ memory_region_add_subregion(get_system_memory(), dram_table[i].addr,\n+ &s->dram[i]);\n+ }\n+\n+ /* UARTs */\n+ for (i = 0; i < AX3000_NUM_UARTS; i++) {\n+ struct {\n+ hwaddr addr;\n+ unsigned int irq;\n+ } serial_table[] = {\n+ { AX3000_UART0_BASE, AX3000_UART0_IRQ },\n+ { AX3000_UART1_BASE, AX3000_UART1_IRQ },\n+ { AX3000_UART2_BASE, AX3000_UART2_IRQ },\n+ { AX3000_UART3_BASE, AX3000_UART3_IRQ }\n+ };\n+\n+ qdev_prop_set_chr(DEVICE(&s->uart[i]), \"chardev\", serial_hd(i));\n+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart[i]), errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart[i]), 0, serial_table[i].addr);\n+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart[i]), 0,\n+ qdev_get_gpio_in(gic_dev, serial_table[i].irq));\n+ }\n+\n+ /* Timer control */\n+ create_unimplemented_device(\"ax3000.timerctrl\", AX3000_TIMER_CTRL, 32);\n+\n+ /* PLL control */\n+ memory_region_init_io(&s->pll_ctrl, OBJECT(s), &pll_ops, s,\n+ \"ax3000.pllctrl\", 32);\n+ memory_region_add_subregion(get_system_memory(), AX3000_PLL_BASE,\n+ &s->pll_ctrl);\n+\n+ /* SDHCI */\n+ sdhci0_sbd = SYS_BUS_DEVICE(&s->sdhci0);\n+ if (!sysbus_realize(sdhci0_sbd, errp)) {\n+ return;\n+ }\n+\n+ sysbus_mmio_map(sdhci0_sbd, 0, AX3000_SDHCI0_BASE);\n+ sysbus_mmio_map(sdhci0_sbd, 1, AX3000_EMMC_PHY_BASE);\n+ sysbus_connect_irq(sdhci0_sbd, 0,\n+ qdev_get_gpio_in(gic_dev, AX3000_SDHCI0_IRQ));\n+\n+ card = qdev_new(TYPE_SD_CARD);\n+ qdev_prop_set_drive_err(card, \"drive\",\n+ blk_by_legacy_dinfo((drive_get(IF_SD, 0, 0))),\n+ &error_fatal);\n+ qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);\n+}\n+\n+static void ax3000_class_init(ObjectClass *oc, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(oc);\n+ Ax3000SoCClass *sc = AX3000_SOC_CLASS(oc);\n+\n+ dc->desc = \"Axiado SoC AX3000\";\n+ dc->realize = ax3000_realize;\n+ sc->num_cpus = AX3000_NUM_CPUS;\n+}\n+\n+static const TypeInfo axiado_soc_types[] = {\n+ {\n+ .name = TYPE_AX3000_SOC,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(Ax3000SoCState),\n+ .instance_init = ax3000_init,\n+ .class_init = ax3000_class_init,\n+ }\n+};\n+\n+DEFINE_TYPES(axiado_soc_types)\ndiff --git a/hw/arm/meson.build b/hw/arm/meson.build\nindex b187b946f0..e32f5eb0c7 100644\n--- a/hw/arm/meson.build\n+++ b/hw/arm/meson.build\n@@ -105,6 +105,9 @@ arm_common_ss.add(when: 'CONFIG_SX1', if_true: files('omap_sx1.c'))\n arm_common_ss.add(when: 'CONFIG_VERSATILE', if_true: files('versatilepb.c'))\n arm_common_ss.add(when: 'CONFIG_VEXPRESS', if_true: files('vexpress.c'))\n \n+arm_common_ss.add(when: ['CONFIG_AXIADO_SOC', 'TARGET_AARCH64'], if_true: files(\n+ 'ax3000-soc.c'))\n+\n arm_common_ss.add(files('boot.c'))\n \n hw_arch += {'arm': arm_ss}\ndiff --git a/hw/sd/Kconfig b/hw/sd/Kconfig\nindex 633b9afec9..c69bf24f8d 100644\n--- a/hw/sd/Kconfig\n+++ b/hw/sd/Kconfig\n@@ -23,3 +23,7 @@ config SDHCI_PCI\n config CADENCE_SDHCI\n bool\n select SDHCI\n+\n+config AXIADO_SDHCI\n+ bool\n+ select SDHCI\ndiff --git a/hw/sd/axiado_sdhci.c b/hw/sd/axiado_sdhci.c\nnew file mode 100644\nindex 0000000000..219d49079e\n--- /dev/null\n+++ b/hw/sd/axiado_sdhci.c\n@@ -0,0 +1,100 @@\n+/*\n+ * Axiado SD Host Controller\n+ *\n+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+#include \"hw/sd/axiado_sdhci.h\"\n+#include \"sdhci-internal.h\"\n+#include \"qapi/error.h\"\n+#include \"hw/core/qdev-properties.h\"\n+\n+#define EMMC_PHY_ID 0x00\n+#define EMMC_PHY_STATUS 0x50\n+\n+static uint64_t emmc_phy_read(void *opaque, hwaddr offset, unsigned size)\n+{\n+ uint32_t val = 0x00;\n+\n+ switch (offset) {\n+ case EMMC_PHY_ID:\n+ val = 0x3dff6870;\n+ break;\n+ case EMMC_PHY_STATUS:\n+ /* Make DLL_RDY | CAL_DONE */\n+ val = (1u << 0) | (1u << 6);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return val;\n+}\n+\n+static void emmc_phy_write(void *opaque, hwaddr offset, uint64_t value,\n+ unsigned size)\n+{\n+ /* TBD */\n+}\n+\n+static const MemoryRegionOps emmc_phy_ops = {\n+ .read = emmc_phy_read,\n+ .write = emmc_phy_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+};\n+\n+static void axiado_sdhci_realize(DeviceState *dev, Error **errp)\n+{\n+ AxiadoSDHCIState *s = AXIADO_SDHCI(dev);\n+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);\n+ SysBusDevice *sdhci_sbd;\n+\n+ object_initialize_child(OBJECT(s), \"sdhci\", &s->sdhci,\n+ TYPE_SYSBUS_SDHCI);\n+\n+ qdev_prop_set_uint64(DEVICE(&s->sdhci), \"capareg\", 0x216737eed0b0);\n+ qdev_prop_set_uint64(DEVICE(&s->sdhci), \"sd-spec-version\", 3);\n+\n+ sdhci_sbd = SYS_BUS_DEVICE(&s->sdhci);\n+ sysbus_realize(sdhci_sbd, errp);\n+ if (*errp) {\n+ return;\n+ }\n+\n+ sysbus_init_mmio(sbd, sysbus_mmio_get_region(sdhci_sbd, 0));\n+\n+ /* Propagate IRQ from SDHCI and SD bus */\n+ sysbus_pass_irq(sbd, sdhci_sbd);\n+ s->sd_bus = qdev_get_child_bus(DEVICE(sdhci_sbd), \"sd-bus\");\n+\n+ /* Initialize eMMC PHY MMIO */\n+ memory_region_init_io(&s->emmc_phy, OBJECT(s), &emmc_phy_ops, s,\n+ \"axiado.emmc-phy\", 0x1000);\n+\n+ sysbus_init_mmio(sbd, &s->emmc_phy);\n+}\n+\n+static void axiado_sdhci_class_init(ObjectClass *klass, const void *data)\n+{\n+ DeviceClass *dc = DEVICE_CLASS(klass);\n+\n+ dc->realize = axiado_sdhci_realize;\n+ dc->desc = \"Axiado SD Host Controller with eMMC PHY\";\n+}\n+\n+static const TypeInfo axiado_sdhci_info = {\n+ .name = TYPE_AXIADO_SDHCI,\n+ .parent = TYPE_SYS_BUS_DEVICE,\n+ .instance_size = sizeof(AxiadoSDHCIState),\n+ .class_init = axiado_sdhci_class_init,\n+};\n+\n+static void axiado_sdhci_register_types(void)\n+{\n+ type_register_static(&axiado_sdhci_info);\n+}\n+\n+type_init(axiado_sdhci_register_types);\ndiff --git a/hw/sd/meson.build b/hw/sd/meson.build\nindex b43d45bc56..ebf09e30a4 100644\n--- a/hw/sd/meson.build\n+++ b/hw/sd/meson.build\n@@ -10,3 +10,4 @@ system_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c'))\n system_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdhost.c'))\n system_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_sdhci.c'))\n system_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci.c'))\n+system_ss.add(when: 'CONFIG_AXIADO_SDHCI', if_true: files('axiado_sdhci.c'))\ndiff --git a/include/hw/arm/ax3000-soc.h b/include/hw/arm/ax3000-soc.h\nnew file mode 100644\nindex 0000000000..2708c9c672\n--- /dev/null\n+++ b/include/hw/arm/ax3000-soc.h\n@@ -0,0 +1,78 @@\n+/*\n+ * Axiado SoC AX3000\n+ *\n+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef AXIADO_AX3000_H\n+#define AXIADO_AX3000_H\n+\n+#include \"cpu.h\"\n+#include \"hw/intc/arm_gicv3_common.h\"\n+#include \"hw/char/cadence_uart.h\"\n+#include \"hw/sd/axiado_sdhci.h\"\n+#include \"hw/core/sysbus.h\"\n+#include \"qemu/units.h\"\n+\n+#define TYPE_AX3000_SOC \"ax3000\"\n+OBJECT_DECLARE_TYPE(Ax3000SoCState, Ax3000SoCClass, AX3000_SOC)\n+\n+#define AX3000_DRAM0_BASE 0x3C000000\n+#define AX3000_DRAM0_SIZE (1088 * MiB)\n+#define AX3000_DRAM1_BASE 0x400000000\n+#define AX3000_DRAM1_SIZE (2 * GiB)\n+\n+#define AX3000_GIC_DIST_BASE 0x80300000\n+#define AX3000_GIC_DIST_SIZE (64 * KiB)\n+#define AX3000_GIC_REDIST_BASE 0x80380000\n+#define AX3000_GIC_REDIST_SIZE (512 * KiB)\n+\n+#define AX3000_UART0_BASE 0x80520000\n+#define AX3000_UART1_BASE 0x805a0000\n+#define AX3000_UART2_BASE 0x80620000\n+#define AX3000_UART3_BASE 0x80520800\n+\n+#define AX3000_SDHCI0_BASE 0x86000000\n+#define AX3000_EMMC_PHY_BASE 0x80801C00\n+\n+#define AX3000_TIMER_CTRL 0x8A020000\n+#define AX3000_PLL_BASE 0x80000000\n+#define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C\n+#define CLKRST_CPU_PLL_STS_OFFSET 0x14\n+\n+enum Ax3000Configuration {\n+ AX3000_NUM_CPUS = 4,\n+ AX3000_NUM_IRQS = 224,\n+ AX3000_NUM_BANKS = 2,\n+ AX3000_NUM_UARTS = 4,\n+};\n+\n+typedef struct Ax3000SoCState {\n+ SysBusDevice parent;\n+\n+ ARMCPU cpu[AX3000_NUM_CPUS];\n+ GICv3State gic;\n+ MemoryRegion dram[AX3000_NUM_BANKS];\n+ MemoryRegion pll_ctrl;\n+ CadenceUARTState uart[AX3000_NUM_UARTS];\n+ AxiadoSDHCIState sdhci0;\n+} Ax3000SoCState;\n+\n+typedef struct Ax3000SoCClass {\n+ SysBusDeviceClass parent;\n+\n+ uint32_t num_cpus;\n+} Ax3000SoCClass;\n+\n+enum Ax3000Irqs {\n+ AX3000_UART0_IRQ = 112,\n+ AX3000_UART1_IRQ = 113,\n+ AX3000_UART2_IRQ = 114,\n+ AX3000_UART3_IRQ = 170,\n+\n+ AX3000_SDHCI0_IRQ = 123,\n+};\n+\n+#endif /* AXIADO_AX3000_H */\ndiff --git a/include/hw/sd/axiado_sdhci.h b/include/hw/sd/axiado_sdhci.h\nnew file mode 100644\nindex 0000000000..85afebad93\n--- /dev/null\n+++ b/include/hw/sd/axiado_sdhci.h\n@@ -0,0 +1,21 @@\n+/*\n+ * Axiado SD Host Controller\n+ *\n+ * Author: Kuan-Jui Chiu <kchiu@axiado.com>\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"hw/sd/sdhci.h\"\n+#include \"qom/object.h\"\n+\n+#define TYPE_AXIADO_SDHCI \"axiado-sdhci\"\n+OBJECT_DECLARE_SIMPLE_TYPE(AxiadoSDHCIState, AXIADO_SDHCI)\n+\n+typedef struct AxiadoSDHCIState {\n+ SysBusDevice parent;\n+\n+ SDHCIState sdhci;\n+ MemoryRegion emmc_phy;\n+ BusState *sd_bus;\n+} AxiadoSDHCIState;\n", "prefixes": [ "v2", "1/4" ] }