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GET /api/1.1/patches/2230882/?format=api
{ "id": 2230882, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230882/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-13-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430071315.354333-13-zhenzhong.duan@intel.com>", "date": "2026-04-30T07:13:08", "name": "[v4,12/15] intel_iommu_accel: Handle PASID entry removal for system reset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e83259e5d704ca7b5ce4cda4e02db549e2978043", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/1.1/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430071315.354333-13-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 502222, "url": "http://patchwork.ozlabs.org/api/1.1/series/502222/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502222", "date": "2026-04-30T07:12:57", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/502222/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230882/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230882/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=K//NQ6BT;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5lpN3qVpz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 17:16:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wILbW-0005Xh-7Q; Thu, 30 Apr 2026 03:14:34 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1wILbI-0005Ia-IQ\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 03:14:23 -0400", "from mgamail.intel.com ([192.198.163.13])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1wILbF-0008SS-Hu\n for qemu-devel@nongnu.org; Thu, 30 Apr 2026 03:14:19 -0400", "from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:14:16 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by orviesa007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 30 Apr 2026 00:14:13 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1777533257; x=1809069257;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=5AAIh0/fe9VJgDFi4pd/VBv+Ip1yHHhCwUyOn7gO+jc=;\n b=K//NQ6BTOTcG7jVd1wvIB4NMiKVm/3vAcNnHfISSg/h87CrClF3KgH5r\n SdI73Gc1h6R7eSAjjalD1DmCaPtpZ7oIt74KEuNnvI2UqQsDHNs27kIOh\n t81bSKpWOuu1UzfB4HvNmlnFhgSy9W++eIOWKiX9cJu8iL7kcQ9wo+wwH\n K2JpvDUBhwyHnNTkxC9r5zS73k8t2REQrfNfk2M2ugHLTw/H/XiyaFCmo\n rLZ7E19AEga+pN3Vpy58RbbP/3EeKaAhqqNYhQpzxTB7v+flbVhHYhQ/7\n jjF00KCv5jJFeKDSZ6iVstX6e9hCowSXjCV/dqvqzvYSYapIjnFEuxMnx A==;", "X-CSE-ConnectionGUID": [ "trQBpopaSVSx98LQPKpXog==", "3Fi9CFuVQK+gRu1qrd8oKQ==" ], "X-CSE-MsgGUID": [ "HNw7IuS2Qx2OQ/kejyF8TA==", "0CsgCAa/RDOg3sodWSTLyg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11771\"; a=\"81051663\"", "E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"81051663\"", "E=Sophos;i=\"6.23,207,1770624000\"; d=\"scan'208\";a=\"234771573\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v4 12/15] intel_iommu_accel: Handle PASID entry removal for\n system reset", "Date": "Thu, 30 Apr 2026 03:13:08 -0400", "Message-ID": "<20260430071315.354333-13-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260430071315.354333-1-zhenzhong.duan@intel.com>", "References": "<20260430071315.354333-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.13;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When system level reset, DMA translation is turned off, all PASID\nentries become stale and should be deleted.\n\nvtd_hiod list is never accessed without BQL, so no need to guard with\niommu lock.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Yi Liu <yi.l.liu@intel.com>\nTested-by: Xudong Hao <xudong.hao@intel.com>\n---\n hw/i386/intel_iommu_accel.h | 5 +++++\n hw/i386/intel_iommu.c | 2 ++\n hw/i386/intel_iommu_accel.c | 13 +++++++++++++\n 3 files changed, 20 insertions(+)", "diff": "diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h\nindex c9b1823745..a2226b28b6 100644\n--- a/hw/i386/intel_iommu_accel.h\n+++ b/hw/i386/intel_iommu_accel.h\n@@ -28,6 +28,7 @@ void vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, uint16_t domain_id,\n uint32_t pasid, hwaddr addr,\n uint64_t npages, bool ih);\n void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info);\n+void vtd_accel_pasid_cache_reset(IntelIOMMUState *s);\n void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops);\n #else\n static inline bool vtd_check_hiod_accel(IntelIOMMUState *s,\n@@ -62,6 +63,10 @@ static inline void vtd_accel_pasid_cache_sync(IntelIOMMUState *s,\n {\n }\n \n+static inline void vtd_accel_pasid_cache_reset(IntelIOMMUState *s)\n+{\n+}\n+\n static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops)\n {\n }\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex fa145af021..f4a61188c7 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -420,6 +420,8 @@ static void vtd_reset_caches(IntelIOMMUState *s)\n vtd_reset_context_cache_locked(s);\n vtd_pasid_cache_reset_locked(s);\n vtd_iommu_unlock(s);\n+\n+ vtd_accel_pasid_cache_reset(s);\n }\n \n static uint64_t vtd_get_iotlb_gfn(hwaddr addr, uint32_t level)\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 457fdcba62..4abe1d228d 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -516,6 +516,19 @@ void vtd_accel_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info)\n }\n }\n \n+/* Fake a global pasid cache invalidation to remove all pasid cache entries */\n+void vtd_accel_pasid_cache_reset(IntelIOMMUState *s)\n+{\n+ VTDPASIDCacheInfo pc_info = { .type = VTD_INV_DESC_PASIDC_G_GLOBAL };\n+ VTDHostIOMMUDevice *vtd_hiod;\n+ GHashTableIter hiod_it;\n+\n+ g_hash_table_iter_init(&hiod_it, s->vtd_host_iommu_dev);\n+ while (g_hash_table_iter_next(&hiod_it, NULL, (void **)&vtd_hiod)) {\n+ vtd_accel_pasid_cache_invalidate(vtd_hiod, &pc_info);\n+ }\n+}\n+\n static uint64_t vtd_get_host_iommu_quirks(uint32_t type,\n void *caps, uint32_t size)\n {\n", "prefixes": [ "v4", "12/15" ] }