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GET /api/1.1/patches/2230864/?format=api
{ "id": 2230864, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230864/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com>", "date": "2026-04-30T07:10:44", "name": "[v2,4/5] arm64: dts: qcom: sm6350: add LPASS LPI pin controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d5e9c3364193ef14ed1d75b9bb35ea243fc84761", "submitter": { "id": 83060, "url": "http://patchwork.ozlabs.org/api/1.1/people/83060/?format=api", "name": "Luca Weiss", "email": "luca.weiss@fairphone.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com/mbox/", "series": [ { "id": 502221, "url": "http://patchwork.ozlabs.org/api/1.1/series/502221/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502221", "date": "2026-04-30T07:10:40", "name": "Add LPASS LPI pin controller support for SM6350", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/502221/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230864/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230864/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35830-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=fairphone.com header.i=@fairphone.com\n header.a=rsa-sha256 header.s=fair header.b=4kIU7Are;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260430-sm6350-lpi-tlmm-v2-4-81d068025b97@fairphone.com>", "References": "<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>", "In-Reply-To": "<20260430-sm6350-lpi-tlmm-v2-0-81d068025b97@fairphone.com>", "To": "Bjorn Andersson <andersson@kernel.org>,\n Linus Walleij <linusw@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Konrad Dybcio <konradybcio@kernel.org>,\n Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>", "Cc": "~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Luca Weiss <luca.weiss@fairphone.com>,\n Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777533047; l=2211;\n i=luca.weiss@fairphone.com; s=20250611; h=from:subject:message-id;\n bh=xA+JyyhoD+6cuOWQwY5YNIB4x5Pz3Kxm/8/MqUktfKk=;\n b=o47mlBib4+72w4KeKq52GDFNeG46iqvF8whC4buxAu3HdKwKgINEBOpYn5vs8NBfDwkL2uj4N\n y8i1wxSd+I7Db+UWVHa8rVux1DtoPMRNGFdI+uCJlPu1z3JWTXLjZzU", "X-Developer-Key": "i=luca.weiss@fairphone.com; a=ed25519;\n pk=O1aw+AAust5lEmgrNJ1Bs7PTY0fEsJm+mdkjExA69q8=" }, "content": "Add LPASS LPI pinctrl node required for audio functionality on SM6350.\n\nReviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>\nSigned-off-by: Luca Weiss <luca.weiss@fairphone.com>\n---\n arch/arm64/boot/dts/qcom/sm6350.dtsi | 66 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 66 insertions(+)", "diff": "diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi\nindex 034545d2af2d..d6adf68563cb 100644\n--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi\n+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi\n@@ -1450,6 +1450,72 @@ compute-cb@5 {\n \t\t\t};\n \t\t};\n \n+\t\tlpass_tlmm: pinctrl@33c0000 {\n+\t\t\tcompatible = \"qcom,sm6350-lpass-lpi-pinctrl\";\n+\t\t\treg = <0x0 0x033c0000 0x0 0x20000>,\n+\t\t\t <0x0 0x03550000 0x0 0x10000>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&lpass_tlmm 0 0 15>;\n+\n+\t\t\tclocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,\n+\t\t\t\t <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;\n+\t\t\tclock-names = \"core\",\n+\t\t\t\t \"audio\";\n+\n+\t\t\ti2s1_active: i2s1-active-state {\n+\t\t\t\tclk-pins {\n+\t\t\t\t\tpins = \"gpio6\";\n+\t\t\t\t\tfunction = \"i2s1_clk\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t\toutput-high;\n+\t\t\t\t};\n+\n+\t\t\t\tws-pins {\n+\t\t\t\t\tpins = \"gpio7\";\n+\t\t\t\t\tfunction = \"i2s1_ws\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t\toutput-high;\n+\t\t\t\t};\n+\n+\t\t\t\tdata-pins {\n+\t\t\t\t\tpins = \"gpio8\", \"gpio9\";\n+\t\t\t\t\tfunction = \"i2s1_data\";\n+\t\t\t\t\tdrive-strength = <8>;\n+\t\t\t\t\tbias-disable;\n+\t\t\t\t\toutput-high;\n+\t\t\t\t};\n+\t\t\t};\n+\n+\t\t\ti2s1_sleep: i2s1-sleep-state {\n+\t\t\t\tclk-pins {\n+\t\t\t\t\tpins = \"gpio6\";\n+\t\t\t\t\tfunction = \"i2s1_clk\";\n+\t\t\t\t\tdrive-strength = <2>;\n+\t\t\t\t\tbias-pull-down;\n+\t\t\t\t\tinput-enable;\n+\t\t\t\t};\n+\n+\t\t\t\tws-pins {\n+\t\t\t\t\tpins = \"gpio7\";\n+\t\t\t\t\tfunction = \"i2s1_ws\";\n+\t\t\t\t\tdrive-strength = <2>;\n+\t\t\t\t\tbias-pull-down;\n+\t\t\t\t\tinput-enable;\n+\t\t\t\t};\n+\n+\t\t\t\tdata-pins {\n+\t\t\t\t\tpins = \"gpio8\", \"gpio9\";\n+\t\t\t\t\tfunction = \"i2s1_data\";\n+\t\t\t\t\tdrive-strength = <2>;\n+\t\t\t\t\tbias-pull-down;\n+\t\t\t\t\tinput-enable;\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\n \t\tgpu: gpu@3d00000 {\n \t\t\tcompatible = \"qcom,adreno-619.0\", \"qcom,adreno\";\n \t\t\treg = <0x0 0x03d00000 0x0 0x40000>,\n", "prefixes": [ "v2", "4/5" ] }