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GET /api/1.1/patches/2230779/?format=api
{ "id": 2230779, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230779/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260430024945.3413973-12-wei.fang@nxp.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.1/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/" }, "msgid": "<20260430024945.3413973-12-wei.fang@nxp.com>", "date": "2026-04-30T02:49:41", "name": "[v5,net-next,11/15] net: dsa: netc: add phylink MAC operations", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "d413813333ab268b25265d4b6073ed02bd03dbfe", "submitter": { "id": 84380, "url": "http://patchwork.ozlabs.org/api/1.1/people/84380/?format=api", "name": "Wei Fang", "email": "wei.fang@nxp.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260430024945.3413973-12-wei.fang@nxp.com/mbox/", "series": [ { "id": 502180, "url": "http://patchwork.ozlabs.org/api/1.1/series/502180/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=502180", "date": "2026-04-30T02:49:30", "name": "Add preliminary NETC switch support for i.MX94", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502180/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230779/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230779/checks/", "tags": {}, "headers": { "Return-Path": "\n <linuxppc-dev+bounces-20314-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": 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c=relaxed/relaxed; d=nxp.com; s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=scrisMzMwHW3nalchf3MHRRsjin059kDS5eiWt60XHc=;\n b=NHN1ME9YcLEj7HsK/Ki7iCw5yCLssDss9xLy9LUGbURFeQGaLH/3YLCSDsoPBooMTMs0fwDkqgbLwQRsAWW3obLuLx5gtQpWz2smWsFixHYYZySoVR8XJuiVT5Iqz956NcLD5exh+xHmTO5oxNnu0FHsFxtUEixBObMWYaFF3MCotzxa9Wx6b21s4ooBzHe5y1ACqdqBSAePF5PbyFWqaNT1bIyNhq2sZtnznffCdJjiA9c50QwjrlliBU18p4vXpBxjqmiXavRJRi2SUxC7kT58TT9pCUuKzFK5hJP/qgvvV3CaCOLMkm5hwLg/V3sJaUKqGLLwCyQ0aRKZef+Elg==", "From": "Wei Fang <wei.fang@nxp.com>", "To": "claudiu.manoil@nxp.com,\n\tvladimir.oltean@nxp.com,\n\txiaoning.wang@nxp.com,\n\tandrew+netdev@lunn.ch,\n\tdavem@davemloft.net,\n\tedumazet@google.com,\n\tkuba@kernel.org,\n\tpabeni@redhat.com,\n\trobh@kernel.org,\n\tkrzk+dt@kernel.org,\n\tconor+dt@kernel.org,\n\tf.fainelli@gmail.com,\n\tfrank.li@nxp.com,\n\tchleroy@kernel.org,\n\thorms@kernel.org,\n\tlinux@armlinux.org.uk", "Cc": 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lists.ozlabs.org" }, "content": "Different versions of NETC switches have different numbers of ports and\nMAC capabilities. Add .phylink_get_caps() to struct netc_switch_info,\nallowing each NETC switch version to implement its own callback for\nobtaining MAC capabilities.\n\nImplement the phylink_mac_ops callbacks: .mac_config(), .mac_link_up(),\nand .mac_link_down(). Note that flow-control configuration is not yet\nsupported in .mac_link_up(), but will be implemented in a subsequent\npatch.\n\nSigned-off-by: Wei Fang <wei.fang@nxp.com>\n---\n drivers/net/dsa/netc/netc_main.c | 243 ++++++++++++++++++++++++++\n drivers/net/dsa/netc/netc_platform.c | 38 ++++\n drivers/net/dsa/netc/netc_switch.h | 4 +\n drivers/net/dsa/netc/netc_switch_hw.h | 26 +++\n 4 files changed, 311 insertions(+)", "diff": "diff --git a/drivers/net/dsa/netc/netc_main.c b/drivers/net/dsa/netc/netc_main.c\nindex 90a2d8cfd3d2..edf50cb32cb6 100644\n--- a/drivers/net/dsa/netc/netc_main.c\n+++ b/drivers/net/dsa/netc/netc_main.c\n@@ -44,6 +44,26 @@ static void netc_mac_port_wr(struct netc_port *np, u32 reg, u32 val)\n \t\tnetc_port_wr(np, reg + NETC_PMAC_OFFSET, val);\n }\n \n+static void netc_mac_port_rmw(struct netc_port *np, u32 reg,\n+\t\t\t u32 mask, u32 val)\n+{\n+\tu32 old, new;\n+\n+\tif (is_netc_pseudo_port(np))\n+\t\treturn;\n+\n+\tWARN_ON((mask | val) != mask);\n+\n+\told = netc_port_rd(np, reg);\n+\tnew = (old & ~mask) | val;\n+\tif (new == old)\n+\t\treturn;\n+\n+\tnetc_port_wr(np, reg, new);\n+\tif (np->caps.pmac)\n+\t\tnetc_port_wr(np, reg + NETC_PMAC_OFFSET, new);\n+}\n+\n static void netc_port_get_capability(struct netc_port *np)\n {\n \tu32 val;\n@@ -522,10 +542,232 @@ static void netc_switch_get_ip_revision(struct netc_switch *priv)\n \tpriv->revision = FIELD_GET(IPBRR0_IP_REV, val);\n }\n \n+static void netc_phylink_get_caps(struct dsa_switch *ds, int port,\n+\t\t\t\t struct phylink_config *config)\n+{\n+\tstruct netc_switch *priv = ds->priv;\n+\n+\tpriv->info->phylink_get_caps(port, config);\n+}\n+\n+static void netc_port_set_mac_mode(struct netc_port *np,\n+\t\t\t\t unsigned int mode,\n+\t\t\t\t phy_interface_t phy_mode)\n+{\n+\tu32 mask = PM_IF_MODE_IFMODE | PM_IF_MODE_REVMII;\n+\tu32 val = 0;\n+\n+\tswitch (phy_mode) {\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\tval |= IFMODE_RGMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RMII:\n+\t\tval |= IFMODE_RMII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_REVMII:\n+\t\tval |= PM_IF_MODE_REVMII;\n+\t\tfallthrough;\n+\tcase PHY_INTERFACE_MODE_MII:\n+\t\tval |= IFMODE_MII;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tval |= IFMODE_SGMII;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tnetc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);\n+}\n+\n+static void netc_mac_config(struct phylink_config *config, unsigned int mode,\n+\t\t\t const struct phylink_link_state *state)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\n+\tnetc_port_set_mac_mode(NETC_PORT(dp->ds, dp->index), mode,\n+\t\t\t state->interface);\n+}\n+\n+static void netc_port_set_speed(struct netc_port *np, int speed)\n+{\n+\tnetc_port_rmw(np, NETC_PCR, PCR_PSPEED, PSPEED_SET_VAL(speed));\n+}\n+\n+static void netc_port_set_rgmii_mac(struct netc_port *np,\n+\t\t\t\t int speed, int duplex)\n+{\n+\tu32 mask, val;\n+\n+\tmask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;\n+\n+\tswitch (speed) {\n+\tdefault:\n+\tcase SPEED_1000:\n+\t\tval = FIELD_PREP(PM_IF_MODE_SSP, SSP_1G);\n+\t\tbreak;\n+\tcase SPEED_100:\n+\t\tval = FIELD_PREP(PM_IF_MODE_SSP, SSP_100M);\n+\t\tbreak;\n+\tcase SPEED_10:\n+\t\tval = FIELD_PREP(PM_IF_MODE_SSP, SSP_10M);\n+\t\tbreak;\n+\t}\n+\n+\tif (duplex != DUPLEX_FULL)\n+\t\tval |= PM_IF_MODE_HD;\n+\n+\tnetc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);\n+}\n+\n+static void netc_port_set_rmii_mii_mac(struct netc_port *np,\n+\t\t\t\t int speed, int duplex)\n+{\n+\tu32 mask, val = 0;\n+\n+\tmask = PM_IF_MODE_SSP | PM_IF_MODE_HD | PM_IF_MODE_M10;\n+\n+\tif (speed == SPEED_10)\n+\t\tval |= PM_IF_MODE_M10;\n+\n+\tif (duplex != DUPLEX_FULL)\n+\t\tval |= PM_IF_MODE_HD;\n+\n+\tnetc_mac_port_rmw(np, NETC_PM_IF_MODE(0), mask, val);\n+}\n+\n+static void netc_port_mac_rx_enable(struct netc_port *np)\n+{\n+\tnetc_port_rmw(np, NETC_POR, POR_RXDIS, 0);\n+\tnetc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN,\n+\t\t\t PM_CMD_CFG_RX_EN);\n+}\n+\n+static void netc_port_wait_rx_empty(struct netc_port *np, int mac)\n+{\n+\tu32 val;\n+\n+\t/* PM_IEVENT_RX_EMPTY is a read-only bit, it is automatically set by\n+\t * hardware if RX FIFO is empty and no RX packet receive in process.\n+\t * And it is automatically cleared if RX FIFO is not empty or RX\n+\t * packet receive in process.\n+\t */\n+\tif (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_RX_EMPTY,\n+\t\t\t 100, 10000, false, np, NETC_PM_IEVENT(mac)))\n+\t\tdev_warn(np->switch_priv->dev,\n+\t\t\t \"swp%d MAC%d: RX is not idle\\n\", np->dp->index, mac);\n+}\n+\n+static void netc_port_mac_rx_graceful_stop(struct netc_port *np)\n+{\n+\tu32 val;\n+\n+\tif (is_netc_pseudo_port(np))\n+\t\tgoto rx_disable;\n+\n+\tif (np->caps.pmac) {\n+\t\tnetc_port_rmw(np, NETC_PM_CMD_CFG(1), PM_CMD_CFG_RX_EN, 0);\n+\t\tnetc_port_wait_rx_empty(np, 1);\n+\t}\n+\n+\tnetc_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_RX_EN, 0);\n+\tnetc_port_wait_rx_empty(np, 0);\n+\n+\tif (read_poll_timeout(netc_port_rd, val, !(val & PSR_RX_BUSY),\n+\t\t\t 100, 10000, false, np, NETC_PSR))\n+\t\tdev_warn(np->switch_priv->dev, \"swp%d RX is busy\\n\",\n+\t\t\t np->dp->index);\n+\n+rx_disable:\n+\tnetc_port_rmw(np, NETC_POR, POR_RXDIS, POR_RXDIS);\n+}\n+\n+static void netc_port_mac_tx_enable(struct netc_port *np)\n+{\n+\tnetc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN,\n+\t\t\t PM_CMD_CFG_TX_EN);\n+\tnetc_port_rmw(np, NETC_POR, POR_TXDIS, 0);\n+}\n+\n+static void netc_port_wait_tx_empty(struct netc_port *np, int mac)\n+{\n+\tu32 val;\n+\n+\t/* PM_IEVENT_TX_EMPTY is a read-only bit, it is automatically set by\n+\t * hardware if TX FIFO is empty. And it is automatically cleared if\n+\t * TX FIFO is not empty.\n+\t */\n+\tif (read_poll_timeout(netc_port_rd, val, val & PM_IEVENT_TX_EMPTY,\n+\t\t\t 100, 10000, false, np, NETC_PM_IEVENT(mac)))\n+\t\tdev_warn(np->switch_priv->dev,\n+\t\t\t \"swp%d MAC%d: TX FIFO is not empty\\n\",\n+\t\t\t np->dp->index, mac);\n+}\n+\n+static void netc_port_mac_tx_graceful_stop(struct netc_port *np)\n+{\n+\tnetc_port_rmw(np, NETC_POR, POR_TXDIS, POR_TXDIS);\n+\n+\tif (is_netc_pseudo_port(np))\n+\t\treturn;\n+\n+\tnetc_port_wait_tx_empty(np, 0);\n+\tif (np->caps.pmac)\n+\t\tnetc_port_wait_tx_empty(np, 1);\n+\n+\tnetc_mac_port_rmw(np, NETC_PM_CMD_CFG(0), PM_CMD_CFG_TX_EN, 0);\n+}\n+\n+static void netc_mac_link_up(struct phylink_config *config,\n+\t\t\t struct phy_device *phy, unsigned int mode,\n+\t\t\t phy_interface_t interface, int speed,\n+\t\t\t int duplex, bool tx_pause, bool rx_pause)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct netc_port *np;\n+\n+\tnp = NETC_PORT(dp->ds, dp->index);\n+\tnetc_port_set_speed(np, speed);\n+\n+\tif (phy_interface_mode_is_rgmii(interface))\n+\t\tnetc_port_set_rgmii_mac(np, speed, duplex);\n+\n+\tif (interface == PHY_INTERFACE_MODE_RMII ||\n+\t interface == PHY_INTERFACE_MODE_REVMII ||\n+\t interface == PHY_INTERFACE_MODE_MII)\n+\t\tnetc_port_set_rmii_mii_mac(np, speed, duplex);\n+\n+\tnetc_port_mac_tx_enable(np);\n+\tnetc_port_mac_rx_enable(np);\n+}\n+\n+static void netc_mac_link_down(struct phylink_config *config,\n+\t\t\t unsigned int mode,\n+\t\t\t phy_interface_t interface)\n+{\n+\tstruct dsa_port *dp = dsa_phylink_to_port(config);\n+\tstruct netc_port *np;\n+\n+\tnp = NETC_PORT(dp->ds, dp->index);\n+\tnetc_port_mac_rx_graceful_stop(np);\n+\tnetc_port_mac_tx_graceful_stop(np);\n+}\n+\n+static const struct phylink_mac_ops netc_phylink_mac_ops = {\n+\t.mac_config\t\t= netc_mac_config,\n+\t.mac_link_up\t\t= netc_mac_link_up,\n+\t.mac_link_down\t\t= netc_mac_link_down,\n+};\n+\n static const struct dsa_switch_ops netc_switch_ops = {\n \t.get_tag_protocol\t\t= netc_get_tag_protocol,\n \t.setup\t\t\t\t= netc_setup,\n \t.teardown\t\t\t= netc_teardown,\n+\t.phylink_get_caps\t\t= netc_phylink_get_caps,\n };\n \n static int netc_switch_probe(struct pci_dev *pdev,\n@@ -564,6 +806,7 @@ static int netc_switch_probe(struct pci_dev *pdev,\n \tds->num_ports = priv->info->num_ports;\n \tds->num_tx_queues = NETC_TC_NUM;\n \tds->ops = &netc_switch_ops;\n+\tds->phylink_mac_ops = &netc_phylink_mac_ops;\n \tds->priv = priv;\n \tpriv->ds = ds;\n \ndiff --git a/drivers/net/dsa/netc/netc_platform.c b/drivers/net/dsa/netc/netc_platform.c\nindex abd599ea9c8d..bb4f92d238cb 100644\n--- a/drivers/net/dsa/netc/netc_platform.c\n+++ b/drivers/net/dsa/netc/netc_platform.c\n@@ -11,8 +11,46 @@ struct netc_switch_platform {\n \tconst struct netc_switch_info *info;\n };\n \n+static void imx94_switch_phylink_get_caps(int port,\n+\t\t\t\t\t struct phylink_config *config)\n+{\n+\tconfig->mac_capabilities = MAC_1000FD;\n+\n+\tswitch (port) {\n+\tcase 0 ... 1:\n+\t\t__set_bit(PHY_INTERFACE_MODE_SGMII,\n+\t\t\t config->supported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_2500BASEX,\n+\t\t\t config->supported_interfaces);\n+\t\tconfig->mac_capabilities |= MAC_2500FD;\n+\t\tfallthrough;\n+\tcase 2:\n+\t\tconfig->mac_capabilities |= MAC_10 | MAC_100;\n+\t\t__set_bit(PHY_INTERFACE_MODE_MII,\n+\t\t\t config->supported_interfaces);\n+\t\t__set_bit(PHY_INTERFACE_MODE_RMII,\n+\t\t\t config->supported_interfaces);\n+\t\t/* Port 0 and 1 do not support REVMII */\n+\t\tif (port == 2)\n+\t\t\t__set_bit(PHY_INTERFACE_MODE_REVMII,\n+\t\t\t\t config->supported_interfaces);\n+\n+\t\tphy_interface_set_rgmii(config->supported_interfaces);\n+\t\tbreak;\n+\tcase 3: /* CPU port */\n+\t\t__set_bit(PHY_INTERFACE_MODE_INTERNAL,\n+\t\t\t config->supported_interfaces);\n+\t\tconfig->mac_capabilities |= MAC_10FD | MAC_100FD |\n+\t\t\t\t\t MAC_2500FD;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n static const struct netc_switch_info imx94_info = {\n \t.num_ports = 4,\n+\t.phylink_get_caps = imx94_switch_phylink_get_caps,\n };\n \n static const struct netc_switch_platform netc_platforms[] = {\ndiff --git a/drivers/net/dsa/netc/netc_switch.h b/drivers/net/dsa/netc/netc_switch.h\nindex dac19bfba02b..eb65c36ecead 100644\n--- a/drivers/net/dsa/netc/netc_switch.h\n+++ b/drivers/net/dsa/netc/netc_switch.h\n@@ -34,6 +34,7 @@ struct netc_switch;\n \n struct netc_switch_info {\n \tu32 num_ports;\n+\tvoid (*phylink_get_caps)(int port, struct phylink_config *config);\n };\n \n struct netc_port_caps {\n@@ -70,6 +71,9 @@ struct netc_switch {\n \tstruct ntmp_user ntmp;\n };\n \n+#define NETC_PRIV(ds)\t\t\t((struct netc_switch *)((ds)->priv))\n+#define NETC_PORT(ds, port_id)\t\t(NETC_PRIV(ds)->ports[(port_id)])\n+\n /* Write/Read Switch base registers */\n #define netc_base_rd(r, o)\t\tnetc_read((r)->base + (o))\n #define netc_base_wr(r, o, v)\t\tnetc_write((r)->base + (o), v)\ndiff --git a/drivers/net/dsa/netc/netc_switch_hw.h b/drivers/net/dsa/netc/netc_switch_hw.h\nindex 0419f7f9207e..7d9afb493053 100644\n--- a/drivers/net/dsa/netc/netc_switch_hw.h\n+++ b/drivers/net/dsa/netc/netc_switch_hw.h\n@@ -67,6 +67,14 @@\n #define PQOSMR_VQMP\t\t\tGENMASK(19, 16)\n #define PQOSMR_QVMP\t\t\tGENMASK(23, 20)\n \n+#define NETC_POR\t\t\t0x100\n+#define POR_TXDIS\t\t\tBIT(0)\n+#define POR_RXDIS\t\t\tBIT(1)\n+\n+#define NETC_PSR\t\t\t0x104\n+#define PSR_TX_BUSY\t\t\tBIT(0)\n+#define PSR_RX_BUSY\t\t\tBIT(1)\n+\n #define NETC_PTCTMSDUR(a)\t\t(0x208 + (a) * 0x20)\n #define PTCTMSDUR_MAXSDU\t\tGENMASK(15, 0)\n #define PTCTMSDUR_SDU_TYPE\t\tGENMASK(17, 16)\n@@ -123,6 +131,24 @@ enum netc_mfo {\n #define NETC_PM_MAXFRM(a)\t\t(0x1014 + (a) * 0x400)\n #define PM_MAXFRAM\t\t\tGENMASK(15, 0)\n \n+#define NETC_PM_IEVENT(a)\t\t(0x1040 + (a) * 0x400)\n+#define PM_IEVENT_TX_EMPTY\t\tBIT(5)\n+#define PM_IEVENT_RX_EMPTY\t\tBIT(6)\n+\n+#define NETC_PM_IF_MODE(a)\t\t(0x1300 + (a) * 0x400)\n+#define PM_IF_MODE_IFMODE\t\tGENMASK(2, 0)\n+#define IFMODE_MII\t\t\t1\n+#define IFMODE_RMII\t\t\t3\n+#define IFMODE_RGMII\t\t\t4\n+#define IFMODE_SGMII\t\t\t5\n+#define PM_IF_MODE_REVMII\t\tBIT(3)\n+#define PM_IF_MODE_M10\t\t\tBIT(4)\n+#define PM_IF_MODE_HD\t\t\tBIT(6)\n+#define PM_IF_MODE_SSP\t\t\tGENMASK(14, 13)\n+#define SSP_100M\t\t\t0\n+#define SSP_10M\t\t\t1\n+#define SSP_1G\t\t\t2\n+\n #define NETC_PEMDIOCR\t\t\t0x1c00\n #define NETC_EMDIO_BASE\t\t\tNETC_PEMDIOCR\n \n", "prefixes": [ "v5", "net-next", "11/15" ] }