Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2230762/?format=api
{ "id": 2230762, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230762/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-46-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430002046.59739-46-richard.henderson@linaro.org>", "date": "2026-04-30T00:20:44", "name": "[v3,45/47] target/arm: Implement FMLALL{BB, BT, TB, TT} for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "62438d919199d2be9cea3da478c14f28c351660a", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.1/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-46-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/1.1/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230762/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230762/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=kkVOIYYk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5ZlC6NLFz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:28:07 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIFEL-00089j-UR; Wed, 29 Apr 2026 20:26:14 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFDo-0006V4-Fx\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:41 -0400", "from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIFDk-0007Xd-5M\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:25:39 -0400", "by mail-pj1-x102b.google.com with SMTP id\n 98e67ed59e1d1-35fb16e56efso180809a91.2\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:25:34 -0700 (PDT)", "from stoup.. ([180.233.125.15]) by smtp.gmail.com with ESMTPSA id\n 41be03b00d2f7-c7fd64f21b4sm3204112a12.21.2026.04.29.17.25.32\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Wed, 29 Apr 2026 17:25:33 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=linaro.org; s=google; t=1777508734; x=1778113534; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=sPx4OYP0T6C/6FxkTyH0Xnk5PleHFSWN0X4r8PZjzLU=;\n b=kkVOIYYkF58buSDimG72C4WMQpluVMgWIPDPlbF1OzcV+/SR7bY6OhLyTvd3i6i+wU\n 0I2l6yVsacDUu9OlQ9bu+zZeQ9gxfiaiG52zXVNEWlJjs5oPTbhqEp0/lL7djjv/6Wjj\n 8OxSMGEFkq9dGcbJdXnqz7BaQCwXFVG4I7mCR2Xkave6420RJU3pp3UQIMj6u5ttVLLz\n F6hfjhrqiDmsKn/wWYHl+HQMmPwZWKdMSZksxuUYKaK5F7S5uD61yOLjO97xX//sZ4Tl\n H1ZfL3B0AZ3AwIERg+D6yfyamEqdcVoWpzXRUWw9Ycc3BAqds2Xlwhqn3t8CFGQkOAEZ\n j8Eg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777508734; x=1778113534;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=sPx4OYP0T6C/6FxkTyH0Xnk5PleHFSWN0X4r8PZjzLU=;\n b=mKDu4Ht+VU3TD3QRUuOn5h1xpy09Vxh6BuULFahAUGvKHDIt/8gT4GyBgdyc7nNXjo\n ExEPTeJo/zL1ryXr5aiFalIuB/17+qCjOYGmdqNT+IM0wLscJxOROR2VwGiE4QZZBUlK\n 3AujCjYriCgME2l8FIu43j5YZDHWy5aAihOppO3erFM6uVcZe03at3+Ylp5/NhowGKPW\n 8J8KJ7ovu0bK8FIaxRbAdpmHYGrrjmg3UZSo/mpcectUHEyLUOpNCCv0lEcPmB72sWTL\n M/jGUZWqRIgQwUUEtLoya8hLF75MCNJAc9aaJLiF3TRhS2ndFzqxrNAqgAX/X2Ue//Kb\n aAUg==", "X-Gm-Message-State": "AOJu0YwNrBqCG4pcxR4UE6PRbzXfr1XoRwG6E4VhJKLeVIMcdfQ3bwcf\n 1X+563ZQs9LObwPtQ4JNAkkROEVz0HpXmS06mNuNVf4oLFmQfW7CBaeaJtG90tMIbZoT/7XPtTR\n z4CO4LJ8=", "X-Gm-Gg": "AeBDievbTk45eWk/U+c8LgqKXpVuWMek65v6UFRKu1YmOizJqaYVz0JpQkGKc2+1Smd\n 3ZseAENTXpKdVfof4jrQ8YGzgW59umZrtTD2f6EPHRl1ynS9OForrjffJzeEZgo+pBWs72h/4uQ\n /kqdYRN5siOPvi7JTtOj6S4wrlsbmgQkwAB/McvBSMZbU7yKb+mHybpw1bGvqBfckxL48J0uqor\n mTmWaxfIpFGMcxxvHGCpjzNKxxEBPLkZf6IDmb2jxBEi4+UtG+movMwoLhtaD4aqDJoGu+yxpZs\n QGo2C5O3cI1ykpgpMKl7T9Af41sOfDAjidhFTb25hnDBpDyN789DzA6Z4VJuuMIO10SdafCcq2C\n 1TD7SXOt310/5nXP1DFOOQHtITYLjdrZ1s3/SXnrWo+S217M78qRx0BMarBNZo09tG+KPnOZiXf\n YQLxtHc2YNrhN4Ug73uapEy8mxMCBidE24ONKvMpFm", "X-Received": "by 2002:a05:6a20:2585:b0:398:9d1e:1c6 with SMTP id\n adf61e73a8af0-3a3cf129ab6mr761850637.0.1777508733669;\n Wed, 29 Apr 2026 17:25:33 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-arm@nongnu.org", "Subject": "[PATCH v3 45/47] target/arm: Implement FMLALL{BB, BT, TB,\n TT} for AdvSIMD", "Date": "Thu, 30 Apr 2026 10:20:44 +1000", "Message-ID": "<20260430002046.59739-46-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260430002046.59739-1-richard.henderson@linaro.org>", "References": "<20260430002046.59739-1-richard.henderson@linaro.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::102b;\n envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-fp8-defs.h | 3 ++\n target/arm/tcg/fp8_helper.c | 81 ++++++++++++++++++++++++++++++++\n target/arm/tcg/translate-a64.c | 3 ++\n target/arm/tcg/a64.decode | 7 +++\n 4 files changed, 94 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h\nindex 7aa8366d94..802a3b430e 100644\n--- a/target/arm/tcg/helper-fp8-defs.h\n+++ b/target/arm/tcg/helper-fp8-defs.h\n@@ -26,3 +26,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr, ptr, env, i32)\n \n DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+\n+DEF_HELPER_FLAGS_5(gvec_fmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\n+DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env, i32)\ndiff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c\nindex 4825316b3b..79d66e2604 100644\n--- a/target/arm/tcg/fp8_helper.c\n+++ b/target/arm/tcg/fp8_helper.c\n@@ -953,3 +953,84 @@ void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,\n &env->vfp.fp_status[FPST_A64]);\n clear_tail(vd, oprsz, simd_maxsz(desc));\n }\n+\n+void HELPER(gvec_fmla_sb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ float_status stat = env->vfp.fp_status[FPST_A64];\n+ size_t idx = extract32(desc, SIMD_DATA_SHIFT, 2);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float32 *d = vd;\n+\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType fmt_n = FIELD_EX64(fpmr, FPMR, F8S1);\n+ FPMRType fmt_m = FIELD_EX64(fpmr, FPMR, F8S2);\n+ int scale = -FIELD_EX64(fpmr, FPMR, LSCALE);\n+\n+ set_flush_to_zero(0, &stat);\n+ set_flush_inputs_to_zero(0, &stat);\n+ set_default_nan_mode(true, &stat);\n+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)\n+ ? float_round_nearest_even_max\n+ : float_round_nearest_even, &stat);\n+\n+ for (size_t i = 0; i < nelem; i++) {\n+ FloatParts64 p0 = unpack_fp8(n[H1(4 * i + idx)], fmt_n, &stat);\n+ FloatParts64 p1 = unpack_fp8(m[H1(4 * i + idx)], fmt_m, &stat);\n+ FloatParts64 p2 = float32_unpack_canonical(d[H4(i)], &stat);\n+\n+ f8muladd(&p0, &p1, &p2, scale, &stat);\n+ d[H4(i)] = float32_round_pack_canonical(&p0, &stat);\n+ }\n+\n+ float_raise(get_float_exception_flags(&stat)\n+ & ~float_flag_input_denormal_used,\n+ &env->vfp.fp_status[FPST_A64]);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\n+\n+void HELPER(gvec_fmla_idx_sb)(void *vd, void *vn, void *vm,\n+ CPUARMState *env, uint32_t desc)\n+{\n+ float_status stat = env->vfp.fp_status[FPST_A64];\n+ size_t idx_n = extract32(desc, SIMD_DATA_SHIFT, 2);\n+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);\n+ size_t oprsz = simd_oprsz(desc);\n+ size_t nelem = oprsz / 4;\n+ uint8_t *n = vn;\n+ uint8_t *m = vm;\n+ float32 *d = vd;\n+\n+ uint64_t fpmr = env->vfp.fpmr;\n+ FPMRType fmt_n = FIELD_EX64(fpmr, FPMR, F8S1);\n+ FPMRType fmt_m = FIELD_EX64(fpmr, FPMR, F8S2);\n+ int scale = -FIELD_EX64(fpmr, FPMR, LSCALE);\n+\n+ set_flush_to_zero(0, &stat);\n+ set_flush_inputs_to_zero(0, &stat);\n+ set_default_nan_mode(true, &stat);\n+ set_float_rounding_mode(FIELD_EX64(fpmr, FPMR, OSM)\n+ ? float_round_nearest_even_max\n+ : float_round_nearest_even, &stat);\n+\n+ for (size_t seg = 0; seg < nelem; seg += 4) {\n+ FloatParts64 p1 = unpack_fp8(m[H1(4 * seg + idx_m)], fmt_m, &stat);\n+\n+ for (size_t j = 0; j < 4; j++) {\n+ size_t i = seg + j;\n+ FloatParts64 p0 = unpack_fp8(n[H1(4 * i + idx_n)], fmt_n, &stat);\n+ FloatParts64 p2 = float32_unpack_canonical(d[H4(i)], &stat);\n+\n+ f8muladd(&p0, &p1, &p2, scale, &stat);\n+ d[H4(i)] = float32_round_pack_canonical(&p0, &stat);\n+ }\n+ }\n+\n+ float_raise(get_float_exception_flags(&stat)\n+ & ~float_flag_input_denormal_used,\n+ &env->vfp.fp_status[FPST_A64]);\n+ clear_tail(vd, oprsz, simd_maxsz(desc));\n+}\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex 1c1d4ad2f7..946c16d439 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -7400,6 +7400,9 @@ static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,\n TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)\n TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_hb)\n \n+TRANS_FEAT(FMLALL_sb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)\n+TRANS_FEAT(FMLALL_sb_vi, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_idx_sb)\n+\n static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,\n gen_helper_gvec_3 * const fns[2])\n {\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex b89e83ce76..ef6d7dfeaa 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1209,6 +1209,10 @@ FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... ..... @qrrr_h\n FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \\\n &rxx idxm=0\n \n+%fmlall_idxn 30:1 22:1\n+FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \\\n+ &rxx idxm=0 idxn=%fmlall_idxn\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n@@ -1330,6 +1334,9 @@ SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... ..... @qrrx_s\n FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \\\n &rxx idxm=%hlm4\n \n+FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \\\n+ &rxx idxm=%hlm4 idxn=%fmlall_idxn\n+\n # Floating-point conditional select\n \n FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd\n", "prefixes": [ "v3", "45/47" ] }