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GET /api/1.1/patches/2230730/?format=api
{ "id": 2230730, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230730/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-18-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260430002046.59739-18-richard.henderson@linaro.org>", "date": "2026-04-30T00:20:16", "name": "[v3,17/47] target/arm: Implement FSCALE for AdvSIMD", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a34fa907e5c87046a0b4eb51b362a4ec68396688", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.1/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260430002046.59739-18-richard.henderson@linaro.org/mbox/", "series": [ { "id": 502175, "url": "http://patchwork.ozlabs.org/api/1.1/series/502175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502175", "date": "2026-04-30T00:20:06", "name": "target/arm: Implement FEAT_FP8", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502175/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230730/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230730/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=tUG9Hh7x;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5Zdl5Skxz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 10:23:23 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIF9v-0006lc-2r; Wed, 29 Apr 2026 20:21:39 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9o-0006YW-Tc\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:33 -0400", "from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <richard.henderson@linaro.org>)\n id 1wIF9m-0006KP-T3\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 20:21:32 -0400", "by mail-pf1-x436.google.com with SMTP id\n d2e1a72fcca58-82418b0178cso197076b3a.1\n for <qemu-devel@nongnu.org>; Wed, 29 Apr 2026 17:21:30 -0700 (PDT)", "from stoup.. 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helo=mail-pf1-x436.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Richard Henderson <richard.henderson@linaro.org>\n---\n target/arm/tcg/helper-a64-defs.h | 4 ++++\n target/arm/tcg/vec_internal.h | 4 ++++\n target/arm/tcg/translate-a64.c | 7 +++++++\n target/arm/tcg/vec_helper64.c | 16 ++++++++++++++++\n target/arm/tcg/a64.decode | 3 +++\n 5 files changed, 34 insertions(+)", "diff": "diff --git a/target/arm/tcg/helper-a64-defs.h b/target/arm/tcg/helper-a64-defs.h\nindex 215df1201b..b7880f773e 100644\n--- a/target/arm/tcg/helper-a64-defs.h\n+++ b/target/arm/tcg/helper-a64-defs.h\n@@ -152,6 +152,10 @@ DEF_HELPER_FLAGS_5(gvec_famin_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32\n DEF_HELPER_FLAGS_5(gvec_famax_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n DEF_HELPER_FLAGS_5(gvec_famin_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n \n+DEF_HELPER_FLAGS_5(gvec_fscale_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+DEF_HELPER_FLAGS_5(gvec_fscale_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, fpst, i32)\n+\n #ifndef CONFIG_USER_ONLY\n DEF_HELPER_2(exception_return, void, env, i64)\n #endif\ndiff --git a/target/arm/tcg/vec_internal.h b/target/arm/tcg/vec_internal.h\nindex cc2691b2f6..68b1116171 100644\n--- a/target/arm/tcg/vec_internal.h\n+++ b/target/arm/tcg/vec_internal.h\n@@ -345,6 +345,10 @@ float32 float32_famin(float32, float32, float_status *);\n float64 float64_famax(float64, float64, float_status *);\n float64 float64_famin(float64, float64, float_status *);\n \n+#define float16_fscale float16_scalbn\n+#define float32_fscale float32_scalbn\n+float64 float64_fscale(float64, int64_t, float_status *);\n+\n /*\n * Decode helper functions for predicate as counter.\n */\ndiff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c\nindex d2a4b0fadc..ac18ceeeab 100644\n--- a/target/arm/tcg/translate-a64.c\n+++ b/target/arm/tcg/translate-a64.c\n@@ -6496,6 +6496,13 @@ static gen_helper_gvec_3_ptr * const f_vector_famin[3] = {\n };\n TRANS_FEAT(FAMIN, aa64_faminmax, do_fp3_vector, a, 0, f_vector_famin)\n \n+static gen_helper_gvec_3_ptr * const f_vector_fscale[3] = {\n+ gen_helper_gvec_fscale_h,\n+ gen_helper_gvec_fscale_s,\n+ gen_helper_gvec_fscale_d,\n+};\n+TRANS_FEAT(FSCALE, aa64_f8cvt, do_fp3_vector, a, 0, f_vector_fscale)\n+\n static bool do_fmlal(DisasContext *s, arg_qrrr_e *a, bool is_s, bool is_2)\n {\n if (fp_access_check(s)) {\ndiff --git a/target/arm/tcg/vec_helper64.c b/target/arm/tcg/vec_helper64.c\nindex b5ad67b5e0..5479d98daf 100644\n--- a/target/arm/tcg/vec_helper64.c\n+++ b/target/arm/tcg/vec_helper64.c\n@@ -175,3 +175,19 @@ DO_3OP(gvec_famax_s, float32_famax, float32)\n DO_3OP(gvec_famin_s, float32_famin, float32)\n DO_3OP(gvec_famax_d, float64_famax, float64)\n DO_3OP(gvec_famin_d, float64_famin, float64)\n+\n+float64 float64_fscale(float64 n, int64_t m, float_status *s)\n+{\n+ /*\n+ * Given the 'int' parameter of float64_scalbn, we have to saturate\n+ * the 'int64_t' parameter of the operation to some value. Since\n+ * float64 has an 11-bit exponent, saturating to 12 bits is sufficient\n+ * to ensure that DBL_TRUE_MIN can be made to overflow.\n+ */\n+ int sat_m = MIN(MAX(m, -0xfff), 0xfff);\n+ return float64_scalbn(n, sat_m, s);\n+}\n+\n+DO_3OP(gvec_fscale_h, float16_fscale, int16_t)\n+DO_3OP(gvec_fscale_s, float32_fscale, int32_t)\n+DO_3OP(gvec_fscale_d, float64_fscale, int64_t)\ndiff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode\nindex 666a293540..02c7264cb9 100644\n--- a/target/arm/tcg/a64.decode\n+++ b/target/arm/tcg/a64.decode\n@@ -1198,6 +1198,9 @@ FAMAX 0.00 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n FAMIN 0.10 1110 110 ..... 00011 1 ..... ..... @qrrr_h\n FAMIN 0.10 1110 1.1 ..... 11011 1 ..... ..... @qrrr_sd\n \n+FSCALE 0.10 1110 110 ..... 00111 1 ..... ..... @qrrr_h\n+FSCALE 0.10 1110 1.1 ..... 11111 1 ..... ..... @qrrr_sd\n+\n ### Advanced SIMD scalar x indexed element\n \n FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h\n", "prefixes": [ "v3", "17/47" ] }