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{ "id": 2230644, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230644/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOr_LppNZ39evsqLC02=SOeGGNbnwJ+QadHaPEoWg8EWtA@mail.gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<CAMe9rOr_LppNZ39evsqLC02=SOeGGNbnwJ+QadHaPEoWg8EWtA@mail.gmail.com>", "date": "2026-04-29T22:29:32", "name": "x86_cse: Convert CONST_VECTOR load to constant integer load", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dded8559aa285f5ff92ef87da875e7d11f1c7da3", "submitter": { "id": 4387, "url": "http://patchwork.ozlabs.org/api/1.1/people/4387/?format=api", "name": "H.J. Lu", "email": "hjl.tools@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOr_LppNZ39evsqLC02=SOeGGNbnwJ+QadHaPEoWg8EWtA@mail.gmail.com/mbox/", "series": [ { "id": 502162, "url": "http://patchwork.ozlabs.org/api/1.1/series/502162/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=502162", "date": "2026-04-29T22:29:32", "name": "x86_cse: Convert CONST_VECTOR load to constant integer load", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502162/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230644/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230644/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=bDmixQeC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Wed, 29 Apr 2026\n 15:30:09 -0700 (PDT)", "MIME-Version": "1.0", "From": "\"H.J. Lu\" <hjl.tools@gmail.com>", "Date": "Thu, 30 Apr 2026 06:29:32 +0800", "X-Gm-Features": "AVHnY4LWrY1WLHgASf1Ye46SFuel4Qrc4qZRCW_O2KWJ7kUQKjZoWKrMkFtKz10", "Message-ID": "\n <CAMe9rOr_LppNZ39evsqLC02=SOeGGNbnwJ+QadHaPEoWg8EWtA@mail.gmail.com>", "Subject": "[PATCH] x86_cse: Convert CONST_VECTOR load to constant integer load", "To": "GCC Patches <gcc-patches@gcc.gnu.org>, Uros Bizjak <ubizjak@gmail.com>,\n Hongtao Liu <hongtao.liu@intel.com>", "Content-Type": "multipart/mixed; boundary=\"000000000000f2bdbf0650a0e3ea\"", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Convert CONST_VECTOR load no larger than integer register:\n\n (set (reg:V2SI 106)\n (const_vector:V2SI [(const_int 1 [1]) repeated x2]))\n\nto constant integer load:\n\n (set (subreg:DI (reg:V2SI 106 [ _20 ]) 0)\n (const_int 4294967297 [0x100000001]))\n\nand keep redundant constant integer load. Generate zero CONST_VECTOR\nload which works for both MMX and XMM registers.\n\ngcc/\n\nPR target/125026\nPR target/125032\n* config/i386/i386-features.cc (ix86_place_single_vector_set):\nDon't check CONST_VECTOR load size.\n(replace_vector_const): Handle constant integer load.\n(x86_cse::x86_cse): Convert CONST_VECTOR load no larger than\ninteger to constant integer load and keep redundant constant\ninteger load. Generate zero CONST_VECTOR load.\n\nTested on Linux/x86-64 and Linux/i686.\n\ngcc/testsuite/\n\nPR target/125026\nPR target/125032\n* gcc.target/i386/pr125026.c: New test.\n* gcc.target/i386/pr125032-1.c: Likewise.\n* gcc.target/i386/pr125032-2.c: Likewise.", "diff": "From f5119f14ee1202c587aadcbff54ff94937c6511d Mon Sep 17 00:00:00 2001\nFrom: \"H.J. Lu\" <hjl.tools@gmail.com>\nDate: Wed, 29 Apr 2026 19:50:38 +0800\nSubject: [PATCH] x86_cse: Convert CONST_VECTOR load to constant integer load\n\nConvert CONST_VECTOR load no larger than integer register:\n\n (set (reg:V2SI 106)\n (const_vector:V2SI [(const_int 1 [1]) repeated x2]))\n\nto constant integer load:\n\n (set (subreg:DI (reg:V2SI 106 [ _20 ]) 0)\n (const_int 4294967297 [0x100000001]))\n\nand keep redundant constant integer load. Generate zero CONST_VECTOR\nload which works for both MMX and XMM registers.\n\nTested on Linux/x86-64 and Linux/i686.\n\ngcc/\n\n\tPR target/125026\n\tPR target/125032\n\t* config/i386/i386-features.cc (ix86_place_single_vector_set):\n\tDon't check CONST_VECTOR load size.\n\t(replace_vector_const): Handle constant integer load.\n\t(x86_cse::x86_cse): Convert CONST_VECTOR load no larger than\n\tinteger to constant integer load and keep redundant constant\n\tinteger load. Generate zero CONST_VECTOR load.\n\ngcc/testsuite/\n\n\tPR target/125026\n\tPR target/125032\n\t* gcc.target/i386/pr125026.c: New test.\n\t* gcc.target/i386/pr125032-1.c: Likewise.\n\t* gcc.target/i386/pr125032-2.c: Likewise.\n\nSigned-off-by: H.J. Lu <hjl.tools@gmail.com>\n---\n gcc/config/i386/i386-features.cc | 97 ++++++++++++++++------\n gcc/testsuite/gcc.target/i386/pr125026.c | 18 ++++\n gcc/testsuite/gcc.target/i386/pr125032-1.c | 30 +++++++\n gcc/testsuite/gcc.target/i386/pr125032-2.c | 15 ++++\n 4 files changed, 135 insertions(+), 25 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125026.c\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125032-1.c\n create mode 100644 gcc/testsuite/gcc.target/i386/pr125032-2.c\n\ndiff --git a/gcc/config/i386/i386-features.cc b/gcc/config/i386/i386-features.cc\nindex a04efb52a3e..123c86a0fac 100644\n--- a/gcc/config/i386/i386-features.cc\n+++ b/gcc/config/i386/i386-features.cc\n@@ -3322,16 +3322,10 @@ ix86_place_single_vector_set (rtx dest, rtx src, bitmap bbs,\n \t}\n }\n \n- /* CONST_VECTOR load no larger than integer register\n-\n- (set (reg:V2QI 294)\n-\t (const_vector:V2QI [(const_int 0 [0]) repeated x2]))\n-\n- can use integer load. */\n+ /* NB: CONST_VECTOR load is generated and handled in x86_cse. */\n if (load\n- && load->kind == X86_CSE_VEC_DUP\n- && (!CONST_VECTOR_P (src)\n-\t || GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD))\n+ && !CONST_VECTOR_P (src)\n+ && load->kind == X86_CSE_VEC_DUP)\n {\n /* Get the source from LOAD as (reg:SI 99) in\n \n@@ -3645,7 +3639,9 @@ replace_vector_const (machine_mode vector_mode, rtx vector_const,\n \n rtx replace;\n /* Replace the source operand with VECTOR_CONST. */\n- if (SUBREG_P (src) || mode == vector_mode)\n+ if (SUBREG_P (src)\n+\t || mode == vector_mode\n+\t || CONST_INT_P (vector_const))\n \treplace = vector_const;\n else\n \t{\n@@ -3687,6 +3683,11 @@ replace_vector_const (machine_mode vector_mode, rtx vector_const,\n \t print_rtl_single (dump_file, insn);\n \t}\n SET_SRC (set) = replace;\n+ if (CONST_INT_P (replace))\n+\t{\n+\t dest = gen_rtx_SUBREG (scalar_mode, dest, 0);\n+\t SET_DEST (set) = dest;\n+\t}\n /* Drop possible dead definitions. */\n PATTERN (insn) = set;\n INSN_CODE (insn) = -1;\n@@ -4702,7 +4703,8 @@ pass_x86_cse::x86_cse (void)\n if (load->count >= load->threshold)\n {\n \tmachine_mode mode;\n-\trtx reg, broadcast_source, broadcast_reg;\n+\trtx reg, broadcast_reg;\n+\trtx broadcast_source = nullptr;\n \treplaced = true;\n \tswitch (load->kind)\n \t {\n@@ -4717,9 +4719,61 @@ pass_x86_cse::x86_cse (void)\n \t load->broadcast_reg = broadcast_reg;\n \t break;\n \n+\t case X86_CSE_VEC_DUP:\n+\t if (CONST_INT_P (load->val)\n+\t\t&& (load->val == CONST0_RTX (load->mode)\n+\t\t || load->size <= UNITS_PER_WORD))\n+\t {\n+\t\t/* Generate CONST_VECTOR load. */\n+\t\tmode = ix86_get_vector_cse_mode (load->size,\n+\t\t\t\t\t\t load->mode);\n+\n+\t\tif (load->val == CONST0_RTX (load->mode))\n+\t\t broadcast_source = CONST0_RTX (mode);\n+\t\telse if (load->val == CONSTM1_RTX (load->mode))\n+\t\t broadcast_source = CONSTM1_RTX (mode);\n+\t\telse\n+\t\t {\n+\t\t int nunits = GET_MODE_NUNITS (mode);\n+\t\t rtvec v = rtvec_alloc (nunits);\n+\t\t for (int j = 0; j < nunits ; j++)\n+\t\t RTVEC_ELT (v, j) = load->val;\n+\t\t broadcast_source = gen_rtx_CONST_VECTOR (mode, v);\n+\t\t }\n+\n+\t\t/* NB: Zero CONST_VECTOR load works for MMX and XMM\n+\t\t registers. */\n+\t\tif (load->size <= UNITS_PER_WORD)\n+\t\t {\n+\t\t /* Convert CONST_VECTOR load no larger than integer\n+\t\t register:\n+\n+\t\t (set (reg:V2SI 106)\n+\t\t\t (const_vector:V2SI [(const_int 1 [1]) repeated x2]))\n+\n+\t\t to constant integer load:\n+\n+\t\t (set (subreg:DI (reg:V2SI 106 [ _20 ]) 0)\n+\t\t\t (const_int 4294967297 [0x100000001]))\n+\t\t */\n+\t\t machine_mode int_mode\n+\t\t = int_mode_for_mode (mode).require ();\n+\t\t broadcast_source = simplify_subreg (int_mode,\n+\t\t\t\t\t\t\tbroadcast_source,\n+\t\t\t\t\t\t\tmode, 0);\n+\t\t gcc_assert (broadcast_source != nullptr);\n+\t\t replace_vector_const (mode, broadcast_source,\n+\t\t\t\t\t load->insns, int_mode);\n+\t\t /* Keep redundant constant integer load. */\n+\t\t load->broadcast_source = nullptr;\n+\t\t load->broadcast_reg = nullptr;\n+\t\t break;\n+\t\t }\n+\t }\n+\t /* FALLTHRU */\n+\n \t case X86_CSE_CONST0_VECTOR:\n \t case X86_CSE_CONSTM1_VECTOR:\n-\t case X86_CSE_VEC_DUP:\n \t mode = ix86_get_vector_cse_mode (load->size, load->mode);\n \t broadcast_reg = gen_reg_rtx (mode);\n \t if (load->def_insn)\n@@ -4744,18 +4798,7 @@ pass_x86_cse::x86_cse (void)\n \t\t broadcast_source = CONSTM1_RTX (mode);\n \t\t break;\n \t\tcase X86_CSE_VEC_DUP:\n-\t\t if (CONST_INT_P (load->val)\n-\t\t && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)\n-\t\t {\n-\t\t /* CONST_VECTOR load no larger than integer\n-\t\t\t register size can use integer load. */\n-\t\t int nunits = GET_MODE_NUNITS (mode);\n-\t\t rtvec v = rtvec_alloc (nunits);\n-\t\t for (int j = 0; j < nunits ; j++)\n-\t\t\tRTVEC_ELT (v, j) = load->val;\n-\t\t broadcast_source = gen_rtx_CONST_VECTOR (mode, v);\n-\t\t }\n-\t\t else\n+\t\t if (!broadcast_source)\n \t\t {\n \t\t reg = gen_reg_rtx (load->mode);\n \t\t broadcast_source = gen_rtx_VEC_DUPLICATE (mode,\n@@ -4845,9 +4888,13 @@ pass_x86_cse::x86_cse (void)\n \t\t\t\t\t updated_gnu_tls_insns,\n \t\t\t\t\t updated_gnu2_tls_insns);\n \t\t break;\n+\t\tcase X86_CSE_VEC_DUP:\n+\t\t /* Keep redundant constant integer load. */\n+\t\t if (!load->broadcast_reg)\n+\t\t break;\n+\t\t /* FALLTHRU */\n \t\tcase X86_CSE_CONST0_VECTOR:\n \t\tcase X86_CSE_CONSTM1_VECTOR:\n-\t\tcase X86_CSE_VEC_DUP:\n \t\t ix86_place_single_vector_set (load->broadcast_reg,\n \t\t\t\t\t\tload->broadcast_source,\n \t\t\t\t\t\tload->bbs,\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125026.c b/gcc/testsuite/gcc.target/i386/pr125026.c\nnew file mode 100644\nindex 00000000000..96ac6a9ef20\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125026.c\n@@ -0,0 +1,18 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-O2 -march=x86-64\" } */\n+\n+extern void a(int[]);\n+int b;\n+int d(int e, volatile int f) {\n+ b = f - e;\n+ int t[2] = {b, b};\n+ a(t);\n+}\n+void g(int h[1]) {\n+ if (d(0, 1))\n+ h[0] = 0;\n+ d(0, 1);\n+}\n+\n+/* { dg-final { scan-assembler-times \"movabsq\\[ \\\\t\\]+\\\\\\$4294967297, %r\\[a-z0-9\\]+\" 2 { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler-not \"xmm\" { target { ! ia32 } } } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125032-1.c b/gcc/testsuite/gcc.target/i386/pr125032-1.c\nnew file mode 100644\nindex 00000000000..7c54bab332a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125032-1.c\n@@ -0,0 +1,30 @@\n+/* { dg-do compile { target { ia32 && pie } } } */\n+/* { dg-options \"-O2 -march=i686 -mmmx -fPIE\" } */\n+\n+typedef int __m64 __attribute__((__vector_size__(8)));\n+typedef short __v4hi __attribute__((__vector_size__(8)));\n+typedef char __v8qi __attribute__((__vector_size__(8)));\n+int mmx_composite_over_n_8_0565_info_0, mmx_composite_over_n_8_0565_w;\n+long long mmx_composite_over_n_8_0565_m3;\n+__m64 mmx_composite_over_n_8_0565_v2, mmx_composite_over_n_8_0565_v3;\n+__m64 in_over(__m64 src)\n+{\n+ __m64 __m1 = src, __m2;\n+ return (__m64)__builtin_ia32_pmullw((__v4hi)__m1, (__v4hi)__m2);\n+}\n+__m64 load8888()\n+{\n+ __m64 __m2, __m1;\n+ return (__m64)__builtin_ia32_punpcklbw((__v8qi)__m1, (__v8qi)__m2);\n+}\n+void mmx_composite_over_n_8_0565()\n+{\n+ __m64 vsrc = load8888();\n+ mmx_composite_over_n_8_0565_w = mmx_composite_over_n_8_0565_info_0;\n+ while (mmx_composite_over_n_8_0565_info_0)\n+ if (mmx_composite_over_n_8_0565_m3)\n+ {\n+\tmmx_composite_over_n_8_0565_v2 = in_over(vsrc);\n+\tmmx_composite_over_n_8_0565_v3 = in_over(vsrc);\n+ }\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/pr125032-2.c b/gcc/testsuite/gcc.target/i386/pr125032-2.c\nnew file mode 100644\nindex 00000000000..71b072a7bfe\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/pr125032-2.c\n@@ -0,0 +1,15 @@\n+/* { dg-do compile { target fpic } } */\n+/* { dg-options \"-O2 -fPIC\" } */\n+\n+long _HMAC_SHA256_Init_Klen;\n+char _crypt_HMAC_SHA256_Init_pad[64];\n+char _crypt_HMAC_SHA256_Init_pad_0, _crypt_HMAC_SHA256_Init_K_0;\n+void _crypt_HMAC_SHA256_Init_i() {\n+ if (_HMAC_SHA256_Init_Klen)\n+ _HMAC_SHA256_Init_Klen = 2;\n+ long __trans_tmp_1 =\n+ __builtin_dynamic_object_size(_crypt_HMAC_SHA256_Init_pad, 0);\n+ __builtin___memset_chk(_crypt_HMAC_SHA256_Init_pad, 2, 64, __trans_tmp_1);\n+ for (; _HMAC_SHA256_Init_Klen;)\n+ _crypt_HMAC_SHA256_Init_pad_0 ^= _crypt_HMAC_SHA256_Init_K_0;\n+}\n-- \n2.53.0\n\n", "prefixes": [] }