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GET /api/1.1/patches/2230486/?format=api
{ "id": 2230486, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230486/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429190532.26538-9-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429190532.26538-9-mohamed@unpredictable.fr>", "date": "2026-04-29T19:05:25", "name": "[v21,08/15] hvf: arm: allow exposing minimal PMU for kernel-irqchip=on", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "10538611a4e2b4f8e564e15cd57ebd4decaeb2c5", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/1.1/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429190532.26538-9-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 502138, "url": "http://patchwork.ozlabs.org/api/1.1/series/502138/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502138", "date": "2026-04-29T19:05:29", "name": "HVF: Add support for platform vGIC and nested virtualisation", "version": 21, "mbox": "http://patchwork.ozlabs.org/series/502138/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230486/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230486/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=GHvgYPUZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Wed, 29 Apr 2026 15:06:07 -0400", "from outbound.ms.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-3a-60-percent-6 (Postfix) with ESMTPS id\n 501DA18002E8; Wed, 29 Apr 2026 19:06:01 +0000 (UTC)", "from localhost.localdomain (unknown [17.57.154.37])\n by p00-icloudmta-asmtp-us-west-3a-60-percent-6 (Postfix) with ESMTPSA id\n 78D5618005CA; Wed, 29 Apr 2026 19:05:58 +0000 (UTC)" ], "X-ICL-Out-Info": "\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJAE1fDl4fBBdGGVUERx5dVl4eGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCAEkKXQJYAF4LTgZeD0YLXVQXWwxaDlYwTBZDH1IPWxNNGVEBUkVUAgdYRxRHDg8TTAtHAlo0Vh9UGVoD", "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1777489563; x=1780081563;\n bh=1/v/2pEP4nLxYkH1Z43qTSg56sckGJLMILFhZ9ygbpU=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:Content-Type:x-icloud-hme;\n b=GHvgYPUZ7tZ2cjCzZnPiDgPFeO88hhi7vFOhs0xZZsAZwLZcPA0nWPAggRAOOSwFOxQLxduaMWt1gDyCboShKLTOi3kEytOq9jdxR67mk10WUL9B6rXEzNho4mroC4imHW6WNlKLZ0W8wrFkecm0g9McHHVjcVBmd6ul4hI0ocKPRZXNUtF51vJqcEetvJb45PukqF17Fj7xFP+tXsdRWCQof7cfPmJJL9/O/NhckjCAKxl1c6awAkUff+SS0/KNCKL0HdMwDibHntQsWeUZ1XiMZp9Q/Ss8PQjK48FFDBlFyb12VMnNVli2HdSFqvmz/DRuevsYtotwFkuYOwIIgA==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Phil Dennis-Jordan <phil@philjordan.eu>,\n Yanan Wang <wangyanan55@huawei.com>, Paolo Bonzini <pbonzini@redhat.com>,\n Roman Bolshakov <rbolshakov@ddn.com>,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n qemu-arm@nongnu.org, Zhao Liu <zhao1.liu@intel.com>,\n Alexander Graf <agraf@csgraf.de>, Eduardo Habkost <eduardo@habkost.net>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Mohamed Mediouni <mohamed@unpredictable.fr>", "Subject": "[PATCH v21 08/15] hvf: arm: allow exposing minimal PMU for\n kernel-irqchip=on", "Date": "Wed, 29 Apr 2026 21:05:25 +0200", "Message-ID": "<20260429190532.26538-9-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260429190532.26538-1-mohamed@unpredictable.fr>", "References": "<20260429190532.26538-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Type": "text/plain; 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helo=outbound.ms.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When running with the Apple vGIC, a minimum PMU is exposed by Hypervisor.framework\nif a valid PMUVer register value is set. That PMU isn't exposed otherwise.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/arm/hvf/hvf.c | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)", "diff": "diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c\nindex 9d64f2e1a5..390a3529ff 100644\n--- a/target/arm/hvf/hvf.c\n+++ b/target/arm/hvf/hvf.c\n@@ -1145,6 +1145,25 @@ static bool hvf_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)\n \n clamp_id_aa64mmfr0_parange_to_ipa_size(&host_isar);\n \n+ /*\n+ * Windows wants at least the PMU's cycles counter to be available.\n+ *\n+ * With kernel-irqchip=off, we \"emulate\" the cycles counter\n+ * in reference to time in QEMU. Having that, even with\n+ * ID_AA64DFR0_EL1.PMUVer = 0 is enough to make Windows happy.\n+ *\n+ * As it's a very inaccurate implementation with its only purpose\n+ * being making Windows boot, expose ID_AA64DFR0_EL1.PMUVer = 0\n+ * when kernel-irqchip=off.\n+ *\n+ * When kernel-irqchip=on *and* ID_AA64DFR0_EL1.PMUVer = 1,\n+ * the OS provides its own PMU emulation, which is currently\n+ * a cycles counter only emulation.\n+ */\n+ if (hvf_irqchip_in_kernel()) {\n+ FIELD_DP64_IDREG(&host_isar, ID_AA64DFR0, PMUVER, 0x1);\n+ }\n+\n ahcf->isar = host_isar;\n \n /*\n", "prefixes": [ "v21", "08/15" ] }