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GET /api/1.1/patches/2230484/?format=api
{ "id": 2230484, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230484/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429190532.26538-16-mohamed@unpredictable.fr/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429190532.26538-16-mohamed@unpredictable.fr>", "date": "2026-04-29T19:05:32", "name": "[v21,15/15] hvf: arm: enable vGIC by default for virt-11.1 and later", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2bd112438dfd9845846940b45a469d316bebb15b", "submitter": { "id": 91318, "url": "http://patchwork.ozlabs.org/api/1.1/people/91318/?format=api", "name": "Mohamed Mediouni", "email": "mohamed@unpredictable.fr" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429190532.26538-16-mohamed@unpredictable.fr/mbox/", "series": [ { "id": 502138, "url": "http://patchwork.ozlabs.org/api/1.1/series/502138/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=502138", "date": "2026-04-29T19:05:29", "name": "HVF: Add support for platform vGIC and nested virtualisation", "version": 21, "mbox": "http://patchwork.ozlabs.org/series/502138/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230484/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230484/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=unpredictable.fr header.i=@unpredictable.fr\n header.a=rsa-sha256 header.s=sig1 header.b=KJWnFtE1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5RdJ20Nhz1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 30 Apr 2026 05:07:32 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wIAFM-0002SP-1u; Wed, 29 Apr 2026 15:06:56 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wIAEz-00027H-A7\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 15:06:35 -0400", "from p-west3-cluster5-host9-snip4-4.eps.apple.com ([57.103.72.87]\n helo=outbound.ms.icloud.com)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mohamed@unpredictable.fr>)\n id 1wIAEt-0000XI-99\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 15:06:32 -0400", "from outbound.ms.icloud.com (unknown [127.0.0.2])\n by p00-icloudmta-asmtp-us-west-3a-60-percent-6 (Postfix) with ESMTPS id\n CD42F18002FE; Wed, 29 Apr 2026 19:06:20 +0000 (UTC)", "from localhost.localdomain (unknown [17.57.154.37])\n by p00-icloudmta-asmtp-us-west-3a-60-percent-6 (Postfix) with ESMTPSA id\n 7BA1118000B2; Wed, 29 Apr 2026 19:06:17 +0000 (UTC)" ], "X-ICL-Out-Info": "\n HUtFAUMHWwJACUgBTUQeDx5WFlZNRAJCTQFIHV8DWRxBAUkdXw9LVxQEFVwFVgZXFHkNXR1FDlYZWgxSD1sOHBZLWFUJCgZdGFgVVgl3HlwASx1XBFQfUxJVHR0LRUtAEwRJB01fDl4fBBdGGVUERx5dVl4eGQJRHFYNV0NUBF9QSQxBUGxaAEcXSB1dGVlvUF0cDhhZG0AVXRFQGVYJXhUXHkFNWgJWTQVKA18BWwZCAEkKXQJYAF4LTgZeD0YDRhQVXAVWBlcUeQ1dHUUOVhlaDFIPWw4cFktGExlOG1dNWg1AGVgGbRRWFVIEWQ==", "Dkim-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=unpredictable.fr;\n s=sig1; t=1777489584; x=1780081584;\n bh=/HRGlWLuPFRz+dTWvUYo4FsxGpbjTjjRzSa0MkdCpkU=;\n h=From:To:Subject:Date:Message-ID:MIME-Version:x-icloud-hme;\n b=KJWnFtE1fx6DZYomDHGzYTbT2mTYawxvVhOZKXzubCI1/pXHcMcm0oEQlfZuH2p2XQ3vMEjKAPplyANsIT7LgHFLYIaKgPcOM3dTpVi3a6dB9b75MCukyY0vOxKppa+muInJAPt/LXCrkQNKRJLBBnAOcimBz/l9ViSDuH5cJnrNZ7QDEvPvRim9aojvGHOdXum0/zB4lyaTMtNe7klb6wT9li9dPJrLoZuYflvXLIaGnwhtYxbsF0bHF3dYXSiTtgmeom7qj4nuTdWwqhOX2eOZ9njS+BzbhJIfPCmwIN3lWhZXeCQN1c9mCSOx5gtcd2SRFMS47JOCq+aT7hs+0g==", "mail-alias-created-date": "1752046281608", "From": "Mohamed Mediouni <mohamed@unpredictable.fr>", "To": "qemu-devel@nongnu.org", "Cc": "Phil Dennis-Jordan <phil@philjordan.eu>,\n Yanan Wang <wangyanan55@huawei.com>, Paolo Bonzini <pbonzini@redhat.com>,\n Roman Bolshakov <rbolshakov@ddn.com>,\n =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>,\n qemu-arm@nongnu.org, Zhao Liu <zhao1.liu@intel.com>,\n Alexander Graf <agraf@csgraf.de>, Eduardo Habkost <eduardo@habkost.net>,\n Marcel Apfelbaum <marcel.apfelbaum@gmail.com>,\n Peter Maydell <peter.maydell@linaro.org>,\n Mohamed Mediouni <mohamed@unpredictable.fr>,\n Manos Pitsidianakis <manos.pitsidianakis@linaro.org>", "Subject": "[PATCH v21 15/15] hvf: arm: enable vGIC by default for virt-11.1 and\n later", "Date": "Wed, 29 Apr 2026 21:05:32 +0200", "Message-ID": "<20260429190532.26538-16-mohamed@unpredictable.fr>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260429190532.26538-1-mohamed@unpredictable.fr>", "References": "<20260429190532.26538-1-mohamed@unpredictable.fr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI5MDE5MCBTYWx0ZWRfX+0TMmKyr6yhw\n QjwkQTxPQrFiSWvAAuTPB+sU1Rej3kxV05hBCTgz8qR4Ubd94+IjUuhqDvO9noTrvDKZ1Qs5UPw\n iD+ogko8iT3ij8evzhrt9sVCKrumHzgU9NM938PlIM08UhW9rUPXjgVrFGxFCiGY5vsTp0r60Ci\n QxFT1HPDu2sXuFF2lhnl4MRG1wgu6Ksg2uJKXRG/xrAj1V1ImJ7UXUFenufQatW3b7VdlItRjOy\n A0ZuLG9GIATwKMOnGdSaVjXeto24zXMBHKqppBTAL02nybWzAoQFyeOwzcitx5O8LyWS+gbgnXZ\n z3LiNNouVFHrKjA/ld07HKH6ETQncw2s/fkiINMpB9mNH8E7v9v2qZo9FBAKLE=", "X-Proofpoint-GUID": "SEtOQLs6EVwDf8RR6I4lFViaEE2pVzA_", "X-Authority-Info-Out": "v=2.4 cv=Hq172kTS c=1 sm=1 tr=0 ts=69f256ae\n cx=c_apl:c_pps:t_out a=qkKslKyYc0ctBTeLUVfTFg==:117 a=A5OVakUREuEA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=KKAkSRfTAAAA:8 a=PDSgDrDRFnq58FnMM9AA:9\n a=cvBusfyB2V15izCimMoJ:22", "X-Proofpoint-ORIG-GUID": "SEtOQLs6EVwDf8RR6I4lFViaEE2pVzA_", "Received-SPF": "pass client-ip=57.103.72.87;\n envelope-from=mohamed@unpredictable.fr; helo=outbound.ms.icloud.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Save states are incompatible between kernel-irqchip=on and off on HVF due to opaque vGIC state.\n\nSigned-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>\nReviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>\n---\n accel/hvf/hvf-all.c | 11 +++++++++++\n hw/arm/virt.c | 14 ++++++++++++++\n include/hw/arm/virt.h | 2 ++\n include/hw/core/boards.h | 1 +\n include/system/hvf_int.h | 1 +\n 5 files changed, 29 insertions(+)", "diff": "diff --git a/accel/hvf/hvf-all.c b/accel/hvf/hvf-all.c\nindex 48c653630f..4e5a8c58a8 100644\n--- a/accel/hvf/hvf-all.c\n+++ b/accel/hvf/hvf-all.c\n@@ -25,6 +25,7 @@\n bool hvf_allowed;\n bool hvf_kernel_irqchip;\n bool hvf_nested_virt;\n+bool hvf_kernel_irqchip_override;\n \n void hvf_nested_virt_enable(bool nested_virt) {\n hvf_nested_virt = nested_virt;\n@@ -203,6 +204,13 @@ static int hvf_accel_init(AccelState *as, MachineState *ms)\n }\n }\n \n+ if (mc->get_kernel_irqchip_default) {\n+ bool kernel_irqchip_default = mc->get_kernel_irqchip_default(ms);\n+ if (!hvf_kernel_irqchip_override) {\n+ hvf_kernel_irqchip = kernel_irqchip_default;\n+ }\n+ }\n+\n ret = hvf_arch_vm_create(ms, (uint32_t)pa_range);\n if (ret == HV_DENIED) {\n error_report(\"Could not access HVF. Is the executable signed\"\n@@ -229,6 +237,8 @@ static void hvf_set_kernel_irqchip(Object *obj, Visitor *v,\n Error **errp)\n {\n OnOffSplit mode;\n+\n+ hvf_kernel_irqchip_override = true;\n if (!visit_type_OnOffSplit(v, name, &mode, errp)) {\n return;\n }\n@@ -268,6 +278,7 @@ static void hvf_accel_class_init(ObjectClass *oc, const void *data)\n ac->init_machine = hvf_accel_init;\n ac->allowed = &hvf_allowed;\n ac->gdbstub_supported_sstep_flags = hvf_gdbstub_sstep_flags;\n+ hvf_kernel_irqchip_override = false;\n hvf_kernel_irqchip = false;\n object_class_property_add(oc, \"kernel-irqchip\", \"on|off|split\",\n NULL, hvf_set_kernel_irqchip,\ndiff --git a/hw/arm/virt.c b/hw/arm/virt.c\nindex ad0a459987..3464cf9f9e 100644\n--- a/hw/arm/virt.c\n+++ b/hw/arm/virt.c\n@@ -3769,6 +3769,16 @@ static int virt_get_physical_address_range(MachineState *ms,\n return requested_ipa_size;\n }\n \n+static bool get_kernel_irqchip_default(const MachineState *ms) {\n+ VirtMachineState *vms = VIRT_MACHINE(ms);\n+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);\n+ if (hvf_allowed) {\n+ return !vmc->hvf_no_kernel_irqchip_default;\n+ } else {\n+ return true;\n+ }\n+}\n+\n static const char *virt_get_default_cpu_type(const MachineState *ms)\n {\n return tcg_enabled() ? ARM_CPU_TYPE_NAME(\"cortex-a15\")\n@@ -3835,6 +3845,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)\n mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;\n mc->kvm_type = virt_kvm_type;\n mc->get_physical_address_range = virt_get_physical_address_range;\n+ mc->get_kernel_irqchip_default = get_kernel_irqchip_default;\n assert(!mc->get_hotplug_handler);\n mc->get_hotplug_handler = virt_machine_get_hotplug_handler;\n hc->pre_plug = virt_machine_device_pre_plug_cb;\n@@ -4079,8 +4090,11 @@ DEFINE_VIRT_MACHINE_AS_LATEST(11, 1)\n \n static void virt_machine_11_0_options(MachineClass *mc)\n {\n+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));\n+\n virt_machine_11_1_options(mc);\n compat_props_add(mc->compat_props, hw_compat_11_0, hw_compat_11_0_len);\n+ vmc->hvf_no_kernel_irqchip_default = true;\n }\n DEFINE_VIRT_MACHINE(11, 0)\n \ndiff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h\nindex fc7950da85..13e135a460 100644\n--- a/include/hw/arm/virt.h\n+++ b/include/hw/arm/virt.h\n@@ -138,6 +138,8 @@ struct VirtMachineClass {\n bool no_tcg_lpa2;\n bool no_ns_el2_virt_timer_irq;\n bool no_nested_smmu;\n+ /* HVF specific: support for kernel-irqchip=on introduced in QEMU 11.1 */\n+ bool hvf_no_kernel_irqchip_default;\n };\n \n struct VirtMachineState {\ndiff --git a/include/hw/core/boards.h b/include/hw/core/boards.h\nindex ca63304c95..29c68931d8 100644\n--- a/include/hw/core/boards.h\n+++ b/include/hw/core/boards.h\n@@ -280,6 +280,7 @@ struct MachineClass {\n int (*kvm_type)(MachineState *machine, const char *arg);\n int (*get_physical_address_range)(MachineState *machine,\n int default_ipa_size, int max_ipa_size);\n+ bool (*get_kernel_irqchip_default) (const MachineState *machine);\n \n BlockInterfaceType block_default_type;\n int units_per_default_bus;\ndiff --git a/include/system/hvf_int.h b/include/system/hvf_int.h\nindex 2621164cb2..ad7d375109 100644\n--- a/include/system/hvf_int.h\n+++ b/include/system/hvf_int.h\n@@ -112,4 +112,5 @@ bool hvf_arch_cpu_realize(CPUState *cpu, Error **errp);\n uint32_t hvf_arch_get_default_ipa_bit_size(void);\n uint32_t hvf_arch_get_max_ipa_bit_size(void);\n \n+extern bool hvf_kernel_irqchip_override;\n #endif\n", "prefixes": [ "v21", "15/15" ] }