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GET /api/1.1/patches/2230401/?format=api
{ "id": 2230401, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230401/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260429-winbond-v6-18-rc1-cont-read-v3-11-0f38b3c229ad@bootlin.com/", "project": { "id": 57, "url": "http://patchwork.ozlabs.org/api/1.1/projects/57/?format=api", "name": "Linux ASPEED SoC development", "link_name": "linux-aspeed", "list_id": "linux-aspeed.lists.ozlabs.org", "list_email": "linux-aspeed@lists.ozlabs.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429-winbond-v6-18-rc1-cont-read-v3-11-0f38b3c229ad@bootlin.com>", "date": "2026-04-29T17:56:48", "name": "[v3,11/11] mtd: spinand: winbond: Add support for continuous reads on W25NxxJW", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "a99ff26270fbbb6f75737f810c42e61d08f5e317", "submitter": { "id": 73368, "url": "http://patchwork.ozlabs.org/api/1.1/people/73368/?format=api", "name": "Miquel Raynal", "email": "miquel.raynal@bootlin.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-aspeed/patch/20260429-winbond-v6-18-rc1-cont-read-v3-11-0f38b3c229ad@bootlin.com/mbox/", "series": [ { "id": 502122, "url": "http://patchwork.ozlabs.org/api/1.1/series/502122/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-aspeed/list/?series=502122", "date": "2026-04-29T17:56:39", "name": "mtd: spinand: Winbond continuous read support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/502122/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230401/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230401/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-aspeed+bounces-3981-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-aspeed@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=Kc0vRRlq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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lists.ozlabs.org;\n dmarc=pass (p=reject dis=none) header.from=bootlin.com;\n dkim=pass (2048-bit key;\n unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256\n header.s=dkim header.b=Kc0vRRlq; dkim-atps=neutral;\n spf=pass (client-ip=185.171.202.116; helo=smtpout-04.galae.net;\n envelope-from=miquel.raynal@bootlin.com;\n receiver=lists.ozlabs.org) smtp.mailfrom=bootlin.com", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=dkim;\n\tt=1777485500; h=from:subject:date:message-id:to:cc:mime-version:content-type:\n\t content-transfer-encoding:in-reply-to:references;\n\tbh=MmcPFcCFT0gegKw7/GAlAOSTHc6JlaEROIWqR2nOl4k=;\n\tb=Kc0vRRlqvfSudEFr1jF1Gd7LJngYIVk/OpJ9Xy8LuG253NtHk6/h4qCUHyLC/uelRVb4cc\n\t4dtdIBzKI2GiH9nxWVLuBkH0XM6+60TUTV3lPbduunRwVmtsS7NZANu7HdJhAtQLgyg/XC\n\tqfAyvlNfSlYsoOKdexYgZ4wm/bWSodcggsYCwEBKkDHvzztBYmluC6xuKPrOLpX9/h7Qic\n\tpT6L6tnkencqHbZvV4EVzLeBhMxFjsgykFNa9YcAAIpXCmpJMwhvoG1NFc/Ior2L3DtbkU\n\t3DKkjUd9tAEKhfs0hEhZ7womvlhnP/h4dMJsvpfuXnYvpxywIGUMsaSX8ch/9Q==", "From": "Miquel Raynal <miquel.raynal@bootlin.com>", "Date": "Wed, 29 Apr 2026 19:56:48 +0200", "Subject": "[PATCH v3 11/11] mtd: spinand: winbond: Add support for continuous\n reads on W25NxxJW", "X-Mailing-List": "linux-aspeed@lists.ozlabs.org", "List-Id": "<linux-aspeed.lists.ozlabs.org>", "List-Help": "<mailto:linux-aspeed+help@lists.ozlabs.org>", "List-Owner": "<mailto:linux-aspeed+owner@lists.ozlabs.org>", "List-Post": "<mailto:linux-aspeed@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linux-aspeed/>,\n <https://lists.ozlabs.org/pipermail/linux-aspeed/>", "List-Subscribe": "<mailto:linux-aspeed+subscribe@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-digest@lists.ozlabs.org>,\n <mailto:linux-aspeed+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linux-aspeed+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260429-winbond-v6-18-rc1-cont-read-v3-11-0f38b3c229ad@bootlin.com>", "References": "\n <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>", "In-Reply-To": "\n <20260429-winbond-v6-18-rc1-cont-read-v3-0-0f38b3c229ad@bootlin.com>", "To": "Mark Brown <broonie@kernel.org>, Richard Weinberger <richard@nod.at>,\n Vignesh Raghavendra <vigneshr@ti.com>, Michael Walle <mwalle@kernel.org>,\n Miquel Raynal <miquel.raynal@bootlin.com>,\n Takahiro Kuwano <takahiro.kuwano@infineon.com>,\n Lorenzo Bianconi <lorenzo@kernel.org>, Ray Liu <ray.liu@airoha.com>,\n Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>, =?utf-8?q?C=C3=A9dric_Le_Goa?=\n\t=?utf-8?q?ter?= <clg@kaod.org>, Joel Stanley <joel@jms.id.au>,\n Andrew Jeffery <andrew@codeconstruct.com.au>,\n Avi Fishman <avifishman70@gmail.com>, Tomer Maimon <tmaimon77@gmail.com>,\n Tali Perry <tali.perry1@gmail.com>, Patrick Venture <venture@google.com>,\n Nancy Yuen <yuenn@google.com>, Benjamin Fair <benjaminfair@google.com>,\n Maxime Coquelin <mcoquelin.stm32@gmail.com>,\n Alexandre Torgue <alexandre.torgue@foss.st.com>, =?utf-8?q?Jonathan_Neusch?=\n\t=?utf-8?q?=C3=A4fer?= <j.neuschaefer@gmx.net>", "Cc": "Pratyush Yadav <pratyush@kernel.org>,\n Thomas Petazzoni <thomas.petazzoni@bootlin.com>,\n Steam Lin <STLin2@winbond.com>, Santhosh Kumar K <s-k6@ti.com>,\n linux-spi@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-mtd@lists.infradead.org, linux-arm-kernel@lists.infradead.org,\n linux-aspeed@lists.ozlabs.org, openbmc@lists.ozlabs.org,\n linux-stm32@st-md-mailman.stormreply.com", "X-Mailer": "b4 0.14.3", "X-Last-TLS-Session-Version": "TLSv1.3", "X-Spam-Status": "No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,\n\tDKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS autolearn=disabled\n\tversion=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "As for the W35NxxJW family, add support for W25N{01,02}JW continuous\nread support. Similar operations require to be done, such as setting a\nspecific bit in a configuration register, and providing a set of read\nvariants without the address cycles.\n\nAs read from cache variants are badly supported by SPI memory\ncontrollers, we create a new set of read from cache templates with a\nfake address cycle and just enough dummy cycles. There are two\nunsupported configurations (which would require 4.5 dummy bytes), so we\njust do not provide them.\n\nThe same extra value in the ECC is possible as with the W35NxxJW family,\nso we reference the same helper to retrieve the ECC status.\n\nSigned-off-by: Miquel Raynal <miquel.raynal@bootlin.com>\n---\nAll variants have been validated on a Nuvoton MA35D1 platform.\n---\n drivers/mtd/nand/spi/winbond.c | 108 +++++++++++++++++++++++++++++++++++++----\n 1 file changed, 98 insertions(+), 10 deletions(-)", "diff": "diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c\nindex ffbcd25b0366..578f702528ee 100644\n--- a/drivers/mtd/nand/spi/winbond.c\n+++ b/drivers/mtd/nand/spi/winbond.c\n@@ -46,6 +46,62 @@\n \t\t SPI_MEM_OP_DATA_IN(len, buf, 1),\t\t\t\\\n \t\t SPI_MEM_OP_MAX_FREQ(freq))\n \n+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_1D_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0x0d, 1),\t\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_ADDR(2, 0, 1),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DUMMY(ndummy, 1),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DATA_IN(len, buf, 1),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0x3b, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_ADDR(1, 0, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_DUMMY(ndummy - 1, 1),\t\t\t\\\n+\t\t SPI_MEM_OP_DATA_IN(len, buf, 2),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0xbb, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_ADDR(1, 0, 2),\t\t\t\t\\\n+\t\t SPI_MEM_OP_DUMMY(ndummy - 1, 2),\t\t\t\\\n+\t\t SPI_MEM_OP_DATA_IN(len, buf, 2),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0xbd, 1),\t\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_ADDR(1, 0, 2),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 2),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DATA_IN(len, buf, 2),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0x6b, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_ADDR(1, 0, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_DUMMY(ndummy - 1, 1),\t\t\t\\\n+\t\t SPI_MEM_OP_DATA_IN(len, buf, 4),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0x6d, 1),\t\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_ADDR(1, 0, 1),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 1),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DATA_IN(len, buf, 4),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0xeb, 1),\t\t\t\t\\\n+\t\t SPI_MEM_OP_ADDR(1, 0, 4),\t\t\t\t\\\n+\t\t SPI_MEM_OP_DUMMY(ndummy - 1, 4),\t\t\t\\\n+\t\t SPI_MEM_OP_DATA_IN(len, buf, 4),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n+#define WINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(ndummy, buf, len, freq) \\\n+\tSPI_MEM_OP(SPI_MEM_OP_CMD(0xed, 1),\t\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_ADDR(1, 0, 4),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DUMMY(ndummy - 1, 4),\t\t\t\\\n+\t\t SPI_MEM_DTR_OP_DATA_IN(len, buf, 4),\t\t\t\\\n+\t\t SPI_MEM_OP_MAX_FREQ(freq))\n+\n #define WINBOND_CONT_READ_FROM_CACHE_1S_1S_8S_OP(ndummy, buf, len, freq) \\\n \tSPI_MEM_OP(SPI_MEM_OP_CMD(0x8b, 1),\t\t\t\t\\\n \t\t SPI_MEM_OP_ADDR(1, 0, 1),\t\t\t\t\\\n@@ -133,6 +189,20 @@ static SPINAND_OP_VARIANTS(read_cache_dual_quad_dtr_variants,\n \t\tSPINAND_PAGE_READ_FROM_CACHE_FAST_1S_1S_1S_OP(0, 1, NULL, 0, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_1S_1S_1S_OP(0, 1, NULL, 0, 54 * HZ_PER_MHZ));\n \n+static SPINAND_OP_VARIANTS(cont_read_cache_dual_quad_dtr_variants,\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_4D_4D_OP(11, NULL, 0, 80 * HZ_PER_MHZ),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_1D_4D_OP(5, NULL, 0, 80 * HZ_PER_MHZ),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(7, NULL, 0, 0),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_4S_4S_OP(6, NULL, 0, 104 * HZ_PER_MHZ),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_1S_4S_OP(4, NULL, 0, 0),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_2D_2D_OP(6, NULL, 0, 80 * HZ_PER_MHZ),\n+\t\t/* The 1S_1D_2D variant would require 4.5 dummy bytes, this is not possible */\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(5, NULL, 0, 0),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_2S_2S_OP(4, NULL, 0, 104 * HZ_PER_MHZ),\n+\t\tWINBOND_CONT_READ_FROM_CACHE_1S_1S_2S_OP(4, NULL, 0, 0),\n+\t\t/* The 1S_1D_1D variant would require 4.5 dummy bytes, this is not possible */\n+\t\tWINBOND_CONT_READ_FROM_CACHE_FAST_1S_1S_1S_OP(4, NULL, 0, 0));\n+\n static SPINAND_OP_VARIANTS(read_cache_variants,\n \t\tSPINAND_PAGE_READ_FROM_CACHE_1S_4S_4S_OP(0, 2, NULL, 0, 0),\n \t\tSPINAND_PAGE_READ_FROM_CACHE_1S_1S_4S_OP(0, 1, NULL, 0, 0),\n@@ -445,11 +515,25 @@ static int w25n0xjw_hs_cfg(struct spinand_device *spinand,\n \tif (iface != SSDR)\n \t\treturn -EOPNOTSUPP;\n \n+\t/*\n+\t * At this stage, we do not yet know the continuous read template, nor\n+\t * if there is going to be one. Let's assume the continuous read\n+\t * template will be selected with the same heuristics as the buffered\n+\t * read variant, as there cannot be a HS configuration mismatch between\n+\t * them.\n+\t */\n \top = spinand->op_templates->read_cache;\n \n \treturn w25n0xjw_set_sr4_hs(spinand, w25n0xjw_op_needs_hs(op));\n }\n \n+static int w25n0xjw_set_cont_read(struct spinand_device *spinand, bool enable)\n+{\n+\tu8 mask = enable ? 0 : WINBOND_CFG_BUF_READ;\n+\n+\treturn spinand_upd_cfg(spinand, WINBOND_CFG_BUF_READ, mask);\n+}\n+\n static int w35n0xjw_write_vcr(struct spinand_device *spinand, u8 reg, u8 val)\n {\n \tstruct spi_mem_op op = SPINAND_OP(spinand, winbond_write_vcr,\n@@ -580,12 +664,14 @@ static const struct spinand_info winbond_spinand_table[] = {\n \t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbc, 0x21),\n \t\t NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),\n \t\t NAND_ECCREQ(1, 512),\n-\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,\n-\t\t\t\t\t &write_cache_variants,\n-\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,\n+\t\t\t\t\t\t\t&write_cache_variants,\n+\t\t\t\t\t\t\t&update_cache_variants,\n+\t\t\t\t\t\t\t&cont_read_cache_dual_quad_dtr_variants),\n \t\t SPINAND_HAS_QE_BIT,\n-\t\t SPINAND_ECCINFO(&w25n01jw_ooblayout, NULL),\n-\t\t SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),\n+\t\t SPINAND_ECCINFO(&w25n01jw_ooblayout, w25w35nxxjw_ecc_get_status),\n+\t\t SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),\n+\t\t SPINAND_CONT_READ(w25n0xjw_set_cont_read)),\n \tSPINAND_INFO(\"W25N01KV\", /* 3.3V */\n \t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21),\n \t\t NAND_MEMORG(1, 2048, 96, 64, 1024, 20, 1, 1, 1),\n@@ -624,12 +710,14 @@ static const struct spinand_info winbond_spinand_table[] = {\n \t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xbf, 0x22),\n \t\t NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 2, 1),\n \t\t NAND_ECCREQ(1, 512),\n-\t\t SPINAND_INFO_OP_VARIANTS(&read_cache_dual_quad_dtr_variants,\n-\t\t\t\t\t &write_cache_variants,\n-\t\t\t\t\t &update_cache_variants),\n+\t\t SPINAND_INFO_OP_VARIANTS_WITH_CONT(&read_cache_dual_quad_dtr_variants,\n+\t\t\t\t\t\t\t&write_cache_variants,\n+\t\t\t\t\t\t\t&update_cache_variants,\n+\t\t\t\t\t\t\t&cont_read_cache_dual_quad_dtr_variants),\n \t\t SPINAND_HAS_QE_BIT,\n-\t\t SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL),\n-\t\t SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg)),\n+\t\t SPINAND_ECCINFO(&w25m02gv_ooblayout, w25w35nxxjw_ecc_get_status),\n+\t\t SPINAND_CONFIGURE_CHIP(w25n0xjw_hs_cfg),\n+\t\t SPINAND_CONT_READ(w25n0xjw_set_cont_read)),\n \tSPINAND_INFO(\"W25N02KV\", /* 3.3V */\n \t\t SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22),\n \t\t NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),\n", "prefixes": [ "v3", "11/11" ] }