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GET /api/1.1/patches/2230219/?format=api
{ "id": 2230219, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230219/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429-shikra-pinctrl-v1-1-1b4bb2b3a8d6@oss.qualcomm.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.1/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429-shikra-pinctrl-v1-1-1b4bb2b3a8d6@oss.qualcomm.com>", "date": "2026-04-29T13:11:56", "name": "[1/2] dt-bindings: pinctrl: qcom: Document Shikra Top Level Mode Multiplexer", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3713dcc1bdcf1438bb73d4dae34909f60c73d01e", "submitter": { "id": 93282, "url": "http://patchwork.ozlabs.org/api/1.1/people/93282/?format=api", "name": "Komal Bajaj", "email": "komal.bajaj@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260429-shikra-pinctrl-v1-1-1b4bb2b3a8d6@oss.qualcomm.com/mbox/", "series": [ { "id": 502057, "url": "http://patchwork.ozlabs.org/api/1.1/series/502057/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502057", "date": "2026-04-29T13:11:57", "name": "pinctrl: qcom: Add support for Qualcomm Shikra SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502057/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230219/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230219/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-gpio+bounces-35794-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=XnbW4eR9;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=SoOp0auG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260429-shikra-pinctrl-v1-1-1b4bb2b3a8d6@oss.qualcomm.com>", "References": "<20260429-shikra-pinctrl-v1-0-1b4bb2b3a8d6@oss.qualcomm.com>", "In-Reply-To": "<20260429-shikra-pinctrl-v1-0-1b4bb2b3a8d6@oss.qualcomm.com>", "To": "Bjorn Andersson <andersson@kernel.org>, Linus Walleij <linusw@kernel.org>,\n Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n Richard Cochran <richardcochran@gmail.com>", "Cc": "linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n netdev@vger.kernel.org, Komal Bajaj <komal.bajaj@oss.qualcomm.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777468321; l=4446;\n i=komal.bajaj@oss.qualcomm.com; s=20250710; h=from:subject:message-id;\n bh=5FeJwkn0w0hoFaU+H21wk2uMRmNaRakanqYwZuX9Z0c=;\n b=5jYkUxcG5qPe/fWWUGltzwDAgJLZr6glLKzLyJP+03Re8Cc4tJBsVZ9G9sEMEt6u+w9eaRTWw\n V+XLS/mm+G9AuFu3CCoI/hgR3eMkZjKVQcDn8YkI3I5xRZWPMyf3+Ol", "X-Developer-Key": "i=komal.bajaj@oss.qualcomm.com; a=ed25519;\n pk=wKh8mgDh+ePUZ4IIvpBhQOqf16/KvuQHvSvHK20LXNU=", "X-Proofpoint-GUID": "nyB0iznwLxSUIZbxaUauE5cEFEaHqa0x", "X-Proofpoint-ORIG-GUID": "nyB0iznwLxSUIZbxaUauE5cEFEaHqa0x", "X-Authority-Analysis": "v=2.4 cv=Wak8rUhX c=1 sm=1 tr=0 ts=69f203ac cx=c_pps\n a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22\n a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=bT5XQOCXPleopHcqzpYA:9 a=QEXdDO2ut3YA:10\n a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI5MDEzNCBTYWx0ZWRfX5eST+fxizbLX\n qsDd96F40Dn6ksR3F4wlwpZXgQSBGXP34UI5u6jpShgNuV3vj9NnJRBbtic+OwW8eyvkIbWw5CA\n ifJaZ4HB7EMDJtEcJcdhKJrJTd/9idkpForu4en3qeAcMv/sQy/59A3dELuGSdlbkxqGbCO90bv\n 09hAgzeSG2rX4R2xYA3yICuRGu7+beANiFGwuGMHA48HprhDQgFRStqFD6tt1kzBxcl48mmwG/m\n 53CkbdaQf3QaJ4FdKUprtKTUNU2u4eZwLWD1T0KyhbRPUGjV/B7qlVKZN4jtT0uxhHD0QHhJZeV\n th4gTilnyWR/uH1c8lB7FHHFCGuTsOHD0Mz5ONvSXoTd7K+liqj+QfSWgfocproNojwVbSc3Ika\n XWDEaHX7Oy7jHMX69Wyt93+btUrZ0LmsEmJ/mxwRCUU8U8iE4KmRCWKAlUjZzB5lUchCTcrgOU5\n 90jGDLgsGjCatMT/hKg==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1011\n bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290134" }, "content": "Add a DeviceTree binding to describe the TLMM block on Qualcomm's\nShikra SoC.\n\nSigned-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>\n---\n .../bindings/pinctrl/qcom,shikra-tlmm.yaml | 123 +++++++++++++++++++++\n 1 file changed, 123 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml\nnew file mode 100644\nindex 000000000000..896fbe461ef9\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml\n@@ -0,0 +1,123 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Technologies, Inc. Shikra TLMM block\n+\n+maintainers:\n+ - Komal Bajaj <komal.bajaj@oss.qualcomm.com>\n+\n+description: |\n+ Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC.\n+\n+allOf:\n+ - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,shikra-tlmm\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ gpio-reserved-ranges:\n+ minItems: 1\n+ maxItems: 83\n+\n+ gpio-line-names:\n+ maxItems: 165\n+\n+patternProperties:\n+ \"-state$\":\n+ oneOf:\n+ - $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ - patternProperties:\n+ \"-pins$\":\n+ $ref: \"#/$defs/qcom-shikra-tlmm-state\"\n+ additionalProperties: false\n+\n+$defs:\n+ qcom-shikra-tlmm-state:\n+ type: object\n+ description:\n+ Pinctrl node's client devices use subnodes for desired pin configuration.\n+ Client device subnodes use below standard properties.\n+ $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pins:\n+ description:\n+ List of gpio pins affected by the properties specified in this\n+ subnode.\n+ items:\n+ oneOf:\n+ - pattern: \"^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$\"\n+ - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,\n+ sdc2_clk, sdc2_cmd, sdc2_data ]\n+ minItems: 1\n+ maxItems: 36\n+\n+ function:\n+ description:\n+ Specify the alternative function to be configured for the specified\n+ pins.\n+\n+ enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc,\n+ atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0,\n+ cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib,\n+ dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg,\n+ emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux,\n+ emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1,\n+ i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0,\n+ mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte,\n+ nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n,\n+ phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0,\n+ qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01,\n+ qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6,\n+ qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01,\n+ qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig,\n+ ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async,\n+ tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps,\n+ vfr, vsense_trigger_mirnat, wlan ]\n+\n+ required:\n+ - pins\n+\n+required:\n+ - compatible\n+ - reg\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ tlmm: pinctrl@500000 {\n+ compatible = \"qcom,shikra-tlmm\";\n+ reg = <0x00500000 0x800000>;\n+\n+ interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+\n+ gpio-ranges = <&tlmm 0 0 166>;\n+\n+ qup-uart0-default-state {\n+ pins = \"gpio0\", \"gpio1\";\n+ function = \"qup0_se1\";\n+ drive-strength = <2>;\n+ bias-disable;\n+ };\n+ };\n+...\n", "prefixes": [ "1/2" ] }