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GET /api/1.1/patches/2230169/?format=api
{ "id": 2230169, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230169/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260429121816.1026326-6-mwalle@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260429121816.1026326-6-mwalle@kernel.org>", "date": "2026-04-29T12:17:19", "name": "[05/10] boards/nxp: remove board_eth_init()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "efbeae818c22bc5514f81b1e632354ebe5a69d78", "submitter": { "id": 86646, "url": "http://patchwork.ozlabs.org/api/1.1/people/86646/?format=api", "name": "Michael Walle", "email": "mwalle@kernel.org" }, "delegate": { "id": 55230, "url": "http://patchwork.ozlabs.org/api/1.1/users/55230/?format=api", "username": "freenix", "first_name": "Peng", "last_name": "Fan", "email": "van.freenix@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260429121816.1026326-6-mwalle@kernel.org/mbox/", "series": [ { "id": 502047, "url": "http://patchwork.ozlabs.org/api/1.1/series/502047/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=502047", "date": "2026-04-29T12:17:14", "name": "Generic powerpc fixes and NXP board cleanup", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502047/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230169/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230169/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=iYsEerPq;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"iYsEerPq\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=mwalle@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g5GZN6x9qz1yHZ\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 22:19:24 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 0BBF584870;\n\tWed, 29 Apr 2026 14:19:00 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 254368486B; Wed, 29 Apr 2026 14:18:58 +0200 (CEST)", "from sea.source.kernel.org (sea.source.kernel.org\n [IPv6:2600:3c0a:e001:78e:0:1991:8:25])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 47BE08486D\n for <u-boot@lists.denx.de>; Wed, 29 Apr 2026 14:18:53 +0200 (CEST)", "from smtp.kernel.org (transwarp.subspace.kernel.org [100.75.92.58])\n by sea.source.kernel.org (Postfix) with ESMTP id CF3C9444E7;\n Wed, 29 Apr 2026 12:18:51 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id A2EEFC2BCC6;\n Wed, 29 Apr 2026 12:18:46 +0000 (UTC)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1777465131;\n bh=ocCCATXNoMHch4k4s0BpCEw0yeIIgSbb7v5+yv7uJ58=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=iYsEerPqc15aRHwLzOeyMNNEwNHy6dW8t2SV3//K6TVFsznj0+UJYJm+ZZgPzlgy0\n oBZoeEmhcgDqwcmkfNFwQK634cNfUjSOgVF9VommByHgb7bbjbkieT0TGYjJMj3AJJ\n a9eNBZcqywKlE5I2X0eCSgXmdlx3ANwrvnHSEcXPXxmGLemRskIX9DvneZJHC0B6n+\n xMQKZGVzKfMOzAdLh2HWzZ4KMhfeYXSCX8V/QT7SIjZqo0hFEQZ9xChq803Uhx0avP\n UqPpPsDF+dl7eXxqNinJZsRdTf37cpUGUsSIITG1nfOl2T1AHewxdBteVgUMgYYF8/\n sQCxd82iDP6WQ==", "From": "Michael Walle <mwalle@kernel.org>", "To": "=?utf-8?q?Marek_Beh=C3=BAn?= <kabel@kernel.org>,\n Tom Rini <trini@konsulko.com>, Pramod Kumar <pramod.kumar_1@nxp.com>,\n Vladimir Oltean <olteanv@gmail.com>, Alison Wang <alison.wang@nxp.com>,\n Tang Yuantian <andy.tang@nxp.com>, Mingkai Hu <mingkai.hu@nxp.com>,\n Priyanka Jain <priyanka.jain@nxp.com>, Wasim Khan <wasim.khan@nxp.com>,\n Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com>,\n TsiChung Liew <Tsi-Chung.Liew@nxp.com>, Stefano Babic <sbabic@nabladev.com>,\n Fabio Estevam <festevam@gmail.com>,\n \"NXP i . MX U-Boot Team\" <uboot-imx@nxp.com>, Peng Fan <peng.fan@nxp.com>,\n Shengzhou Liu <Shengzhou.Liu@nxp.com>", "Cc": "Tomas Alvarez Vanoli <tomas.alvarez-vanoli@hitachienergy.com>,\n Jerome Forissier <jerome.forissier@arm.com>, u-boot@lists.denx.de,\n Michael Walle <mwalle@kernel.org>", "Subject": "[PATCH 05/10] boards/nxp: remove board_eth_init()", "Date": "Wed, 29 Apr 2026 14:17:19 +0200", "Message-ID": "<20260429121816.1026326-6-mwalle@kernel.org>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260429121816.1026326-1-mwalle@kernel.org>", "References": "<20260429121816.1026326-1-mwalle@kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "board_eth_init() is dead code since commit e524f3a449f5 (\"net: Remove\neth_legacy.c\"). Remove it.\n\nI'm not sure, all the shenanigans are covered by the new DM-version. The\nMDIO mux and iomux controls probably are. The fman configuration\nprobably isn't. OTOH, nobody cared for years and the called\nfm_info_set_phy_address() was also removed years ago.\n\nThis also removes fdt_fixup_board_enet() for the ls1043a and ls1046a\nbecause it relies on the local variable \"mdio_mux\" being initialized by\nthe board_eth_init().\n\nSigned-off-by: Michael Walle <mwalle@kernel.org>\n---\n board/nxp/ls1012afrdm/eth.c | 10 -\n board/nxp/ls1012ardb/eth.c | 12 -\n board/nxp/ls1021atsn/ls1021atsn.c | 5 -\n board/nxp/ls1021atwr/ls1021atwr.c | 5 -\n board/nxp/ls1028a/ls1028a.c | 5 -\n board/nxp/ls1043aqds/eth.c | 391 ------------------\n board/nxp/ls1043ardb/Makefile | 1 -\n board/nxp/ls1043ardb/eth.c | 77 ----\n board/nxp/ls1046afrwy/eth.c | 57 ---\n board/nxp/ls1046aqds/eth.c | 339 ----------------\n board/nxp/ls1046ardb/eth.c | 71 ----\n board/nxp/ls2080ardb/eth_ls2080rdb.c | 19 -\n board/nxp/lx2160a/eth_lx2160aqds.c | 18 -\n board/nxp/lx2160a/eth_lx2160ardb.c | 17 -\n board/nxp/lx2160a/eth_lx2162aqds.c | 18 -\n board/nxp/m5253demo/m5253demo.c | 7 -\n board/nxp/mx6sxsabreauto/mx6sxsabreauto.c | 52 ---\n board/nxp/mx6sxsabresd/mx6sxsabresd.c | 78 ----\n board/nxp/p2041rdb/Makefile | 1 -\n board/nxp/p2041rdb/eth.c | 140 -------\n board/nxp/t102xrdb/eth_t102xrdb.c | 103 -----\n board/nxp/t104xrdb/Makefile | 1 -\n board/nxp/t104xrdb/eth.c | 91 -----\n board/nxp/t208xqds/eth_t208xqds.c | 460 ----------------------\n board/nxp/t4rdb/eth.c | 115 ------\n 25 files changed, 2093 deletions(-)\n delete mode 100644 board/nxp/ls1043ardb/eth.c\n delete mode 100644 board/nxp/p2041rdb/eth.c\n delete mode 100644 board/nxp/t104xrdb/eth.c", "diff": "diff --git a/board/nxp/ls1012afrdm/eth.c b/board/nxp/ls1012afrdm/eth.c\nindex c431e5e611b..8761ec7845e 100644\n--- a/board/nxp/ls1012afrdm/eth.c\n+++ b/board/nxp/ls1012afrdm/eth.c\n@@ -7,16 +7,6 @@\n #include <dm.h>\n #include <net.h>\n #include <asm/io.h>\n-#include <netdev.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-#include <asm/types.h>\n-#include <fsl_dtsec.h>\n-#include <asm/arch/soc.h>\n-#include <asm/arch-fsl-layerscape/config.h>\n-#include <asm/arch-fsl-layerscape/immap_lsch2.h>\n-#include <asm/arch/fsl_serdes.h>\n #include <linux/delay.h>\n #include <net/pfe_eth/pfe_eth.h>\n #include <dm/platform_data/pfe_dm_eth.h>\ndiff --git a/board/nxp/ls1012ardb/eth.c b/board/nxp/ls1012ardb/eth.c\nindex 71cb2988a56..6a6f4608fd1 100644\n--- a/board/nxp/ls1012ardb/eth.c\n+++ b/board/nxp/ls1012ardb/eth.c\n@@ -6,18 +6,6 @@\n \n #include <config.h>\n #include <dm.h>\n-#include <net.h>\n-#include <asm/io.h>\n-#include <netdev.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-#include <asm/types.h>\n-#include <fsl_dtsec.h>\n-#include <asm/arch/soc.h>\n-#include <asm/arch-fsl-layerscape/config.h>\n-#include <asm/arch-fsl-layerscape/immap_lsch2.h>\n-#include <asm/arch/fsl_serdes.h>\n #include <linux/delay.h>\n #include <net/pfe_eth/pfe_eth.h>\n #include <dm/platform_data/pfe_dm_eth.h>\ndiff --git a/board/nxp/ls1021atsn/ls1021atsn.c b/board/nxp/ls1021atsn/ls1021atsn.c\nindex c92430c0896..277506fdbb8 100644\n--- a/board/nxp/ls1021atsn/ls1021atsn.c\n+++ b/board/nxp/ls1021atsn/ls1021atsn.c\n@@ -123,11 +123,6 @@ int dram_init(void)\n \treturn 0;\n }\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-\treturn pci_eth_init(bis);\n-}\n-\n int board_early_init_f(void)\n {\n \tstruct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;\ndiff --git a/board/nxp/ls1021atwr/ls1021atwr.c b/board/nxp/ls1021atwr/ls1021atwr.c\nindex 0758e5eae25..135497f7c5d 100644\n--- a/board/nxp/ls1021atwr/ls1021atwr.c\n+++ b/board/nxp/ls1021atwr/ls1021atwr.c\n@@ -239,11 +239,6 @@ int dram_init(void)\n \treturn 0;\n }\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-\treturn pci_eth_init(bis);\n-}\n-\n #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)\n static void convert_serdes_mux(int type, int need_reset)\n {\ndiff --git a/board/nxp/ls1028a/ls1028a.c b/board/nxp/ls1028a/ls1028a.c\nindex db94d9c1fa8..007125358bd 100644\n--- a/board/nxp/ls1028a/ls1028a.c\n+++ b/board/nxp/ls1028a/ls1028a.c\n@@ -103,11 +103,6 @@ int board_init(void)\n \treturn 0;\n }\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-\treturn pci_eth_init(bis);\n-}\n-\n #ifdef CONFIG_MISC_INIT_R\n int misc_init_r(void)\n {\ndiff --git a/board/nxp/ls1043aqds/eth.c b/board/nxp/ls1043aqds/eth.c\nindex 5680fd2d377..d62cf74732c 100644\n--- a/board/nxp/ls1043aqds/eth.c\n+++ b/board/nxp/ls1043aqds/eth.c\n@@ -4,399 +4,8 @@\n * Copyright 2019 NXP\n */\n \n-#include <config.h>\n-#include <log.h>\n-#include <net.h>\n-#include <asm/io.h>\n-#include <netdev.h>\n #include <fdt_support.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <fsl_dtsec.h>\n-#include <linux/libfdt.h>\n-#include <malloc.h>\n-#include <asm/arch/fsl_serdes.h>\n-\n-#include \"../common/qixis.h\"\n-#include \"../common/fman.h\"\n-#include \"ls1043aqds_qixis.h\"\n-\n-#define EMI_NONE\t0xFF\n-#define EMI1_RGMII1\t0\n-#define EMI1_RGMII2\t1\n-#define EMI1_SLOT1\t2\n-#define EMI1_SLOT2\t3\n-#define EMI1_SLOT3\t4\n-#define EMI1_SLOT4\t5\n-#define EMI2\t\t6\n-\n-static const char * const mdio_names[] = {\n-\t\"LS1043AQDS_MDIO_RGMII1\",\n-\t\"LS1043AQDS_MDIO_RGMII2\",\n-\t\"LS1043AQDS_MDIO_SLOT1\",\n-\t\"LS1043AQDS_MDIO_SLOT2\",\n-\t\"LS1043AQDS_MDIO_SLOT3\",\n-\t\"LS1043AQDS_MDIO_SLOT4\",\n-\t\"NULL\",\n-};\n-\n-/* Map SerDes1 4 lanes to default slot, will be initialized dynamically */\n-#ifdef CONFIG_FMAN_ENET\n-static int mdio_mux[NUM_FM_PORTS];\n-\n-static u8 lane_to_slot[] = {1, 2, 3, 4};\n-#endif\n-\n-static const char *ls1043aqds_mdio_name_for_muxval(u8 muxval)\n-{\n-\treturn mdio_names[muxval];\n-}\n-\n-struct mii_dev *mii_dev_for_muxval(u8 muxval)\n-{\n-\tstruct mii_dev *bus;\n-\tconst char *name;\n-\n-\tif (muxval > EMI2)\n-\t\treturn NULL;\n-\n-\tname = ls1043aqds_mdio_name_for_muxval(muxval);\n-\n-\tif (!name) {\n-\t\tprintf(\"No bus for muxval %x\\n\", muxval);\n-\t\treturn NULL;\n-\t}\n-\n-\tbus = miiphy_get_dev_by_name(name);\n-\n-\tif (!bus) {\n-\t\tprintf(\"No bus by name %s\\n\", name);\n-\t\treturn NULL;\n-\t}\n-\n-\treturn bus;\n-}\n-\n-#ifdef CONFIG_FMAN_ENET\n-struct ls1043aqds_mdio {\n-\tu8 muxval;\n-\tstruct mii_dev *realbus;\n-};\n-\n-static void ls1043aqds_mux_mdio(u8 muxval)\n-{\n-\tu8 brdcfg4;\n-\n-\tif (muxval < 7) {\n-\t\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n-\t\tbrdcfg4 &= ~BRDCFG4_EMISEL_MASK;\n-\t\tbrdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);\n-\t\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n-\t}\n-}\n-\n-static int ls1043aqds_mdio_read(struct mii_dev *bus, int addr, int devad,\n-\t\t\t int regnum)\n-{\n-\tstruct ls1043aqds_mdio *priv = bus->priv;\n-\n-\tls1043aqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->read(priv->realbus, addr, devad, regnum);\n-}\n-\n-static int ls1043aqds_mdio_write(struct mii_dev *bus, int addr, int devad,\n-\t\t\t int regnum, u16 value)\n-{\n-\tstruct ls1043aqds_mdio *priv = bus->priv;\n-\n-\tls1043aqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->write(priv->realbus, addr, devad,\n-\t\t\t\t regnum, value);\n-}\n-\n-static int ls1043aqds_mdio_reset(struct mii_dev *bus)\n-{\n-\tstruct ls1043aqds_mdio *priv = bus->priv;\n-\n-\treturn priv->realbus->reset(priv->realbus);\n-}\n-\n-static int ls1043aqds_mdio_init(char *realbusname, u8 muxval)\n-{\n-\tstruct ls1043aqds_mdio *pmdio;\n-\tstruct mii_dev *bus = mdio_alloc();\n-\n-\tif (!bus) {\n-\t\tprintf(\"Failed to allocate ls1043aqds MDIO bus\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio = malloc(sizeof(*pmdio));\n-\tif (!pmdio) {\n-\t\tprintf(\"Failed to allocate ls1043aqds private data\\n\");\n-\t\tfree(bus);\n-\t\treturn -1;\n-\t}\n-\n-\tbus->read = ls1043aqds_mdio_read;\n-\tbus->write = ls1043aqds_mdio_write;\n-\tbus->reset = ls1043aqds_mdio_reset;\n-\tstrcpy(bus->name, ls1043aqds_mdio_name_for_muxval(muxval));\n-\n-\tpmdio->realbus = miiphy_get_dev_by_name(realbusname);\n-\n-\tif (!pmdio->realbus) {\n-\t\tprintf(\"No bus with name %s\\n\", realbusname);\n-\t\tfree(bus);\n-\t\tfree(pmdio);\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio->muxval = muxval;\n-\tbus->priv = pmdio;\n-\treturn mdio_register(bus);\n-}\n \n void fdt_fixup_board_enet(void *fdt)\n {\n-\tint i;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\tu32 srds_s1;\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tfor (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\tcase PHY_INTERFACE_MODE_QSGMII:\n-\t\t\tswitch (mdio_mux[i]) {\n-\t\t\tcase EMI1_SLOT1:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot1\");\n-\t\t\t\tbreak;\n-\t\t\tcase EMI1_SLOT2:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot2\");\n-\t\t\t\tbreak;\n-\t\t\tcase EMI1_SLOT3:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot3\");\n-\t\t\t\tbreak;\n-\t\t\tcase EMI1_SLOT4:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot4\");\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_XGMII:\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-\tint i, idx, lane, slot, interface;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\tu32 srds_s1;\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\t/* Initialize the mdio_mux array so we can recognize empty elements */\n-\tfor (i = 0; i < NUM_FM_PORTS; i++)\n-\t\tmdio_mux[i] = EMI_NONE;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/* Register the muxing front-ends to the MDIO buses */\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);\n-\tls1043aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);\n-\tls1043aqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);\n-\n-\t/* Set the two on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x2555:\n-\t\t/* 2.5G SGMII on lane A, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, 9);\n-\t\tbreak;\n-\tcase 0x4555:\n-\tcase 0x4558:\n-\t\t/* QSGMII on lane A, MAC 1/2/5/6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1,\n-\t\t\t\t\tQSGMII_CARD_PORT1_PHY_ADDR_S1);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2,\n-\t\t\t\t\tQSGMII_CARD_PORT2_PHY_ADDR_S1);\n-\t\tfm_info_set_phy_address(FM1_DTSEC5,\n-\t\t\t\t\tQSGMII_CARD_PORT3_PHY_ADDR_S1);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6,\n-\t\t\t\t\tQSGMII_CARD_PORT4_PHY_ADDR_S1);\n-\t\tbreak;\n-\tcase 0x1355:\n-\t\t/* SGMII on lane B, MAC 2*/\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x2355:\n-\t\t/* 2.5G SGMII on lane A, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, 9);\n-\t\t/* SGMII on lane B, MAC 2*/\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x3335:\n-\t\t/* SGMII on lane C, MAC 5 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT1_PHY_ADDR);\n-\tcase 0x3355:\n-\tcase 0x3358:\n-\t\t/* SGMII on lane B, MAC 2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);\n-\tcase 0x3555:\n-\tcase 0x3558:\n-\t\t/* SGMII on lane A, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x1455:\n-\t\t/* QSGMII on lane B, MAC 1/2/5/6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1,\n-\t\t\t\t\tQSGMII_CARD_PORT1_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2,\n-\t\t\t\t\tQSGMII_CARD_PORT2_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC5,\n-\t\t\t\t\tQSGMII_CARD_PORT3_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6,\n-\t\t\t\t\tQSGMII_CARD_PORT4_PHY_ADDR_S2);\n-\t\tbreak;\n-\tcase 0x2455:\n-\t\t/* 2.5G SGMII on lane A, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, 9);\n-\t\t/* QSGMII on lane B, MAC 1/2/5/6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1,\n-\t\t\t\t\tQSGMII_CARD_PORT1_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2,\n-\t\t\t\t\tQSGMII_CARD_PORT2_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC5,\n-\t\t\t\t\tQSGMII_CARD_PORT3_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6,\n-\t\t\t\t\tQSGMII_CARD_PORT4_PHY_ADDR_S2);\n-\t\tbreak;\n-\tcase 0x2255:\n-\t\t/* 2.5G SGMII on lane A, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, 9);\n-\t\t/* 2.5G SGMII on lane B, MAC 2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, 2);\n-\t\tbreak;\n-\tcase 0x3333:\n-\t\t/* SGMII on lane A/B/C/D, MAC 9/2/5/6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9,\n-\t\t\t\t\tSGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2,\n-\t\t\t\t\tSGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC5,\n-\t\t\t\t\tSGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6,\n-\t\t\t\t\tSGMII_CARD_PORT1_PHY_ADDR);\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1043AQDS\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tidx = i - FM1_DTSEC1;\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n-\t\tcase PHY_INTERFACE_MODE_QSGMII:\n-\t\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tSGMII_FM1_DTSEC1 + idx);\n-\t\t\t} else if (interface == PHY_INTERFACE_MODE_2500BASEX) {\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tSGMII_2500_FM1_DTSEC1 + idx);\n-\t\t\t} else {\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tQSGMII_FM1_A);\n-\t\t\t}\n-\n-\t\t\tif (lane < 0)\n-\t\t\t\tbreak;\n-\n-\t\t\tslot = lane_to_slot[lane];\n-\t\t\tdebug(\"FM1@DTSEC%u expects SGMII in slot %u\\n\",\n-\t\t\t idx + 1, slot);\n-\t\t\tif (QIXIS_READ(present2) & (1 << (slot - 1)))\n-\t\t\t\tfm_disable_port(i);\n-\n-\t\t\tswitch (slot) {\n-\t\t\tcase 1:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT1;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 2:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT2;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 3:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT3;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 4:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT4;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\tif (i == FM1_DTSEC3)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII1;\n-\t\t\telse if (i == FM1_DTSEC4)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII2;\n-\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tcpu_eth_init(bis);\n-\n-\treturn pci_eth_init(bis);\n }\n-#endif /* CONFIG_FMAN_ENET */\ndiff --git a/board/nxp/ls1043ardb/Makefile b/board/nxp/ls1043ardb/Makefile\nindex 95745bf3a9c..13e0411c1ba 100644\n--- a/board/nxp/ls1043ardb/Makefile\n+++ b/board/nxp/ls1043ardb/Makefile\n@@ -5,6 +5,5 @@\n obj-y += ddr.o\n obj-y += ls1043ardb.o\n ifndef CONFIG_XPL_BUILD\n-obj-$(CONFIG_NET) += eth.o\n obj-y += cpld.o\n endif\ndiff --git a/board/nxp/ls1043ardb/eth.c b/board/nxp/ls1043ardb/eth.c\ndeleted file mode 100644\nindex cacc49c0584..00000000000\n--- a/board/nxp/ls1043ardb/eth.c\n+++ /dev/null\n@@ -1,77 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2015 Freescale Semiconductor, Inc.\n- */\n-#include <config.h>\n-#include <net.h>\n-#include <asm/io.h>\n-#include <netdev.h>\n-#include <fm_eth.h>\n-#include <fsl_dtsec.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-\n-#include \"../common/fman.h\"\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_FMAN_ENET\n-\tint i;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tstruct mii_dev *dev;\n-\tu32 srds_s1;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/* Set the two on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);\n-\n-\t/* QSGMII on lane B, MAC 1/2/5/6 */\n-\tfm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT1_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC2, QSGMII_PORT2_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT3_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT4_PHY_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x1455:\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1043ARDB\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)\n-\t\tfm_info_set_mdio(i, dev);\n-\n-\t/* 10GBase-R on lane A, MAC 9 */\n-\tfm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);\n-\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\tfm_info_set_mdio(FM1_10GEC1, dev);\n-\n-\tcpu_eth_init(bis);\n-#endif\n-\n-\treturn pci_eth_init(bis);\n-}\ndiff --git a/board/nxp/ls1046afrwy/eth.c b/board/nxp/ls1046afrwy/eth.c\nindex 8efc7f68424..d76841c6ab4 100644\n--- a/board/nxp/ls1046afrwy/eth.c\n+++ b/board/nxp/ls1046afrwy/eth.c\n@@ -4,64 +4,7 @@\n */\n #include <config.h>\n #include <fdt_support.h>\n-#include <net.h>\n #include <asm/io.h>\n-#include <netdev.h>\n-#include <fm_eth.h>\n-#include <fsl_dtsec.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-\n-#include \"../common/fman.h\"\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_FMAN_ENET\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct mii_dev *dev;\n-\tu32 srds_s1;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\t/* QSGMII on lane B, MAC 6/5/10/1 */\n-\tfm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x3040:\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1046AFRWY\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\tfm_info_set_mdio(FM1_DTSEC6, dev);\n-\tfm_info_set_mdio(FM1_DTSEC5, dev);\n-\tfm_info_set_mdio(FM1_DTSEC10, dev);\n-\tfm_info_set_mdio(FM1_DTSEC1, dev);\n-\n-\tfm_disable_port(FM1_DTSEC9);\n-\n-\tcpu_eth_init(bis);\n-#endif\n-\n-\treturn pci_eth_init(bis);\n-}\n \n #ifdef CONFIG_FMAN_ENET\n int fdt_update_ethernet_dt(void *blob)\ndiff --git a/board/nxp/ls1046aqds/eth.c b/board/nxp/ls1046aqds/eth.c\nindex 8446f438d3c..24e6c93aece 100644\n--- a/board/nxp/ls1046aqds/eth.c\n+++ b/board/nxp/ls1046aqds/eth.c\n@@ -4,347 +4,8 @@\n * Copyright 2018-2020 NXP\n */\n \n-#include <config.h>\n-#include <log.h>\n-#include <net.h>\n-#include <asm/io.h>\n-#include <netdev.h>\n #include <fdt_support.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <fsl_dtsec.h>\n-#include <malloc.h>\n-#include <asm/arch/fsl_serdes.h>\n-\n-#include \"../common/qixis.h\"\n-#include \"../common/fman.h\"\n-#include \"ls1046aqds_qixis.h\"\n-\n-#define EMI_NONE\t0xFF\n-#define EMI1_RGMII1\t0\n-#define EMI1_RGMII2\t1\n-#define EMI1_SLOT1\t2\n-#define EMI1_SLOT2\t3\n-#define EMI1_SLOT4\t4\n-\n-static const char * const mdio_names[] = {\n-\t\"LS1046AQDS_MDIO_RGMII1\",\n-\t\"LS1046AQDS_MDIO_RGMII2\",\n-\t\"LS1046AQDS_MDIO_SLOT1\",\n-\t\"LS1046AQDS_MDIO_SLOT2\",\n-\t\"LS1046AQDS_MDIO_SLOT4\",\n-\t\"NULL\",\n-};\n-\n-/* Map SerDes 1 & 2 lanes to default slot. */\n-#ifdef CONFIG_FMAN_ENET\n-static int mdio_mux[NUM_FM_PORTS];\n-\n-static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};\n-#endif\n-\n-static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)\n-{\n-\treturn mdio_names[muxval];\n-}\n-\n-struct mii_dev *mii_dev_for_muxval(u8 muxval)\n-{\n-\tstruct mii_dev *bus;\n-\tconst char *name;\n-\n-\tif (muxval > EMI1_SLOT4)\n-\t\treturn NULL;\n-\n-\tname = ls1046aqds_mdio_name_for_muxval(muxval);\n-\n-\tif (!name) {\n-\t\tprintf(\"No bus for muxval %x\\n\", muxval);\n-\t\treturn NULL;\n-\t}\n-\n-\tbus = miiphy_get_dev_by_name(name);\n-\n-\tif (!bus) {\n-\t\tprintf(\"No bus by name %s\\n\", name);\n-\t\treturn NULL;\n-\t}\n-\n-\treturn bus;\n-}\n-\n-#ifdef CONFIG_FMAN_ENET\n-struct ls1046aqds_mdio {\n-\tu8 muxval;\n-\tstruct mii_dev *realbus;\n-};\n-\n-static void ls1046aqds_mux_mdio(u8 muxval)\n-{\n-\tu8 brdcfg4;\n-\n-\tif (muxval < 7) {\n-\t\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n-\t\tbrdcfg4 &= ~BRDCFG4_EMISEL_MASK;\n-\t\tbrdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);\n-\t\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n-\t}\n-}\n-\n-static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,\n-\t\t\t int regnum)\n-{\n-\tstruct ls1046aqds_mdio *priv = bus->priv;\n-\n-\tls1046aqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->read(priv->realbus, addr, devad, regnum);\n-}\n-\n-static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,\n-\t\t\t int regnum, u16 value)\n-{\n-\tstruct ls1046aqds_mdio *priv = bus->priv;\n-\n-\tls1046aqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->write(priv->realbus, addr, devad,\n-\t\t\t\t regnum, value);\n-}\n-\n-static int ls1046aqds_mdio_reset(struct mii_dev *bus)\n-{\n-\tstruct ls1046aqds_mdio *priv = bus->priv;\n-\n-\treturn priv->realbus->reset(priv->realbus);\n-}\n-\n-static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)\n-{\n-\tstruct ls1046aqds_mdio *pmdio;\n-\tstruct mii_dev *bus = mdio_alloc();\n-\n-\tif (!bus) {\n-\t\tprintf(\"Failed to allocate ls1046aqds MDIO bus\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio = malloc(sizeof(*pmdio));\n-\tif (!pmdio) {\n-\t\tprintf(\"Failed to allocate ls1046aqds private data\\n\");\n-\t\tfree(bus);\n-\t\treturn -1;\n-\t}\n-\n-\tbus->read = ls1046aqds_mdio_read;\n-\tbus->write = ls1046aqds_mdio_write;\n-\tbus->reset = ls1046aqds_mdio_reset;\n-\tsprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));\n-\n-\tpmdio->realbus = miiphy_get_dev_by_name(realbusname);\n-\n-\tif (!pmdio->realbus) {\n-\t\tprintf(\"No bus with name %s\\n\", realbusname);\n-\t\tfree(bus);\n-\t\tfree(pmdio);\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio->muxval = muxval;\n-\tbus->priv = pmdio;\n-\treturn mdio_register(bus);\n-}\n \n void fdt_fixup_board_enet(void *fdt)\n {\n-\tint i;\n-\n-\tfor (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\tcase PHY_INTERFACE_MODE_QSGMII:\n-\t\t\tswitch (mdio_mux[i]) {\n-\t\t\tcase EMI1_SLOT1:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot1\");\n-\t\t\t\tbreak;\n-\t\t\tcase EMI1_SLOT2:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot2\");\n-\t\t\t\tbreak;\n-\t\t\tcase EMI1_SLOT4:\n-\t\t\t\tfdt_status_okay_by_alias(fdt, \"emi1-slot4\");\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-\tint i, idx, lane, slot, interface;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\tu32 srds_s1, srds_s2;\n-\tu8 brdcfg12;\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tsrds_s2 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;\n-\tsrds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;\n-\n-\t/* Initialize the mdio_mux array so we can recognize empty elements */\n-\tfor (i = 0; i < NUM_FM_PORTS; i++)\n-\t\tmdio_mux[i] = EMI_NONE;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\t/* Register the muxing front-ends to the MDIO buses */\n-\tls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);\n-\tls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);\n-\tls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);\n-\tls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);\n-\tls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);\n-\n-\t/* Set the two on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x3333:\n-\t\t/* SGMII on slot 1, MAC 9 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\tcase 0x1333:\n-\tcase 0x2333:\n-\t\t/* SGMII on slot 1, MAC 10 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\tcase 0x1133:\n-\tcase 0x2233:\n-\t\t/* SGMII on slot 1, MAC 5/6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x1040:\n-\tcase 0x2040:\n-\t\t/* QSGMII on lane B, MAC 6/5/10/1 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC6,\n-\t\t\t\t\tQSGMII_CARD_PORT1_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC5,\n-\t\t\t\t\tQSGMII_CARD_PORT2_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10,\n-\t\t\t\t\tQSGMII_CARD_PORT3_PHY_ADDR_S2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC1,\n-\t\t\t\t\tQSGMII_CARD_PORT4_PHY_ADDR_S2);\n-\t\tbreak;\n-\tcase 0x3363:\n-\t\t/* SGMII on slot 1, MAC 9/10 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\tcase 0x1163:\n-\tcase 0x2263:\n-\tcase 0x2223:\n-\t\t/* SGMII on slot 1, MAC 6 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1046AQDS\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tif (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)\n-\t\t/* SGMII on slot 4, MAC 2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tidx = i - FM1_DTSEC1;\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\tcase PHY_INTERFACE_MODE_QSGMII:\n-\t\t\tif (interface == PHY_INTERFACE_MODE_SGMII) {\n-\t\t\t\tif (i == FM1_DTSEC5) {\n-\t\t\t\t\t/* route lane 2 to slot1 so to have\n-\t\t\t\t\t * one sgmii riser card supports\n-\t\t\t\t\t * MAC5 and MAC6.\n-\t\t\t\t\t */\n-\t\t\t\t\tbrdcfg12 = QIXIS_READ(brdcfg[12]);\n-\t\t\t\t\tQIXIS_WRITE(brdcfg[12],\n-\t\t\t\t\t\t brdcfg12 | 0x80);\n-\t\t\t\t}\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tSGMII_FM1_DTSEC1 + idx);\n-\t\t\t} else {\n-\t\t\t\t/* clear the bit 7 to route lane B on slot2. */\n-\t\t\t\tbrdcfg12 = QIXIS_READ(brdcfg[12]);\n-\t\t\t\tQIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);\n-\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tQSGMII_FM1_A);\n-\t\t\t\tlane_to_slot[lane] = 2;\n-\t\t\t}\n-\n-\t\t\tif (i == FM1_DTSEC2)\n-\t\t\t\tlane = 5;\n-\n-\t\t\tif (lane < 0)\n-\t\t\t\tbreak;\n-\n-\t\t\tslot = lane_to_slot[lane];\n-\t\t\tdebug(\"FM1@DTSEC%u expects SGMII in slot %u\\n\",\n-\t\t\t idx + 1, slot);\n-\t\t\tif (QIXIS_READ(present2) & (1 << (slot - 1)))\n-\t\t\t\tfm_disable_port(i);\n-\n-\t\t\tswitch (slot) {\n-\t\t\tcase 1:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT1;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 2:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT2;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 4:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT4;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tdefault:\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\tif (i == FM1_DTSEC3)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII1;\n-\t\t\telse if (i == FM1_DTSEC4)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII2;\n-\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tcpu_eth_init(bis);\n-\n-\treturn pci_eth_init(bis);\n }\n-#endif /* CONFIG_FMAN_ENET */\ndiff --git a/board/nxp/ls1046ardb/eth.c b/board/nxp/ls1046ardb/eth.c\nindex fee8e0e21d4..ce9b7b81e3d 100644\n--- a/board/nxp/ls1046ardb/eth.c\n+++ b/board/nxp/ls1046ardb/eth.c\n@@ -4,78 +4,7 @@\n */\n #include <config.h>\n #include <fdt_support.h>\n-#include <net.h>\n #include <asm/io.h>\n-#include <netdev.h>\n-#include <fm_eth.h>\n-#include <fsl_dtsec.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-\n-#include \"../common/fman.h\"\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_FMAN_ENET\n-\tint i;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tstruct mii_dev *dev;\n-\tu32 srds_s1;\n-\tstruct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\tFSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;\n-\tsrds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/* Set the two on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);\n-\n-\t/* Set the two on-board SGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);\n-\n-\t/* Set the on-board AQ PHY address */\n-\tfm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x1133:\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"Invalid SerDes protocol 0x%x for LS1046ARDB\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++)\n-\t\tfm_info_set_mdio(i, dev);\n-\n-\t/* 10GBase-R on lane A, MAC 9 */\n-\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\tfm_info_set_mdio(FM1_10GEC1, dev);\n-\n-\tcpu_eth_init(bis);\n-#endif\n-\n-\treturn pci_eth_init(bis);\n-}\n \n #ifdef CONFIG_FMAN_ENET\n int fdt_update_ethernet_dt(void *blob)\ndiff --git a/board/nxp/ls2080ardb/eth_ls2080rdb.c b/board/nxp/ls2080ardb/eth_ls2080rdb.c\nindex 7d5beb32417..6a8859fd0c5 100644\n--- a/board/nxp/ls2080ardb/eth_ls2080rdb.c\n+++ b/board/nxp/ls2080ardb/eth_ls2080rdb.c\n@@ -9,25 +9,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-\n-#if defined(CONFIG_PHY_AQUANTIA) && !defined(CONFIG_XPL_BUILD)\n-\t/*\n-\t * Export functions to be used by AQ firmware\n-\t * upload application\n-\t */\n-\tgd->jt->strcpy = strcpy;\n-\tgd->jt->mdelay = mdelay;\n-\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n-\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n-\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n-\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n-#endif\n-\n-\treturn 0;\n-}\n-\n #if defined(CONFIG_RESET_PHY_R)\n void reset_phy(void)\n {\ndiff --git a/board/nxp/lx2160a/eth_lx2160aqds.c b/board/nxp/lx2160a/eth_lx2160aqds.c\nindex 9939bb6f89e..4c16f565b69 100644\n--- a/board/nxp/lx2160a/eth_lx2160aqds.c\n+++ b/board/nxp/lx2160a/eth_lx2160aqds.c\n@@ -11,24 +11,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_PHY_AQUANTIA\n-\t/*\n-\t * Export functions to be used by AQ firmware\n-\t * upload application\n-\t */\n-\tgd->jt->strcpy = strcpy;\n-\tgd->jt->mdelay = mdelay;\n-\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n-\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n-\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n-\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n-#endif\n-\n-\treturn 0;\n-}\n-\n #if defined(CONFIG_RESET_PHY_R)\n void reset_phy(void)\n {\ndiff --git a/board/nxp/lx2160a/eth_lx2160ardb.c b/board/nxp/lx2160a/eth_lx2160ardb.c\nindex 90e7c9100e1..31bbac6310e 100644\n--- a/board/nxp/lx2160a/eth_lx2160ardb.c\n+++ b/board/nxp/lx2160a/eth_lx2160ardb.c\n@@ -11,23 +11,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_PHY_AQUANTIA\n-\t/*\n-\t * Export functions to be used by AQ firmware\n-\t * upload application\n-\t */\n-\tgd->jt->strcpy = strcpy;\n-\tgd->jt->mdelay = mdelay;\n-\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n-\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n-\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n-\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n-#endif\n-\treturn pci_eth_init(bis);\n-}\n-\n #if defined(CONFIG_RESET_PHY_R)\n void reset_phy(void)\n {\ndiff --git a/board/nxp/lx2160a/eth_lx2162aqds.c b/board/nxp/lx2160a/eth_lx2162aqds.c\nindex 805aa705be9..81b81d47978 100644\n--- a/board/nxp/lx2160a/eth_lx2162aqds.c\n+++ b/board/nxp/lx2160a/eth_lx2162aqds.c\n@@ -11,24 +11,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_PHY_AQUANTIA\n-\t/*\n-\t * Export functions to be used by AQ firmware\n-\t * upload application\n-\t */\n-\tgd->jt->strcpy = strcpy;\n-\tgd->jt->mdelay = mdelay;\n-\tgd->jt->mdio_get_current_dev = mdio_get_current_dev;\n-\tgd->jt->phy_find_by_mask = phy_find_by_mask;\n-\tgd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;\n-\tgd->jt->miiphy_set_current_dev = miiphy_set_current_dev;\n-#endif\n-\n-\treturn 0;\n-}\n-\n #if defined(CONFIG_RESET_PHY_R)\n void reset_phy(void)\n {\ndiff --git a/board/nxp/m5253demo/m5253demo.c b/board/nxp/m5253demo/m5253demo.c\nindex 50c5320b55c..7d4b60b283e 100644\n--- a/board/nxp/m5253demo/m5253demo.c\n+++ b/board/nxp/m5253demo/m5253demo.c\n@@ -133,10 +133,3 @@ void ide_set_reset(int idereset)\n \t}\n }\n #endif\t\t\t\t/* CONFIG_IDE */\n-\n-#ifdef CONFIG_DRIVER_DM9000\n-int board_eth_init(struct bd_info *bis)\n-{\n-\treturn dm9000_initialize(bis);\n-}\n-#endif\ndiff --git a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c\nindex ac91da3f4f6..036deb464b5 100644\n--- a/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c\n+++ b/board/nxp/mx6sxsabreauto/mx6sxsabreauto.c\n@@ -33,16 +33,6 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \\\n-\tPAD_CTL_SPEED_HIGH | \\\n-\tPAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)\n-\n-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \\\n-\tPAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)\n-\n-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n-\tPAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)\n-\n #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)\n #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \\\n \t\t\tPAD_CTL_SRE_FAST)\n@@ -55,48 +45,6 @@ int dram_init(void)\n \treturn 0;\n }\n \n-static iomux_v3_cfg_t const fec2_pads[] = {\n-\tMX6_PAD_ENET1_MDC__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_ENET1_MDIO__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RX_CTL__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RD0__ENET2_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RD1__ENET2_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RD2__ENET2_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RD3__ENET2_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_RXC__ENET2_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TX_CTL__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TD0__ENET2_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TD1__ENET2_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TD2__ENET2_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TD3__ENET2_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII2_TXC__ENET2_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-};\n-\n-static int setup_fec(void)\n-{\n-\tstruct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\n-\t/* Use 125MHz anatop loopback REF_CLK1 for ENET2 */\n-\tclrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK, 0);\n-\n-\treturn enable_fec_anatop_clock(1, ENET_125MHZ);\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-\tint ret;\n-\n-\timx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));\n-\tsetup_fec();\n-\n-\tret = fecmxc_initialize_multi(bis, 1,\n-\t\tCFG_FEC_MXC_PHYADDR, IMX_FEC_BASE);\n-\tif (ret)\n-\t\tprintf(\"FEC%d MXC: %s:failed\\n\", 1, __func__);\n-\n-\treturn ret;\n-}\n-\n int board_phy_config(struct phy_device *phydev)\n {\n \t/*\ndiff --git a/board/nxp/mx6sxsabresd/mx6sxsabresd.c b/board/nxp/mx6sxsabresd/mx6sxsabresd.c\nindex e3353feec68..cab0892affc 100644\n--- a/board/nxp/mx6sxsabresd/mx6sxsabresd.c\n+++ b/board/nxp/mx6sxsabresd/mx6sxsabresd.c\n@@ -40,16 +40,6 @@ DECLARE_GLOBAL_DATA_PTR;\n \tPAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW |\t\t\\\n \tPAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)\n \n-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \\\n-\tPAD_CTL_SPEED_HIGH | \\\n-\tPAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)\n-\n-#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \\\n-\tPAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)\n-\n-#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \\\n-\tPAD_CTL_SPEED_HIGH | PAD_CTL_SRE_FAST)\n-\n #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \\\n \tPAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)\n \n@@ -71,84 +61,16 @@ static iomux_v3_cfg_t const uart1_pads[] = {\n static iomux_v3_cfg_t const wdog_b_pad = {\n \tMX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL),\n };\n-static iomux_v3_cfg_t const fec1_pads[] = {\n-\tMX6_PAD_ENET1_MDC__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_ENET1_MDIO__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RX_CTL__ENET1_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RD0__ENET1_RX_DATA_0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RD1__ENET1_RX_DATA_1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RD2__ENET1_RX_DATA_2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RD3__ENET1_RX_DATA_3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_RXC__ENET1_RX_CLK | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TX_CTL__ENET1_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TD0__ENET1_TX_DATA_0 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TD1__ENET1_TX_DATA_1 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TD2__ENET1_TX_DATA_2 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TD3__ENET1_TX_DATA_3 | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-\tMX6_PAD_RGMII1_TXC__ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),\n-};\n \n static iomux_v3_cfg_t const peri_3v3_pads[] = {\n \tMX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL),\n };\n \n-static iomux_v3_cfg_t const phy_control_pads[] = {\n-\t/* 25MHz Ethernet PHY Clock */\n-\tMX6_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),\n-\n-\t/* ENET PHY Power */\n-\tMX6_PAD_ENET2_COL__GPIO2_IO_6 | MUX_PAD_CTRL(NO_PAD_CTRL),\n-\n-\t/* AR8031 PHY Reset */\n-\tMX6_PAD_ENET2_CRS__GPIO2_IO_7 | MUX_PAD_CTRL(NO_PAD_CTRL),\n-};\n-\n static void setup_iomux_uart(void)\n {\n \timx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));\n }\n \n-static int setup_fec(void)\n-{\n-\tstruct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;\n-\tstruct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;\n-\tint reg, ret;\n-\n-\t/* Use 125MHz anatop loopback REF_CLK1 for ENET1 */\n-\tclrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK, 0);\n-\n-\tret = enable_fec_anatop_clock(0, ENET_125MHZ);\n-\tif (ret)\n-\t\treturn ret;\n-\n-\timx_iomux_v3_setup_multiple_pads(phy_control_pads,\n-\t\t\t\t\t ARRAY_SIZE(phy_control_pads));\n-\n-\t/* Enable the ENET power, active low */\n-\tgpio_request(IMX_GPIO_NR(2, 6), \"enet_rst\");\n-\tgpio_direction_output(IMX_GPIO_NR(2, 6) , 0);\n-\n-\t/* Reset AR8031 PHY */\n-\tgpio_request(IMX_GPIO_NR(2, 7), \"phy_rst\");\n-\tgpio_direction_output(IMX_GPIO_NR(2, 7) , 0);\n-\tmdelay(10);\n-\tgpio_set_value(IMX_GPIO_NR(2, 7), 1);\n-\n-\treg = readl(&anatop->pll_enet);\n-\treg |= BM_ANADIG_PLL_ENET_REF_25M_ENABLE;\n-\twritel(reg, &anatop->pll_enet);\n-\n-\treturn 0;\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-\timx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));\n-\tsetup_fec();\n-\n-\treturn cpu_eth_init(bis);\n-}\n-\n int power_init_board(void)\n {\n \tstruct udevice *dev;\ndiff --git a/board/nxp/p2041rdb/Makefile b/board/nxp/p2041rdb/Makefile\nindex ebd0982b5db..5512458832d 100644\n--- a/board/nxp/p2041rdb/Makefile\n+++ b/board/nxp/p2041rdb/Makefile\n@@ -7,4 +7,3 @@\n obj-y\t+= p2041rdb.o\n obj-y\t+= cpld.o\n obj-y\t+= ddr.o\n-obj-y\t+= eth.o\ndiff --git a/board/nxp/p2041rdb/eth.c b/board/nxp/p2041rdb/eth.c\ndeleted file mode 100644\nindex b1ecc8d9642..00000000000\n--- a/board/nxp/p2041rdb/eth.c\n+++ /dev/null\n@@ -1,140 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2011 Freescale Semiconductor, Inc.\n- * Author: Mingkai Hu <Mingkai.hu@freescale.com>\n- */\n-\n-/*\n- * The RGMII PHYs are provided by the two on-board PHY. The SGMII PHYs\n- * are provided by the three on-board PHY or by the standard Freescale\n- * four-port SGMII riser card. We need to change the phy-handle in the\n- * kernel dts file to point to the correct PHY according to serdes mux\n- * and serdes protocol selection.\n- */\n-\n-#include <config.h>\n-#include <net.h>\n-#include <netdev.h>\n-#include <asm/fsl_serdes.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-#include <fsl_dtsec.h>\n-\n-#include \"cpld.h\"\n-#include \"../common/fman.h\"\n-\n-#ifdef CONFIG_FMAN_ENET\n-/*\n- * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means\n- * that the mapping must be determined dynamically, or that the lane maps to\n- * something other than a board slot\n- */\n-static u8 lane_to_slot[] = {\n-\t0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 2, 2, 2, 2, 0, 0, 0, 0\n-};\n-\n-static int riser_phy_addr[] = {\n-\tCFG_SYS_FM1_DTSEC1_RISER_PHY_ADDR,\n-\tCFG_SYS_FM1_DTSEC2_RISER_PHY_ADDR,\n-\tCFG_SYS_FM1_DTSEC3_RISER_PHY_ADDR,\n-\tCFG_SYS_FM1_DTSEC4_RISER_PHY_ADDR,\n-};\n-\n-/*\n- * Initialize the lane_to_slot[] array.\n- *\n- * On the P2040RDB board the mapping is controlled by CPLD register.\n- */\n-static void initialize_lane_to_slot(void)\n-{\n-\tu8 mux = CPLD_READ(serdes_mux);\n-\n-\tlane_to_slot[6] = (mux & SERDES_MUX_LANE_6_MASK) ? 0 : 1;\n-\tlane_to_slot[10] = (mux & SERDES_MUX_LANE_A_MASK) ? 0 : 2;\n-\tlane_to_slot[12] = (mux & SERDES_MUX_LANE_C_MASK) ? 0 : 2;\n-\tlane_to_slot[13] = (mux & SERDES_MUX_LANE_D_MASK) ? 0 : 2;\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_FMAN_ENET\n-\tstruct fsl_pq_mdio_info dtsec_mdio_info;\n-\tstruct tgec_mdio_info tgec_mdio_info;\n-\tunsigned int i, slot;\n-\tint lane;\n-\n-\tprintf(\"Initializing Fman\\n\");\n-\n-\tinitialize_lane_to_slot();\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct tsec_mii_mng *)CFG_SYS_FM1_DTSEC1_MDIO_ADDR;\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the real 1G MDIO bus */\n-\tfsl_pq_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct tgec_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the real 10G MDIO bus */\n-\tfm_tgec_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/*\n-\t * Program the three on-board SGMII PHY addresses. If the SGMII Riser\n-\t * card used, we'll override the PHY address later. For any DTSEC that\n-\t * is RGMII, we'll also override its PHY address later. We assume that\n-\t * DTSEC4 and DTSEC5 are used for RGMII.\n-\t */\n-\tfm_info_set_phy_address(FM1_DTSEC1, CFG_SYS_FM1_DTSEC1_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC2, CFG_SYS_FM1_DTSEC2_PHY_ADDR);\n-\tfm_info_set_phy_address(FM1_DTSEC3, CFG_SYS_FM1_DTSEC3_PHY_ADDR);\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tint idx = i - FM1_DTSEC1;\n-\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tlane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);\n-\t\t\tif (lane < 0)\n-\t\t\t\tbreak;\n-\t\t\tslot = lane_to_slot[lane];\n-\t\t\tif (slot)\n-\t\t\t\tfm_info_set_phy_address(i, riser_phy_addr[i]);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\t/* Only DTSEC4 and DTSEC5 can be routed to RGMII */\n-\t\t\tfm_info_set_phy_address(i, i == FM1_DTSEC5 ?\n-\t\t\t\t\tCFG_SYS_FM1_DTSEC5_PHY_ADDR :\n-\t\t\t\t\tCFG_SYS_FM1_DTSEC4_PHY_ADDR);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Fman1: DTSEC%u set to unknown interface %i\\n\",\n-\t\t\t idx + 1, fm_info_get_enet_if(i));\n-\t\t\tbreak;\n-\t\t}\n-\n-\t\tfm_info_set_mdio(i,\n-\t\t\tmiiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));\n-\t}\n-\n-\tlane = serdes_get_first_lane(XAUI_FM1);\n-\tif (lane >= 0) {\n-\t\tslot = lane_to_slot[lane];\n-\t\tif (slot)\n-\t\t\tfm_info_set_phy_address(FM1_10GEC1,\n-\t\t\t\t\tCFG_SYS_FM1_10GEC1_PHY_ADDR);\n-\t}\n-\n-\tfm_info_set_mdio(FM1_10GEC1,\n-\t\t\tmiiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));\n-\tcpu_eth_init(bis);\n-#endif\n-\n-\treturn pci_eth_init(bis);\n-}\ndiff --git a/board/nxp/t102xrdb/eth_t102xrdb.c b/board/nxp/t102xrdb/eth_t102xrdb.c\nindex 91f87983dc5..a07d242c1eb 100644\n--- a/board/nxp/t102xrdb/eth_t102xrdb.c\n+++ b/board/nxp/t102xrdb/eth_t102xrdb.c\n@@ -26,109 +26,6 @@\n #include <asm/fsl_serdes.h>\n #include \"../common/fman.h\"\n \n-int board_eth_init(struct bd_info *bis)\n-{\n-#if defined(CONFIG_FMAN_ENET)\n-\tint i, interface;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tstruct mii_dev *dev;\n-\tccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);\n-\tu32 srds_s1;\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\t\t\tFSL_CORENET2_RCWSR4_SRDS1_PRTCL;\n-\tsrds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/* Set the on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);\n-\n-\tswitch (srds_s1) {\n-#ifdef CONFIG_TARGET_T1024RDB\n-\tcase 0x95:\n-\t\t/* set the on-board RGMII2 PHY */\n-\t\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);\n-\n-\t\t/* set 10GBase-R with Aquantia AQR105 PHY */\n-\t\tfm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);\n-\t\tbreak;\n-#endif\n-\tcase 0x6a:\n-\tcase 0x6b:\n-\tcase 0x77:\n-\tcase 0x135:\n-\t\t/* set the on-board 2.5G SGMII AQR105 PHY */\n-\t\tfm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);\n-#ifdef CONFIG_TARGET_T1023RDB\n-\t\t/* set the on-board 1G SGMII RTL8211F PHY */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);\n-#endif\n-\t\tbreak;\n-\tdefault:\n-\t\tprintf(\"SerDes protocol 0x%x is not supported on T102xRDB\\n\",\n-\t\t srds_s1);\n-\t\tbreak;\n-\t}\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-#if defined(CONFIG_TARGET_T1023RDB)\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-#elif defined(CONFIG_TARGET_T1024RDB)\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-#endif\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_2500BASEX:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tfor (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_XGMII:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tcpu_eth_init(bis);\n-#endif /* CONFIG_FMAN_ENET */\n-\n-\treturn pci_eth_init(bis);\n-}\n-\n void fdt_fixup_board_enet(void *fdt)\n {\n }\ndiff --git a/board/nxp/t104xrdb/Makefile b/board/nxp/t104xrdb/Makefile\nindex 9bca1a1fbcc..cee574aabb9 100644\n--- a/board/nxp/t104xrdb/Makefile\n+++ b/board/nxp/t104xrdb/Makefile\n@@ -7,7 +7,6 @@ obj-y += spl.o\n else\n obj-y\t+= t104xrdb.o\n obj-y\t+= cpld.o\n-obj-y\t+= eth.o\n endif\n obj-y\t+= ddr.o\n obj-y\t+= law.o\ndiff --git a/board/nxp/t104xrdb/eth.c b/board/nxp/t104xrdb/eth.c\ndeleted file mode 100644\nindex c35ec368a45..00000000000\n--- a/board/nxp/t104xrdb/eth.c\n+++ /dev/null\n@@ -1,91 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright 2014 Freescale Semiconductor, Inc.\n- */\n-\n-#include <config.h>\n-#include <net.h>\n-#include <netdev.h>\n-#include <asm/fsl_serdes.h>\n-#include <asm/immap_85xx.h>\n-#include <fm_eth.h>\n-#include <fsl_mdio.h>\n-#include <malloc.h>\n-#include <fsl_dtsec.h>\n-#include <vsc9953.h>\n-\n-#include \"../common/fman.h\"\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#ifdef CONFIG_FMAN_ENET\n-\tstruct memac_mdio_info memac_mdio_info;\n-\tunsigned int i;\n-\tint phy_addr = 0;\n-\n-\tprintf(\"Initializing Fman\\n\");\n-\n-\tmemac_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\tmemac_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the real 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &memac_mdio_info);\n-\n-\t/*\n-\t * Program on board RGMII, SGMII PHY addresses.\n-\t */\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tint idx = i - FM1_DTSEC1;\n-\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-#ifdef CONFIG_TARGET_T1042D4RDB\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\t/* T1042D4RDB supports SGMII on DTSEC1, DTSEC2\n-\t\t\t * & DTSEC3\n-\t\t\t */\n-\t\t\tif (FM1_DTSEC1 == i)\n-\t\t\t\tphy_addr = CFG_SYS_SGMII1_PHY_ADDR;\n-\t\t\tif (FM1_DTSEC2 == i)\n-\t\t\t\tphy_addr = CFG_SYS_SGMII2_PHY_ADDR;\n-\t\t\tif (FM1_DTSEC3 == i)\n-\t\t\t\tphy_addr = CFG_SYS_SGMII3_PHY_ADDR;\n-\t\t\tfm_info_set_phy_address(i, phy_addr);\n-\t\t\tbreak;\n-#endif\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\tif (FM1_DTSEC4 == i)\n-\t\t\t\tphy_addr = CFG_SYS_RGMII1_PHY_ADDR;\n-\t\t\tif (FM1_DTSEC5 == i)\n-\t\t\t\tphy_addr = CFG_SYS_RGMII2_PHY_ADDR;\n-\t\t\tfm_info_set_phy_address(i, phy_addr);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_QSGMII:\n-\t\t\tfm_info_set_phy_address(i, 0);\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_NA:\n-\t\t\tfm_info_set_phy_address(i, 0);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tprintf(\"Fman1: DTSEC%u set to unknown interface %i\\n\",\n-\t\t\t idx + 1, fm_info_get_enet_if(i));\n-\t\t\tfm_info_set_phy_address(i, 0);\n-\t\t\tbreak;\n-\t\t}\n-\t\tif (fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_QSGMII ||\n-\t\t fm_info_get_enet_if(i) == PHY_INTERFACE_MODE_NA)\n-\t\t\tfm_info_set_mdio(i, NULL);\n-\t\telse\n-\t\t\tfm_info_set_mdio(i,\n-\t\t\t\t\t miiphy_get_dev_by_name(\n-\t\t\t\t\t\t\tDEFAULT_FM_MDIO_NAME));\n-\t}\n-\n-\tcpu_eth_init(bis);\n-#endif\n-\n-\treturn pci_eth_init(bis);\n-}\ndiff --git a/board/nxp/t208xqds/eth_t208xqds.c b/board/nxp/t208xqds/eth_t208xqds.c\nindex 12951df591e..e6aeb9bb66f 100644\n--- a/board/nxp/t208xqds/eth_t208xqds.c\n+++ b/board/nxp/t208xqds/eth_t208xqds.c\n@@ -32,467 +32,7 @@\n #include \"t208xqds_qixis.h\"\n #include <linux/libfdt.h>\n \n-#define EMI_NONE\t0xFFFFFFFF\n-#define EMI1_RGMII1\t0\n-#define EMI1_RGMII2 1\n-#define EMI1_SLOT1\t2\n-#if defined(CONFIG_TARGET_T2080QDS)\n-#define EMI1_SLOT2\t6\n-#define EMI1_SLOT3\t3\n-#define EMI1_SLOT4\t4\n-#define EMI1_SLOT5\t5\n-#define EMI2 7\n-#endif\n-\n-#define PCCR1_SGMIIA_KX_MASK\t\t0x00008000\n-#define PCCR1_SGMIIB_KX_MASK\t\t0x00004000\n-#define PCCR1_SGMIIC_KX_MASK\t\t0x00002000\n-#define PCCR1_SGMIID_KX_MASK\t\t0x00001000\n-#define PCCR1_SGMIIE_KX_MASK\t\t0x00000800\n-#define PCCR1_SGMIIF_KX_MASK\t\t0x00000400\n-#define PCCR1_SGMIIG_KX_MASK\t\t0x00000200\n-#define PCCR1_SGMIIH_KX_MASK\t\t0x00000100\n-\n-static int mdio_mux[NUM_FM_PORTS];\n-\n-static const char * const mdio_names[] = {\n-#if defined(CONFIG_TARGET_T2080QDS)\n-\t\"T2080QDS_MDIO_RGMII1\",\n-\t\"T2080QDS_MDIO_RGMII2\",\n-\t\"T2080QDS_MDIO_SLOT1\",\n-\t\"T2080QDS_MDIO_SLOT3\",\n-\t\"T2080QDS_MDIO_SLOT4\",\n-\t\"T2080QDS_MDIO_SLOT5\",\n-\t\"T2080QDS_MDIO_SLOT2\",\n-\t\"T2080QDS_MDIO_10GC\",\n-#endif\n-};\n-\n-/* Map SerDes1 8 lanes to default slot, will be initialized dynamically */\n-#if defined(CONFIG_TARGET_T2080QDS)\n-static u8 lane_to_slot[] = {3, 3, 3, 3, 1, 1, 1, 1};\n-#endif\n-\n-static const char *t208xqds_mdio_name_for_muxval(u8 muxval)\n-{\n-\treturn mdio_names[muxval];\n-}\n-\n-struct mii_dev *mii_dev_for_muxval(u8 muxval)\n-{\n-\tstruct mii_dev *bus;\n-\tconst char *name = t208xqds_mdio_name_for_muxval(muxval);\n-\n-\tif (!name) {\n-\t\tprintf(\"No bus for muxval %x\\n\", muxval);\n-\t\treturn NULL;\n-\t}\n-\n-\tbus = miiphy_get_dev_by_name(name);\n-\n-\tif (!bus) {\n-\t\tprintf(\"No bus by name %s\\n\", name);\n-\t\treturn NULL;\n-\t}\n-\n-\treturn bus;\n-}\n-\n-struct t208xqds_mdio {\n-\tu8 muxval;\n-\tstruct mii_dev *realbus;\n-};\n-\n-static void t208xqds_mux_mdio(u8 muxval)\n-{\n-\tu8 brdcfg4;\n-\tif (muxval < 8) {\n-\t\tbrdcfg4 = QIXIS_READ(brdcfg[4]);\n-\t\tbrdcfg4 &= ~BRDCFG4_EMISEL_MASK;\n-\t\tbrdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);\n-\t\tQIXIS_WRITE(brdcfg[4], brdcfg4);\n-\t}\n-}\n-\n-static int t208xqds_mdio_read(struct mii_dev *bus, int addr, int devad,\n-\t\t\t\tint regnum)\n-{\n-\tstruct t208xqds_mdio *priv = bus->priv;\n-\n-\tt208xqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->read(priv->realbus, addr, devad, regnum);\n-}\n-\n-static int t208xqds_mdio_write(struct mii_dev *bus, int addr, int devad,\n-\t\t\t\tint regnum, u16 value)\n-{\n-\tstruct t208xqds_mdio *priv = bus->priv;\n-\n-\tt208xqds_mux_mdio(priv->muxval);\n-\n-\treturn priv->realbus->write(priv->realbus, addr, devad, regnum, value);\n-}\n-\n-static int t208xqds_mdio_reset(struct mii_dev *bus)\n-{\n-\tstruct t208xqds_mdio *priv = bus->priv;\n-\n-\treturn priv->realbus->reset(priv->realbus);\n-}\n-\n-static int t208xqds_mdio_init(char *realbusname, u8 muxval)\n-{\n-\tstruct t208xqds_mdio *pmdio;\n-\tstruct mii_dev *bus = mdio_alloc();\n-\n-\tif (!bus) {\n-\t\tprintf(\"Failed to allocate t208xqds MDIO bus\\n\");\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio = malloc(sizeof(*pmdio));\n-\tif (!pmdio) {\n-\t\tprintf(\"Failed to allocate t208xqds private data\\n\");\n-\t\tfree(bus);\n-\t\treturn -1;\n-\t}\n-\n-\tbus->read = t208xqds_mdio_read;\n-\tbus->write = t208xqds_mdio_write;\n-\tbus->reset = t208xqds_mdio_reset;\n-\tstrcpy(bus->name, t208xqds_mdio_name_for_muxval(muxval));\n-\n-\tpmdio->realbus = miiphy_get_dev_by_name(realbusname);\n-\n-\tif (!pmdio->realbus) {\n-\t\tprintf(\"No bus with name %s\\n\", realbusname);\n-\t\tfree(bus);\n-\t\tfree(pmdio);\n-\t\treturn -1;\n-\t}\n-\n-\tpmdio->muxval = muxval;\n-\tbus->priv = pmdio;\n-\treturn mdio_register(bus);\n-}\n-\n void fdt_fixup_board_enet(void *fdt)\n {\n \treturn;\n }\n-\n-/*\n- * This function reads RCW to check if Serdes1{A:H} is configured\n- * to slot 1/2/3/4/5/6/7 and update the lane_to_slot[] array accordingly\n- */\n-static void initialize_lane_to_slot(void)\n-{\n-\tccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);\n-\tu32 srds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\t\tFSL_CORENET2_RCWSR4_SRDS1_PRTCL;\n-\n-\tsrds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tswitch (srds_s1) {\n-#if defined(CONFIG_TARGET_T2080QDS)\n-\tcase 0x51:\n-\tcase 0x5f:\n-\tcase 0x65:\n-\tcase 0x6b:\n-\tcase 0x71:\n-\t\tlane_to_slot[5] = 2;\n-\t\tlane_to_slot[6] = 2;\n-\t\tlane_to_slot[7] = 2;\n-\t\tbreak;\n-\tcase 0xa6:\n-\tcase 0x8e:\n-\tcase 0x8f:\n-\tcase 0x82:\n-\tcase 0x83:\n-\tcase 0xd3:\n-\tcase 0xd9:\n-\tcase 0xcb:\n-\t\tlane_to_slot[6] = 2;\n-\t\tlane_to_slot[7] = 2;\n-\t\tbreak;\n-\tcase 0xda:\n-\t\tlane_to_slot[4] = 3;\n-\t\tlane_to_slot[5] = 3;\n-\t\tlane_to_slot[6] = 3;\n-\t\tlane_to_slot[7] = 3;\n-\t\tbreak;\n-#endif\n-\tdefault:\n-\t\tbreak;\n-\t}\n-}\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#if defined(CONFIG_FMAN_ENET)\n-\tint i, idx, lane, slot, interface;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);\n-\tu32 rcwsr13 = in_be32(&gur->rcwsr[13]);\n-\tu32 srds_s1;\n-\n-\tsrds_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\t\t\tFSL_CORENET2_RCWSR4_SRDS1_PRTCL;\n-\tsrds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\n-\tinitialize_lane_to_slot();\n-\n-\t/* Initialize the mdio_mux array so we can recognize empty elements */\n-\tfor (i = 0; i < NUM_FM_PORTS; i++)\n-\t\tmdio_mux[i] = EMI_NONE;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM1_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\t/* Register the muxing front-ends to the MDIO buses */\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);\n-#if defined(CONFIG_TARGET_T2080QDS)\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);\n-#endif\n-\tt208xqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);\n-\tt208xqds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);\n-\n-\t/* Set the two on-board RGMII PHY address */\n-\tfm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);\n-\tif ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==\n-\t\t\tFSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII)\n-\t\tfm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);\n-\telse\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);\n-\n-\tswitch (srds_s1) {\n-\tcase 0x1b:\n-\tcase 0x1c:\n-\tcase 0x95:\n-\tcase 0xa2:\n-\tcase 0x94:\n-\t\t/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\t/* T2080QDS: SGMII in Slot2; T2081QDS: SGMII in Slot1 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x50:\n-\tcase 0x51:\n-\tcase 0x5e:\n-\tcase 0x5f:\n-\tcase 0x64:\n-\tcase 0x65:\n-\t\t/* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);\n-\t\t/* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x66:\n-\tcase 0x67:\n-\t\t/*\n-\t\t * 10GBase-R does not need a PHY to work, but to avoid U-Boot\n-\t\t * use default PHY address which is zero to a MAC when it found\n-\t\t * a MAC has no PHY address, we give a PHY address to 10GBase-R\n-\t\t * MAC, and should not use a real XAUI PHY address, since\n-\t\t * MDIO can access it successfully, and then MDIO thinks\n-\t\t * the XAUI card is used for the 10GBase-R MAC, which will cause\n-\t\t * error.\n-\t\t */\n-\t\tfm_info_set_phy_address(FM1_10GEC1, 4);\n-\t\tfm_info_set_phy_address(FM1_10GEC2, 5);\n-\t\tfm_info_set_phy_address(FM1_10GEC3, 6);\n-\t\tfm_info_set_phy_address(FM1_10GEC4, 7);\n-\t\tbreak;\n-\tcase 0x6a:\n-\tcase 0x6b:\n-\t\tfm_info_set_phy_address(FM1_10GEC1, 4);\n-\t\tfm_info_set_phy_address(FM1_10GEC2, 5);\n-\t\tfm_info_set_phy_address(FM1_10GEC3, 6);\n-\t\tfm_info_set_phy_address(FM1_10GEC4, 7);\n-\t\t/* T2080QDS: SGMII in Slot2; T2081QDS: in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x6c:\n-\tcase 0x6d:\n-\t\tfm_info_set_phy_address(FM1_10GEC1, 4);\n-\t\tfm_info_set_phy_address(FM1_10GEC2, 5);\n-\t\t/* T2080QDS: SGMII in Slot3; T2081QDS: in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0x70:\n-\tcase 0x71:\n-\t\t/* SGMII in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\t/* SGMII in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0xa6:\n-\tcase 0x8e:\n-\tcase 0x8f:\n-\tcase 0x82:\n-\tcase 0x83:\n-\t\t/* SGMII in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\t/* SGMII in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tbreak;\n-\tcase 0xa4:\n-\tcase 0x96:\n-\tcase 0x8a:\n-\t\t/* SGMII in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-#if defined(CONFIG_TARGET_T2080QDS)\n-\tcase 0xd9:\n-\tcase 0xd3:\n-\tcase 0xcb:\n-\t\t/* SGMII in Slot3 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\t/* SGMII in Slot2 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tbreak;\n-#endif\n-\tcase 0xf2:\n-\t\t/* T2080QDS: SGMII in Slot3; T2081QDS: SGMII in Slot7 */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT3_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);\n-\t\tbreak;\n-\tdefault:\n-\t\tbreak;\n-\t}\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tidx = i - FM1_DTSEC1;\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\tSGMII_FM1_DTSEC1 + idx);\n-\t\t\tif (lane < 0)\n-\t\t\t\tbreak;\n-\t\t\tslot = lane_to_slot[lane];\n-\t\t\tdebug(\"FM1@DTSEC%u expects SGMII in slot %u\\n\",\n-\t\t\t idx + 1, slot);\n-\t\t\tif (QIXIS_READ(present2) & (1 << (slot - 1)))\n-\t\t\t\tfm_disable_port(i);\n-\n-\t\t\tswitch (slot) {\n-\t\t\tcase 1:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT1;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 2:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT2;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\tcase 3:\n-\t\t\t\tmdio_mux[i] = EMI1_SLOT3;\n-\t\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(\n-\t\t\t\t\t\t mdio_mux[i]));\n-\t\t\t\tbreak;\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase PHY_INTERFACE_MODE_RGMII:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n-\t\tcase PHY_INTERFACE_MODE_RGMII_ID:\n-\t\t\tif (i == FM1_DTSEC3)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII1;\n-\t\t\telse if (i == FM1_DTSEC4 || FM1_DTSEC10)\n-\t\t\t\tmdio_mux[i] = EMI1_RGMII2;\n-\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tfor (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {\n-\t\tidx = i - FM1_10GEC1;\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_XGMII:\n-\t\t\tif (srds_s1 == 0x51) {\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tXAUI_FM1_MAC9 + idx);\n-\t\t\t} else if ((srds_s1 == 0x5f) || (srds_s1 == 0x65)) {\n-\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tHIGIG_FM1_MAC9 + idx);\n-\t\t\t} else {\n-\t\t\t\tif (i == FM1_10GEC1 || i == FM1_10GEC2)\n-\t\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tXFI_FM1_MAC9 + idx);\n-\t\t\t\telse\n-\t\t\t\t\tlane = serdes_get_first_lane(FSL_SRDS_1,\n-\t\t\t\t\t\tXFI_FM1_MAC1 + idx);\n-\t\t\t}\n-\n-\t\t\tif (lane < 0)\n-\t\t\t\tbreak;\n-\t\t\tmdio_mux[i] = EMI2;\n-\t\t\tfm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));\n-\n-\t\t\tif ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||\n-\t\t\t (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||\n-\t\t\t (srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||\n-\t\t\t (srds_s1 == 0x71)) {\n-\t\t\t\t/* As 10GBase-R is in cage intead of a slot, so\n-\t\t\t\t * ensure doesn't disable the corresponding port\n-\t\t\t\t */\n-\t\t\t\tbreak;\n-\t\t\t}\n-\n-\t\t\tslot = lane_to_slot[lane];\n-\t\t\tif (QIXIS_READ(present2) & (1 << (slot - 1)))\n-\t\t\t\tfm_disable_port(i);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tcpu_eth_init(bis);\n-#endif /* CONFIG_FMAN_ENET */\n-\n-\treturn pci_eth_init(bis);\n-}\ndiff --git a/board/nxp/t4rdb/eth.c b/board/nxp/t4rdb/eth.c\nindex e7646365d7d..dc2390f1003 100644\n--- a/board/nxp/t4rdb/eth.c\n+++ b/board/nxp/t4rdb/eth.c\n@@ -35,118 +35,3 @@ void fdt_fixup_board_enet(void *fdt)\n {\n \treturn;\n }\n-\n-int board_eth_init(struct bd_info *bis)\n-{\n-#if defined(CONFIG_FMAN_ENET)\n-\tint i, interface;\n-\tstruct memac_mdio_info dtsec_mdio_info;\n-\tstruct memac_mdio_info tgec_mdio_info;\n-\tstruct mii_dev *dev;\n-\tccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);\n-\tu32 srds_prtcl_s1, srds_prtcl_s2;\n-\n-\tsrds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &\n-\t\t\t\tFSL_CORENET2_RCWSR4_SRDS1_PRTCL;\n-\tsrds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;\n-\tsrds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &\n-\t\t\t\tFSL_CORENET2_RCWSR4_SRDS2_PRTCL;\n-\tsrds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;\n-\n-\tdtsec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM2_DTSEC_MDIO_ADDR;\n-\n-\tdtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;\n-\n-\t/* Register the 1G MDIO bus */\n-\tfm_memac_mdio_init(bis, &dtsec_mdio_info);\n-\n-\ttgec_mdio_info.regs =\n-\t\t(struct memac_mdio_controller *)CFG_SYS_FM2_TGEC_MDIO_ADDR;\n-\ttgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;\n-\n-\t/* Register the 10G MDIO bus */\n-\tfm_memac_mdio_init(bis, &tgec_mdio_info);\n-\n-\tif ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {\n-\t\t/* SGMII */\n-\t\tfm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);\n-\t\tfm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);\n-\t\tfm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY_ADDR3);\n-\t\tfm_info_set_phy_address(FM1_DTSEC4, SGMII_PHY_ADDR4);\n-\t} else {\n-\t\tputs(\"Invalid SerDes1 protocol for T4240RDB\\n\");\n-\t}\n-\n-\tfm_disable_port(FM1_DTSEC5);\n-\tfm_disable_port(FM1_DTSEC6);\n-\n-\tfor (i = FM1_DTSEC1; i < FM1_DTSEC1 + CFG_SYS_NUM_FM1_DTSEC; i++) {\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tfor (i = FM1_10GEC1; i < FM1_10GEC1 + CFG_SYS_NUM_FM1_10GEC; i++) {\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_XGMII:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-#if (CFG_SYS_NUM_FMAN == 2)\n-\tif ((srds_prtcl_s2 == 56) || (srds_prtcl_s2 == 55)) {\n-\t\t/* SGMII && 10GBase-R */\n-\t\tfm_info_set_phy_address(FM2_DTSEC1, SGMII_PHY_ADDR5);\n-\t\tfm_info_set_phy_address(FM2_DTSEC2, SGMII_PHY_ADDR6);\n-\t\tfm_info_set_phy_address(FM2_DTSEC3, SGMII_PHY_ADDR7);\n-\t\tfm_info_set_phy_address(FM2_DTSEC4, SGMII_PHY_ADDR8);\n-\t\tfm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM2_10GEC1, FM2_10GEC2_PHY_ADDR);\n-\t\tfm_info_set_phy_address(FM2_10GEC2, FM2_10GEC1_PHY_ADDR);\n-\t} else {\n-\t\tputs(\"Invalid SerDes2 protocol for T4240RDB\\n\");\n-\t}\n-\n-\tfm_disable_port(FM2_DTSEC5);\n-\tfm_disable_port(FM2_DTSEC6);\n-\tfor (i = FM2_DTSEC1; i < FM2_DTSEC1 + CFG_SYS_NUM_FM2_DTSEC; i++) {\n-\t\tinterface = fm_info_get_enet_if(i);\n-\t\tswitch (interface) {\n-\t\tcase PHY_INTERFACE_MODE_SGMII:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-\n-\tfor (i = FM2_10GEC1; i < FM2_10GEC1 + CFG_SYS_NUM_FM2_10GEC; i++) {\n-\t\tswitch (fm_info_get_enet_if(i)) {\n-\t\tcase PHY_INTERFACE_MODE_XGMII:\n-\t\t\tdev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);\n-\t\t\tfm_info_set_mdio(i, dev);\n-\t\t\tbreak;\n-\t\tdefault:\n-\t\t\tbreak;\n-\t\t}\n-\t}\n-#endif /* CFG_SYS_NUM_FMAN */\n-\n-\tcpu_eth_init(bis);\n-#endif /* CONFIG_FMAN_ENET */\n-\n-\treturn pci_eth_init(bis);\n-}\n", "prefixes": [ "05/10" ] }