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GET /api/1.1/patches/2230066/?format=api
{ "id": 2230066, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230066/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com>", "date": "2026-04-29T06:42:25", "name": "[v5,3/5] PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b11b02b3e883a912b6892e1409adbebf70702db8", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.1/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com/mbox/", "series": [ { "id": 502001, "url": "http://patchwork.ozlabs.org/api/1.1/series/502001/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502001", "date": "2026-04-29T06:42:22", "name": "PCI: qcom: Add D3cold support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502001/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230066/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230066/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53371-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=brwlGrWb;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Cb0KhiHC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260429-d3cold-v5-3-89e9735b9df6@oss.qualcomm.com>", "References": "<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>", "In-Reply-To": "<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Will Deacon <will@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777444949; l=5203;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=rgQE2wlPYdGz9Ms01FRnDjEVC8FuvzCU6MQDVXSfne0=;\n b=JaOQDILfJYOoMchLl/cEYOB0wve+tsQCiwlZ6fMiP8IcMh282moLRs2rp/lrg+7a8ohN/4Pgx\n SXKbz9xiUeNAK/x7N3nEAaWjmjNYdphcZac1xnsDzcrx7NiIDmtyHad", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-GUID": "qZWFRMzkWEe65UQKp7NEGLAmcqYqkAnC", "X-Proofpoint-ORIG-GUID": "qZWFRMzkWEe65UQKp7NEGLAmcqYqkAnC", "X-Authority-Analysis": "v=2.4 cv=BfDoFLt2 c=1 sm=1 tr=0 ts=69f1a869 cx=c_pps\n a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22\n a=EUspDBNiAAAA:8 a=oQbQ34n3Jerzy_GFPTkA:9 a=QEXdDO2ut3YA:10\n a=iS9zxrgQBfv6-_F4QbHw:22", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI5MDA2NCBTYWx0ZWRfX7HrbJxb646hC\n 1SDE+9KviNU2XmK20ejgkx9PpkQV0H02Oj1YzhguQNjJkXOSTOWLJCy3rbSkfPdBJz+So0IoqPd\n z3uXP24oLhsVo+fwbyjN+MCSy2QI9yg5XVWpOHj7uIRre4dJkXBUYOfYlU4vLuMjSjaogNrZtgf\n a4llA47Rriep+5JaUQyyD8+PJmolAjtJKrRykUS/Unim/i6vt3o2Zh7pwUAP6Gj7MIRYExoNBFU\n hshPUdfhjfsoYGI+UQnaDknRtPf7BU7aOQfsEL2YD+pmic87yMmOEQuFY//Mly6ZRDQ3SixIEGt\n Nm4nXbnKiG1bkB3oCGnFFxdsg+/2UKNrqirIThztCMH5nKx4suxBjcSb0ohEAiI1IrLEz9CieGN\n 9DPkRCTCtAtD3jxC2Gk7ZEIxAmEC3eK78uIT5X0gGq1DHKz3jdwPyc7dYNgP+Ojr/3Zg+VwTsmd\n ZNqtVI0P4YZDZUGmSRA==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0\n lowpriorityscore=0 bulkscore=0 adultscore=0 phishscore=0 spamscore=0\n suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604290064" }, "content": "Some Qcom PCIe controller variants bring the PHY out of test power-down\n(PHY_TEST_PWR_DOWN) during init. When the link is later transitioned\ntowards D3cold and the driver disables PCIe clocks and/or regulators\nwithout explicitly re-asserting PHY_TEST_PWR_DOWN, the PHY can remain\npartially powered, leading to avoidable power leakage.\n\nUpdate the init-path comments to reflect that PARF_PHY_CTRL is used to\npower the PHY on. Also, for controller revisions that enable PHY power\nin init (2.3.2, 2.3.3, 2.4.0, 2.7.0 and 2.9.0), explicitly power the PHY\ndown via PARF_PHY_CTRL in the deinit path before disabling clocks or\nregulators.\n\nThis ensures the PHY is put into a defined low-power state prior to\nremoving its supplies, preventing leakage when entering D3cold.\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-qcom.c | 38 +++++++++++++++++++++++++++++++---\n 1 file changed, 35 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c\nindex 085300c1d1ec..9dd808e85409 100644\n--- a/drivers/pci/controller/dwc/pcie-qcom.c\n+++ b/drivers/pci/controller/dwc/pcie-qcom.c\n@@ -532,7 +532,7 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)\n \tu32 val;\n \tint ret;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -699,6 +699,12 @@ static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state*/\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \tregulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);\n@@ -731,7 +737,7 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)\n {\n \tu32 val;\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -795,6 +801,12 @@ static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state*/\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \treset_control_bulk_assert(res->num_resets, res->resets);\n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n@@ -863,6 +875,12 @@ static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n@@ -918,6 +936,7 @@ static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)\n \tu16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);\n \tu32 val;\n \n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -1013,7 +1032,7 @@ static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)\n \t/* configure PCIe to RC mode */\n \twritel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);\n \n-\t/* enable PCIe clocks and resets */\n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n@@ -1084,6 +1103,12 @@ static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n \n@@ -1188,6 +1213,12 @@ static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)\n static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)\n {\n \tstruct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;\n+\tu32 val;\n+\n+\t/* Force PHY to lowest power state */\n+\tval = readl(pcie->parf + PARF_PHY_CTRL);\n+\tval |= PHY_TEST_PWR_DOWN;\n+\twritel(val, pcie->parf + PARF_PHY_CTRL);\n \n \tclk_bulk_disable_unprepare(res->num_clks, res->clks);\n }\n@@ -1228,6 +1259,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)\n \tu32 val;\n \tint i;\n \n+\t/* Force PHY out of lowest power state */\n \tval = readl(pcie->parf + PARF_PHY_CTRL);\n \tval &= ~PHY_TEST_PWR_DOWN;\n \twritel(val, pcie->parf + PARF_PHY_CTRL);\n", "prefixes": [ "v5", "3/5" ] }