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{ "id": 2230064, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230064/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-1-89e9735b9df6@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260429-d3cold-v5-1-89e9735b9df6@oss.qualcomm.com>", "date": "2026-04-29T06:42:23", "name": "[v5,1/5] PCI: host-common: Add helper to determine host bridge D3cold eligibility", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "73a2978964b4a8bb8771a0861c1c759fe970034e", "submitter": { "id": 89908, "url": "http://patchwork.ozlabs.org/api/1.1/people/89908/?format=api", "name": "Krishna Chaitanya Chundru", "email": "krishna.chundru@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260429-d3cold-v5-1-89e9735b9df6@oss.qualcomm.com/mbox/", "series": [ { "id": 502001, "url": "http://patchwork.ozlabs.org/api/1.1/series/502001/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502001", "date": "2026-04-29T06:42:22", "name": "PCI: qcom: Add D3cold support", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/502001/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230064/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230064/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53369-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Fj8FXeYM;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=F4WVkwT5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260429-d3cold-v5-1-89e9735b9df6@oss.qualcomm.com>", "References": "<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>", "In-Reply-To": "<20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com>", "To": "Jingoo Han <jingoohan1@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>, Rob Herring <robh@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>, Will Deacon <will@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com,\n Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1777444949; l=5116;\n i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id;\n bh=FM8NSfNkcJ+OAXnXrK/t/KiNoyaQ6US4QTFzM89JCZ8=;\n b=K3LQ2ALmkEnry3Jpnx3w+lm/fygqHjFpyXjjyleGf6Vb/X5u5okUeTqsxaRl61VwYCNLUloXU\n eLbSzw5GJe/CPBY5JRnFaa88MzYlPV6NajQg6GWbTCoBPnJmwpMCZva", "X-Developer-Key": "i=krishna.chundru@oss.qualcomm.com; a=ed25519;\n pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg=", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI5MDA2NCBTYWx0ZWRfXxMQ1zsvwRZ4R\n Y8DRpY2KmyjAmCtmo0IL7NoxemouBGRGHhu16FZvuh7W9YK74m5SUgj0NpVZigHtkMV0u09mZly\n q9Md16Q23Pv8az/rR9Ww2p4HV1FgdmWcLl42MIrYTmqCXWcmPSB+wFfoCIpTj6bSUV89++xbNxi\n fFiWLzFjQmyxFOwE7OD0lkmg4MmY6xyQahv7reLJ0dV++gOyw2D3ygJAqbHl0OgFq+fWdow3IOe\n 7jIpLiCZeGaXwSuPWdJ5E6+Xs9kqF62Q/UVZ3ZswRpIgV33vtiAjxua9ByrrxVPwuRvzqKcw+So\n XW1X8neO3iCMft9HnY7dPOxdd1TQG23Djy1e6d8c6WwX9EbtS8WTJeTVZWhndUQzt4gNuUAksBy\n 2R/nPqqFyMVIIoFwUgN/we/uIY8uA+tJcKSrRUyYb7PlUFGD4HcSlJQOEUm/WjP5Kg/UnT6h7VU\n pp/hJnA8n0ksWv6rvxA==", "X-Proofpoint-GUID": "Ioq40EbLhS3IHcExjreeKBz677rBb_Ox", "X-Authority-Analysis": "v=2.4 cv=MuFiLWae c=1 sm=1 tr=0 ts=69f1a860 cx=c_pps\n a=0uOsjrqzRL749jD1oC5vDA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17\n a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10\n a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22\n a=EUspDBNiAAAA:8 a=w2i6tlqj-xX_7Oe5WM0A:9 a=QEXdDO2ut3YA:10\n a=mQ_c8vxmzFEMiUWkPHU9:22", "X-Proofpoint-ORIG-GUID": "Ioq40EbLhS3IHcExjreeKBz677rBb_Ox", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n bulkscore=0 clxscore=1015 phishscore=0 impostorscore=0 adultscore=0\n priorityscore=1501 malwarescore=0 suspectscore=0 lowpriorityscore=0\n spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound\n adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000\n definitions=main-2604290064" }, "content": "Add a common helper, pci_host_common_d3cold_possible(), to determine\nwhether PCIe devices under host bridge can safely transition to D3cold.\n\nThis helper is intended to be used by PCI host controller drivers to\ndecide whether they may safely put the host bridge into D3cold based on\nthe power state and wakeup capabilities of downstream endpoints.\n\nThe helper walks all devices on the all bridge buses and only allows\nthe devices to enter D3cold if all PCIe endpoints are already in\nPCI_D3hot. This ensures that we do not power off the host bridge while\nany active endpoint still requires the link to remain powered.\n\nFor devices that may wake the system, the helper additionally requires\nthat the device supports PME wake from D3cold (via WAKE#). Devices that\ndo not have wakeup enabled are not restricted by this check and do not\nblock the devices under host bridge from entering D3cold.\n\nDevices without a bound driver and with PCI not enabled via sysfs are\ntreated as inactive and therefore do not prevent the devices under host\nbridge from entering D3cold. This allows controllers to power down more\naggressively when there are no actively managed endpoints.\n\nSome devices (e.g. M.2 without auxiliary power) lose PME detection when\nmain power is removed. Even if such devices advertise PME-from-D3cold\ncapability, entering D3cold may break wakeup. So, return PME-from-D3cold\ncapability via an output parameter so PCIe controller drivers can apply\nplatform-specific handling to preserve wakeup functionality.\n\nSigned-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>\n---\n drivers/pci/controller/pci-host-common.c | 71 ++++++++++++++++++++++++++++++++\n drivers/pci/controller/pci-host-common.h | 2 +\n 2 files changed, 73 insertions(+)", "diff": "diff --git a/drivers/pci/controller/pci-host-common.c b/drivers/pci/controller/pci-host-common.c\nindex d6258c1cffe5..09432d69175c 100644\n--- a/drivers/pci/controller/pci-host-common.c\n+++ b/drivers/pci/controller/pci-host-common.c\n@@ -17,6 +17,9 @@\n \n #include \"pci-host-common.h\"\n \n+#define PCI_HOST_D3COLD_ALLOWED BIT(0)\n+#define PCI_HOST_PME_D3COLD_CAPABLE BIT(1)\n+\n static void gen_pci_unmap_cfg(void *ptr)\n {\n \tpci_ecam_free((struct pci_config_window *)ptr);\n@@ -106,5 +109,73 @@ void pci_host_common_remove(struct platform_device *pdev)\n }\n EXPORT_SYMBOL_GPL(pci_host_common_remove);\n \n+static int __pci_host_common_d3cold_possible(struct pci_dev *pdev, void *userdata)\n+{\n+\tu32 *flags = userdata;\n+\tint type;\n+\n+\t/* Ignore conventional PCI devices */\n+\tif (!pci_is_pcie(pdev))\n+\t\treturn 0;\n+\n+\ttype = pci_pcie_type(pdev);\n+\tif (type != PCI_EXP_TYPE_ENDPOINT &&\n+\t type != PCI_EXP_TYPE_LEG_END &&\n+\t type != PCI_EXP_TYPE_RC_END)\n+\t\treturn 0;\n+\n+\tif (!pdev->dev.driver && !pci_is_enabled(pdev))\n+\t\treturn 0;\n+\n+\tif (pdev->current_state != PCI_D3hot)\n+\t\tgoto exit;\n+\n+\tif (device_may_wakeup(&pdev->dev)) {\n+\t\tif (!pci_pme_capable(pdev, PCI_D3cold))\n+\t\t\tgoto exit;\n+\t\telse\n+\t\t\t*flags |= PCI_HOST_PME_D3COLD_CAPABLE;\n+\t}\n+\n+\treturn 0;\n+\n+exit:\n+\t*flags &= ~PCI_HOST_D3COLD_ALLOWED;\n+\n+\treturn -EOPNOTSUPP;\n+}\n+\n+/**\n+ * pci_host_common_d3cold_possible - Determine whether the host bridge can transition the\n+ *\t\t\t\t devices into D3Cold.\n+ *\n+ * @bridge: PCI host bridge to check\n+ * @pme_capable: Pointer to update if there is any device which is capable of generating\n+ *\t\t PME from D3cold.\n+ *\n+ * Walk downstream PCIe endpoint devices and determine whether the host bridge\n+ * is permitted to transition the devices into D3cold.\n+ *\n+ * Devices under host bridge can enter D3cold only if all active PCIe endpoints are in\n+ * PCI_D3hot and any wakeup-enabled endpoint is capable of generating PME from D3cold.\n+ * Inactive endpoints are ignored.\n+ *\n+ * The @pme_capable output allows PCIe controller drivers to apply\n+ * platform-specific handling to preserve wakeup functionality.\n+ *\n+ * Return: %true if the host bridge may enter D3cold, otherwise %false.\n+ */\n+bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge, bool *pme_capable)\n+{\n+\tu32 flags = PCI_HOST_D3COLD_ALLOWED;\n+\n+\tpci_walk_bus(bridge->bus, __pci_host_common_d3cold_possible, &flags);\n+\n+\t*pme_capable = !!(flags & PCI_HOST_PME_D3COLD_CAPABLE);\n+\n+\treturn !!(flags & PCI_HOST_D3COLD_ALLOWED);\n+}\n+EXPORT_SYMBOL_GPL(pci_host_common_d3cold_possible);\n+\n MODULE_DESCRIPTION(\"Common library for PCI host controller drivers\");\n MODULE_LICENSE(\"GPL v2\");\ndiff --git a/drivers/pci/controller/pci-host-common.h b/drivers/pci/controller/pci-host-common.h\nindex b5075d4bd7eb..7eb5599b9ce4 100644\n--- a/drivers/pci/controller/pci-host-common.h\n+++ b/drivers/pci/controller/pci-host-common.h\n@@ -20,4 +20,6 @@ void pci_host_common_remove(struct platform_device *pdev);\n \n struct pci_config_window *pci_host_common_ecam_create(struct device *dev,\n \tstruct pci_host_bridge *bridge, const struct pci_ecam_ops *ops);\n+\n+bool pci_host_common_d3cold_possible(struct pci_host_bridge *bridge, bool *pme_capable);\n #endif\n", "prefixes": [ "v5", "1/5" ] }