Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2230043/?format=api
{ "id": 2230043, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230043/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/52fd49b46f43dce7be11c6e4e44d912c8c14e13c.1777440221.git.dinesh.maniyam@altera.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<52fd49b46f43dce7be11c6e4e44d912c8c14e13c.1777440221.git.dinesh.maniyam@altera.com>", "date": "2026-04-29T05:32:20", "name": "arm: dts: socfpga_arria10_socdk_sdmmc: migrate to OF_UPSTREAM", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "951a17412fe4c70f579250cdb8390424d80c4b39", "submitter": { "id": 90303, "url": "http://patchwork.ozlabs.org/api/1.1/people/90303/?format=api", "name": "Maniyam, Dinesh", "email": "dinesh.maniyam@altera.com" }, "delegate": { "id": 152680, "url": "http://patchwork.ozlabs.org/api/1.1/users/152680/?format=api", "username": "TIENFONG", "first_name": "TIEN FONG", "last_name": "CHEE", "email": "tien.fong.chee@intel.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/52fd49b46f43dce7be11c6e4e44d912c8c14e13c.1777440221.git.dinesh.maniyam@altera.com/mbox/", "series": [ { "id": 501985, "url": "http://patchwork.ozlabs.org/api/1.1/series/501985/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501985", "date": "2026-04-29T05:32:20", "name": "arm: dts: socfpga_arria10_socdk_sdmmc: migrate to OF_UPSTREAM", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501985/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230043/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230043/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=altera.com header.i=@altera.com header.a=rsa-sha256\n header.s=selector2 header.b=a8kUtAUK;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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mx.microsoft.com 1; spf=pass\n smtp.mailfrom=altera.com; dmarc=pass action=none header.from=altera.com;\n dkim=pass header.d=altera.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=altera.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=xV2A2Vh0uv+fF9nspa8+ojBQw/Ibg/Q1PW+ahK4QLvc=;\n b=a8kUtAUKo2rq8BMKLX9xHg31zveZmFWsrw2/DWn4obzojjOMgqP8GWORjTMTRucTzgAUVAo/TZf4d8WxH0HhzZHCMMYI2bFJgy5bXkcnwAAgyBZMrmf4XrtqH0b6fNqlngDrieGCa0x5sI8mj15dKRirbsPXr1DljAb/GipapVIhIZ0y8PZIZ0qCQTag3rMf6iphc9xY0P+PJfYCqsKEgGH8kNXOYIG+VGBkdLOTXguWifE5SqgrlHqphJ2PyGhk1ZzbHpmnBmq4ULsEz3NeYXOYZnPMOy5jTNEU9d4DIXibLOhfHSOIrRtlHiyut92lPytxCAEMQt7vb+CpA/ZVqw==", "From": "dinesh.maniyam@altera.com", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Marek Vasut <marex@denx.de>,\n Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>,\n Tien Fong Chee <tien.fong.chee@altera.com>, Peng Fan <peng.fan@nxp.com>,\n Jaehoon Chung <jh80.chung@samsung.com>, Dinh Nguyen <dinguyen@kernel.org>,\n Svyatoslav Ryhel <clamor95@gmail.com>,\n Andre Przywara <andre.przywara@arm.com>,\n Frieder Schrempf <frieder.schrempf@kontron.de>,\n Johan Jonker <jbx6244@gmail.com>, Brian Sune <briansune@gmail.com>,\n Hai Pham <hai.pham.ud@renesas.com>,\n Parth Pancholi <parth.pancholi@toradex.com>,\n Emanuele Ghidoli <emanuele.ghidoli@toradex.com>,\n Chris-QJ Chen <chris-qj.chen@mediatek.com>,\n Paul Kocialkowski <contact@paulk.fr>, Alice Guo <alice.guo@nxp.com>,\n Dinesh Maniyam <dinesh.maniyam@altera.com>,\n Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>,\n Chen Huei Lok <chen.huei.lok@altera.com>,\n Kok Kiang <kok.kiang.hea@altera.com>, Boon Khai <boon.khai.ng@altera.com>", "Subject": "[PATCH] arm: dts: socfpga_arria10_socdk_sdmmc: migrate to OF_UPSTREAM", "Date": "Wed, 29 Apr 2026 13:32:20 +0800", "Message-ID": "\n <52fd49b46f43dce7be11c6e4e44d912c8c14e13c.1777440221.git.dinesh.maniyam@altera.com>", "X-Mailer": "git-send-email 2.43.7", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "BYAPR11CA0075.namprd11.prod.outlook.com\n (2603:10b6:a03:f4::16) To PH7PR03MB6942.namprd03.prod.outlook.com\n (2603:10b6:510:157::18)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "PH7PR03MB6942:EE_|DS7PR03MB8340:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b6079748-7fb6-4ef9-1239-08dea5b0bb50", "X-MS-Exchange-AtpMessageProperties": "SA", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|376014|1800799024|7416014|366016|13003099007|56012099003|18002099003|55112099003;", "X-Microsoft-Antispam-Message-Info": "\n XBajFDnw/45AsvLDUk6WcwJ0av9zopG3cXsDdgFNuH1e535k2fvhZWjKacehfdxIzvIea1uQPW1+dYTnJBGnhnykvcyjAcEHZ6l+zla89sCiJyUw0ShJJWFNJQtOndW+0AiXNqIfDvGh9U/PO/yzex0Qeyl9yMdtsSP0fcDAH6G5exoofXylxmMkt9x31MeKisWypn/+h/uTlSXSSGO0Kf/D0/PKR9tvSA3325BK2CINOOxyTX0DHiVmxJHjvbp1zjVarun/ty+Va1Po3EU5oYslJftrrS2a8zWMldPNB4BG7EjYEAhrQiRoTVTeFs5PqaVFM/wv2MXtgPCBRehM7AZz7UtphC8onl5g3rXZsd3F7gAT6Q43E67FeqiPVy3YkO6LKyjI6bmMXwo1YtQa4+4iVQ8krafaCT/4R1aMCtuZWdQKJMlzZUG8ja6o6pvuDg0gBAL9khJsisfz6Mqf0VFzgXnu9umtPxYjYrINuW6jd0ZsPfzCj20REZehDcx0H0/Mzh0ZVxR1zwTpQn3aphw2FFGD2MYjoPBF6SpiX56liRznMOjMQH+3ba4G7waxe6wum+t9zDh4KHsLA04O6i15spDPbfKKJpLtDtyw+A+xBNGwAg8axB9eb1IewKKl3OuHD5VCMH1e+S8iecU3oX0V6qUz0bdA3MLbWokURGsP8gEbKLObbTlpgl1N94ZI", "X-Forefront-Antispam-Report": "CIP:255.255.255.255; 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This\nkeeps U-Boot in sync with Linux and avoids drift between the two trees.\n\nUpdate CONFIG_DEFAULT_DEVICE_TREE to the upstream path\n\"intel/socfpga/socfpga_arria10_socdk_sdmmc\".\n\nRemove the now-obsolete device tree files:\n- arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts\n- arch/arm/dts/socfpga_arria10_socdk.dtsi\nand drop the corresponding entry from arch/arm/dts/Makefile.\n\nThe upstream socfpga_arria10.dtsi does not provide a label on the\n\"clkmgr@ffd04000\" node, so reference it via its full path in\nsocfpga_arria10-u-boot.dtsi to keep adding the bootph-all property.\n\narch/arm/dts/socfpga_arria10.dtsi is intentionally kept since it is\nstill consumed by the Chameleon V3 / Mercury AA1 device trees which\nhave not yet been migrated to OF_UPSTREAM.\n\nBuild tested with socfpga_arria10_defconfig (arm-none-eabi-).\n\nSigned-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com>\n---\n arch/arm/dts/Makefile | 1 -\n arch/arm/dts/socfpga_arria10-u-boot.dtsi | 2 +-\n arch/arm/dts/socfpga_arria10_socdk.dtsi | 178 -------------------\n arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 27 ---\n configs/socfpga_arria10_defconfig | 3 +-\n 5 files changed, 3 insertions(+), 208 deletions(-)\n delete mode 100644 arch/arm/dts/socfpga_arria10_socdk.dtsi\n delete mode 100644 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 4085d4c2de1..51c5b802269 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -446,7 +446,6 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=\t\t\t\t\\\n \tsocfpga_arria10_chameleonv3_270_2.dtb\t\t\\\n \tsocfpga_arria10_chameleonv3_270_3.dtb\t\t\\\n \tsocfpga_arria10_chameleonv3_480_2.dtb\t\t\\\n-\tsocfpga_arria10_socdk_sdmmc.dtb\t\t\t\\\n \tsocfpga_cyclone5_mcvevk.dtb\t\t\t\\\n \tsocfpga_cyclone5_is1.dtb\t\t\t\\\n \tsocfpga_cyclone5_socdk.dtb\t\t\t\\\ndiff --git a/arch/arm/dts/socfpga_arria10-u-boot.dtsi b/arch/arm/dts/socfpga_arria10-u-boot.dtsi\nindex 2ed532ffb54..c0ce337d72e 100644\n--- a/arch/arm/dts/socfpga_arria10-u-boot.dtsi\n+++ b/arch/arm/dts/socfpga_arria10-u-boot.dtsi\n@@ -18,7 +18,7 @@\n \t};\n };\n \n-&clkmgr {\n+&{/soc/clkmgr@ffd04000} {\n \tbootph-all;\n \n \tclocks {\ndiff --git a/arch/arm/dts/socfpga_arria10_socdk.dtsi b/arch/arm/dts/socfpga_arria10_socdk.dtsi\ndeleted file mode 100644\nindex 0efbeccc5cd..00000000000\n--- a/arch/arm/dts/socfpga_arria10_socdk.dtsi\n+++ /dev/null\n@@ -1,178 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright (C) 2015 Altera Corporation <www.altera.com>\n- */\n-#include \"socfpga_arria10.dtsi\"\n-\n-/ {\n-\tmodel = \"Altera SOCFPGA Arria 10\";\n-\tcompatible = \"altr,socfpga-arria10\", \"altr,socfpga\";\n-\n-\taliases {\n-\t\tethernet0 = &gmac0;\n-\t\tserial0 = &uart1;\n-\t};\n-\n-\tchosen {\n-\t\tbootargs = \"earlyprintk\";\n-\t\tstdout-path = \"serial0:115200n8\";\n-\t};\n-\n-\tmemory@0 {\n-\t\tname = \"memory\";\n-\t\tdevice_type = \"memory\";\n-\t\treg = <0x0 0x40000000>; /* 1GB */\n-\t};\n-\n-\ta10leds {\n-\t\tcompatible = \"gpio-leds\";\n-\n-\t\ta10sr_led0 {\n-\t\t\tlabel = \"a10sr-led0\";\n-\t\t\tgpios = <&a10sr_gpio 0 1>;\n-\t\t};\n-\n-\t\ta10sr_led1 {\n-\t\t\tlabel = \"a10sr-led1\";\n-\t\t\tgpios = <&a10sr_gpio 1 1>;\n-\t\t};\n-\n-\t\ta10sr_led2 {\n-\t\t\tlabel = \"a10sr-led2\";\n-\t\t\tgpios = <&a10sr_gpio 2 1>;\n-\t\t};\n-\n-\t\ta10sr_led3 {\n-\t\t\tlabel = \"a10sr-led3\";\n-\t\t\tgpios = <&a10sr_gpio 3 1>;\n-\t\t};\n-\t};\n-\n-\tref_033v: 033-v-ref {\n-\t\tcompatible = \"regulator-fixed\";\n-\t\tregulator-name = \"0.33V\";\n-\t\tregulator-min-microvolt = <330000>;\n-\t\tregulator-max-microvolt = <330000>;\n-\t};\n-\n-\tsoc {\n-\t\tclkmgr@ffd04000 {\n-\t\t\tclocks {\n-\t\t\t\tosc1 {\n-\t\t\t\t\tclock-frequency = <25000000>;\n-\t\t\t\t};\n-\t\t\t};\n-\t\t};\n-\t};\n-};\n-\n-&gmac0 {\n-\tphy-mode = \"rgmii\";\n-\tphy-addr = <0xffffffff>; /* probe for phy addr */\n-\n-\t/*\n-\t * These skews assume the user's FPGA design is adding 600ps of delay\n-\t * for TX_CLK on Arria 10.\n-\t *\n-\t * All skews are offset since hardware skew values for the ksz9031\n-\t * range from a negative skew to a positive skew.\n-\t * See the micrel-ksz90x1.txt Documentation file for details.\n-\t */\n-\ttxd0-skew-ps = <0>; /* -420ps */\n-\ttxd1-skew-ps = <0>; /* -420ps */\n-\ttxd2-skew-ps = <0>; /* -420ps */\n-\ttxd3-skew-ps = <0>; /* -420ps */\n-\trxd0-skew-ps = <420>; /* 0ps */\n-\trxd1-skew-ps = <420>; /* 0ps */\n-\trxd2-skew-ps = <420>; /* 0ps */\n-\trxd3-skew-ps = <420>; /* 0ps */\n-\ttxen-skew-ps = <0>; /* -420ps */\n-\ttxc-skew-ps = <1860>; /* 960ps */\n-\trxdv-skew-ps = <420>; /* 0ps */\n-\trxc-skew-ps = <1680>; /* 780ps */\n-\tmax-frame-size = <3800>;\n-\tstatus = \"okay\";\n-};\n-\n-&gpio1 {\n-\tstatus = \"okay\";\n-};\n-\n-&spi1 {\n-\tstatus = \"okay\";\n-\n-\tresource-manager@0 {\n-\t\tcompatible = \"altr,a10sr\";\n-\t\treg = <0>;\n-\t\tspi-max-frequency = <100000>;\n-\t\t/* low-level active IRQ at GPIO1_5 */\n-\t\tinterrupt-parent = <&portb>;\n-\t\tinterrupts = <5 IRQ_TYPE_LEVEL_LOW>;\n-\t\tinterrupt-controller;\n-\t\t#interrupt-cells = <2>;\n-\n-\t\ta10sr_gpio: gpio-controller {\n-\t\t\tcompatible = \"altr,a10sr-gpio\";\n-\t\t\tgpio-controller;\n-\t\t\t#gpio-cells = <2>;\n-\t\t};\n-\n-\t\ta10sr_rst: reset-controller {\n-\t\t\tcompatible = \"altr,a10sr-reset\";\n-\t\t\t#reset-cells = <1>;\n-\t\t};\n-\t};\n-};\n-\n-&i2c1 {\n-\tstatus = \"okay\";\n-\n-\t/*\n-\t * adjust the falling times to decrease the i2c frequency to 50Khz\n-\t * because the LCD module does not work at the standard 100Khz\n-\t */\n-\tclock-frequency = <100000>;\n-\ti2c-sda-falling-time-ns = <6000>;\n-\ti2c-scl-falling-time-ns = <6000>;\n-\n-\tadc@14 {\n-\t\tcompatible = \"lltc,ltc2497\";\n-\t\treg = <0x14>;\n-\t\tvref-supply = <&ref_033v>;\n-\t};\n-\n-\tadc@16 {\n-\t\tcompatible = \"lltc,ltc2497\";\n-\t\treg = <0x16>;\n-\t\tvref-supply = <&ref_033v>;\n-\t};\n-\n-\teeprom@51 {\n-\t\tcompatible = \"atmel,24c32\";\n-\t\treg = <0x51>;\n-\t\tpagesize = <32>;\n-\t};\n-\n-\trtc@68 {\n-\t\tcompatible = \"dallas,ds1339\";\n-\t\treg = <0x68>;\n-\t};\n-\n-\tltc@5c {\n-\t\tcompatible = \"ltc2977\";\n-\t\treg = <0x5c>;\n-\t};\n-};\n-\n-&uart1 {\n-\tstatus = \"okay\";\n-};\n-\n-&usb0 {\n-\tstatus = \"okay\";\n-\tdisable-over-current;\n-};\n-\n-&watchdog1 {\n-\tstatus = \"okay\";\n-};\ndiff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts\ndeleted file mode 100644\nindex 64dc0799f3d..00000000000\n--- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts\n+++ /dev/null\n@@ -1,27 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0+\n-/*\n- * Copyright (C) 2014-2015 Altera Corporation <www.altera.com>\n- */\n-\n-/dts-v1/;\n-#include \"socfpga_arria10_socdk.dtsi\"\n-\n-&mmc {\n-\tstatus = \"okay\";\n-\tcap-sd-highspeed;\n-\tcap-mmc-highspeed;\n-\tbroken-cd;\n-\tbus-width = <4>;\n-};\n-\n-&eccmgr {\n-\tsdmmca-ecc@ff8c2c00 {\n-\t\tcompatible = \"altr,socfpga-sdmmc-ecc\";\n-\t\treg = <0xff8c2c00 0x400>;\n-\t\taltr,ecc-parent = <&mmc>;\n-\t\tinterrupts = <15 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <47 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <16 IRQ_TYPE_LEVEL_HIGH>,\n-\t\t\t <48 IRQ_TYPE_LEVEL_HIGH>;\n-\t};\n-};\ndiff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig\nindex b32f40ae408..17169472462 100644\n--- a/configs/socfpga_arria10_defconfig\n+++ b/configs/socfpga_arria10_defconfig\n@@ -7,7 +7,7 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffe2b000\n CONFIG_ENV_SIZE=0x2000\n CONFIG_ENV_OFFSET=0x4400\n CONFIG_DM_GPIO=y\n-CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_socdk_sdmmc\"\n+CONFIG_DEFAULT_DEVICE_TREE=\"intel/socfpga/socfpga_arria10_socdk_sdmmc\"\n CONFIG_SPL_DRIVERS_MISC=y\n CONFIG_SPL_STACK=0xffe2b000\n CONFIG_SPL_TEXT_BASE=0xFFE00000\n@@ -46,6 +46,7 @@ CONFIG_CMD_USB=y\n CONFIG_CMD_CACHE=y\n CONFIG_CMD_EXT4_WRITE=y\n CONFIG_MTDIDS_DEFAULT=\"nor0=ff705000.spi.0\"\n+CONFIG_OF_UPSTREAM=y\n CONFIG_OF_SPL_REMOVE_PROPS=\"interrupts interrupt-parent dmas dma-names\"\n CONFIG_ENV_IS_IN_MMC=y\n CONFIG_ENV_RELOC_GD_ENV_ADDR=y\n", "prefixes": [] }