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GET /api/1.1/patches/2230032/?format=api
{ "id": 2230032, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230032/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-28-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-28-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:28", "name": "[PULL,27/51] target/riscv: Add cfg properties for Zvfbfa extensions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3def81a7feb7316c0c1b86fd6431a0c486d4b05e", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-28-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230032/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230032/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=J/RKSGC+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x631.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Max Chou <max.chou@sifive.com>\n\nThe Zvfbfa extension adds more complete BF16 vector compute support\nand requires the Zve32f and Zfbfmin extensions.\n\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\nMessage-ID: <20260402125234.1371897-2-max.chou@sifive.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n target/riscv/cpu.c | 1 +\n target/riscv/tcg/tcg-cpu.c | 8 ++++++++\n 3 files changed, 10 insertions(+)", "diff": "diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc\nindex d4b7c880d4..734fa079f2 100644\n--- a/target/riscv/cpu_cfg_fields.h.inc\n+++ b/target/riscv/cpu_cfg_fields.h.inc\n@@ -100,6 +100,7 @@ BOOL_FIELD(ext_zvks)\n BOOL_FIELD(ext_zvksc)\n BOOL_FIELD(ext_zvksg)\n BOOL_FIELD(ext_zmmul)\n+BOOL_FIELD(ext_zvfbfa)\n BOOL_FIELD(ext_zvfbfmin)\n BOOL_FIELD(ext_zvfbfwma)\n BOOL_FIELD(ext_zvfh)\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 03a1bb075a..7c652dea78 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -189,6 +189,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),\n ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),\n ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),\n+ ISA_EXT_DATA_ENTRY(zvfbfa, PRIV_VERSION_1_13_0, ext_zvfbfa),\n ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),\n ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),\n ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 3407191c22..c4f7da7193 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -720,6 +720,14 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n return;\n }\n \n+ if (cpu->cfg.ext_zvfbfa) {\n+ if (!cpu->cfg.ext_zve32f || !cpu->cfg.ext_zfbfmin) {\n+ error_setg(errp, \"Zvfbfa extension requires Zve32f extension \"\n+ \"and Zfbfmin extension\");\n+ return;\n+ }\n+ }\n+\n if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {\n error_setg(errp, \"Zdinx/Zhinx/Zhinxmin extensions require Zfinx\");\n return;\n", "prefixes": [ "PULL", "27/51" ] }