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GET /api/1.1/patches/2230029/?format=api
{ "id": 2230029, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230029/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-10-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-10-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:10", "name": "[PULL,09/51] target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fb18c9657f2eff62f272090825e13a9ebab8ed69", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-10-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230029/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230029/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=qkegiynv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::635;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x635.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Philippe Mathieu-Daudé <philmd@linaro.org>\n\nAll callers of gen_load_acquire() and gen_store_release() set both\nthe MO_ALIGN|MO_TE flags. Set them once in each callee.\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260318103122.97244-7-philmd@linaro.org>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 ++++++++++--------\n 1 file changed, 10 insertions(+), 8 deletions(-)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc\nindex 525f01ca34..2b1f73f650 100644\n--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc\n@@ -29,6 +29,7 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)\n return false;\n }\n \n+ memop |= MO_ALIGN | MO_TE;\n memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;\n \n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);\n@@ -43,26 +44,26 @@ static bool gen_load_acquire(DisasContext *ctx, arg_lb_aqrl *a, MemOp memop)\n static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_SB));\n+ return gen_load_acquire(ctx, a, MO_SB);\n }\n \n static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));\n+ return gen_load_acquire(ctx, a, MO_SW);\n }\n \n static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));\n+ return gen_load_acquire(ctx, a, MO_SL);\n }\n \n static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)\n {\n REQUIRE_64BIT(ctx);\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));\n+ return gen_load_acquire(ctx, a, MO_UQ);\n }\n \n static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)\n@@ -78,6 +79,7 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)\n return false;\n }\n \n+ memop |= MO_ALIGN | MO_TE;\n memop |= (ctx->cfg_ptr->ext_zama16b) ? MO_ATOM_WITHIN16 : 0;\n \n /* Add a memory barrier implied by RL (mandatory) and AQ (optional) */\n@@ -90,24 +92,24 @@ static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)\n static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_SB));\n+ return gen_store_release(ctx, a, MO_SB);\n }\n \n static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));\n+ return gen_store_release(ctx, a, MO_SW);\n }\n \n static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));\n+ return gen_store_release(ctx, a, MO_SL);\n }\n \n static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)\n {\n REQUIRE_64BIT(ctx);\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));\n+ return gen_store_release(ctx, a, MO_UQ);\n }\n", "prefixes": [ "PULL", "09/51" ] }