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GET /api/1.1/patches/2230025/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2230025,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230025/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-27-alistair.francis@wdc.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260429044752.4176397-27-alistair.francis@wdc.com>",
    "date": "2026-04-29T04:47:27",
    "name": "[PULL,26/51] target/riscv: preserve RV32 henvcfgh on henvcfg writes",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "b7ab9ecb9287179db25e7d2137254880e850daf0",
    "submitter": {
        "id": 64571,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api",
        "name": "Alistair Francis",
        "email": "alistair23@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-27-alistair.francis@wdc.com/mbox/",
    "series": [
        {
            "id": 501983,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983",
            "date": "2026-04-29T04:47:05",
            "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2230025/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2230025/checks/",
    "tags": {},
    "headers": {
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        "From": "alistair23@gmail.com",
        "X-Google-Original-From": "alistair.francis@wdc.com",
        "To": "palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org",
        "Cc": "alistair23@gmail.com, Bruno Sa <bruno.vilaca.sa@gmail.com>,\n Alistair Francis <alistair.francis@wdc.com>",
        "Subject": "[PULL 26/51] target/riscv: preserve RV32 henvcfgh on henvcfg writes",
        "Date": "Wed, 29 Apr 2026 14:47:27 +1000",
        "Message-ID": "<20260429044752.4176397-27-alistair.francis@wdc.com>",
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        "In-Reply-To": "<20260429044752.4176397-1-alistair.francis@wdc.com>",
        "References": "<20260429044752.4176397-1-alistair.francis@wdc.com>",
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    },
    "content": "From: Bruno Sa <bruno.vilaca.sa@gmail.com>\n\nOn RV32, STCE/ADUE/PBMTE/DTE are implemented in henvcfgh. A write to\nhenvcfg should therefore only update the low 32 bits of env->henvcfg.\n\nThe current write_henvcfg() path overwrites env->henvcfg with the\nlow-half value and clears any bits previously written via henvcfgh.\n\nPreserve the upper 32 bits on RV32 henvcfg writes and keep the existing\nRV64 behaviour unchanged.\n\nSigned-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260409155344.2849233-2-bruno.vilaca.sa@gmail.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/csr.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex a75281539b..cfd076b368 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -3353,7 +3353,15 @@ static RISCVException write_henvcfg(CPURISCVState *env, int csrno,\n         }\n     }\n \n-    env->henvcfg = val & mask;\n+    if (riscv_cpu_mxl(env) == MXL_RV32) {\n+        /*\n+         * RV32 stores STCE/ADUE/PBMTE/DTE in henvcfgh, so a low-half henvcfg\n+         * write must not clobber the upper 32 bits.\n+         */\n+        env->henvcfg = (env->henvcfg & ~0xFFFFFFFFULL) | (val & mask);\n+    } else {\n+        env->henvcfg = val & mask;\n+    }\n     if ((env->henvcfg & HENVCFG_DTE) == 0) {\n         env->vsstatus &= ~MSTATUS_SDT;\n     }\n",
    "prefixes": [
        "PULL",
        "26/51"
    ]
}