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GET /api/1.1/patches/2230014/?format=api
{ "id": 2230014, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230014/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-48-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-48-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:48", "name": "[PULL,47/51] target/riscv: Fix pointer masking PMM field selection logic", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "89cfd2f2f1ef3d589e79f63c7cfb32b14b872f5d", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-48-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230014/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230014/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=opzBG8Z+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x634.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Frank Chang <frank.chang@sifive.com>\n\nmstatus.MPV only records the previous virtualization state, and does not\naffect pointer masking according to the Zjpm specification.\n\nThis patch rewrites riscv_pm_get_pmm() to follow the architectural\ndefinition of Smmpm, Smnpm, and Ssnpm.\n\nThe resulting PMM selection logic for each mode is summarized below:\n\n * mstatus.MXR = 1: pointer masking disabled\n\n * Smmpm + Smnpm + Ssnpm:\n M-mode: mseccfg.PMM\n S-mode: menvcfg.PMM\n U-mode: senvcfg.PMM\n VS-mode: henvcfg.PMM\n VU-mode: senvcfg.PMM\n\n * Smmpm + Smnpm (RVS implemented):\n M-mode: mseccfg.PMM\n S-mode: menvcfg.PMM\n U/VS/VU: disabled (Ssnpm not present)\n\n * Smmpm + Smnpm (RVS not implemented):\n M-mode: mseccfg.PMM\n U-mode: menvcfg.PMM\n S/VS/VU: disabled (no S-mode)\n\n * Smmpm only:\n M-mode: mseccfg.PMM\n Other existing modes: pointer masking disabled\n\nSigned-off-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260421093715.2995067-4-frank.chang@sifive.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/cpu_helper.c | 51 +++++++++++++++++++++++++++++++++------\n 1 file changed, 44 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c\nindex 513bad21af..bab4153e53 100644\n--- a/target/riscv/cpu_helper.c\n+++ b/target/riscv/cpu_helper.c\n@@ -131,13 +131,47 @@ bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt)\n #endif\n }\n \n+/*\n+ * Returns the effective PMM field.\n+ *\n+ * @env: CPURISCVState\n+ *\n+ * The PMM field selection logic for each effective privilege mode\n+ * is as follows:\n+ *\n+ * - mstatus.MXR = 1: disabled\n+ *\n+ * - Smmpm + Smnpm + Ssnpm:\n+ * M-mode: mseccfg.PMM\n+ * S-mode: menvcfg.PMM\n+ * U-mode: senvcfg.PMM\n+ * VS-mode: henvcfg.PMM\n+ * VU-mode: senvcfg.PMM\n+ *\n+ * - Smmpm + Smnpm (RVS implemented):\n+ * M-mode: mseccfg.PMM\n+ * S-mode: menvcfg.PMM\n+ * U/VS/VU: disabled (Ssnpm not present)\n+ *\n+ * - Smmpm + Smnpm (RVS not implemented):\n+ * M-mode: mseccfg.PMM\n+ * U-mode: menvcfg.PMM\n+ * S/VS/VU: disabled (no S-mode)\n+ *\n+ * - Smmpm only:\n+ * M-mode: mseccfg.PMM\n+ * Other existing modes: disabled\n+ */\n RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n {\n #ifndef CONFIG_USER_ONLY\n- int priv_mode = cpu_address_mode(env);\n+ int priv_mode;\n+ bool virt;\n+\n+ riscv_cpu_eff_priv(env, &priv_mode, &virt);\n \n- if (get_field(env->mstatus, MSTATUS_MPRV) &&\n- get_field(env->mstatus, MSTATUS_MXR)) {\n+ if ((priv_mode != PRV_M && get_field(env->mstatus, MSTATUS_MXR)) ||\n+ (virt && get_field(env->vsstatus, MSTATUS_MXR))) {\n return PMM_FIELD_DISABLED;\n }\n \n@@ -149,12 +183,14 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n }\n break;\n case PRV_S:\n- if (riscv_cpu_cfg(env)->ext_smnpm) {\n- if (get_field(env->mstatus, MSTATUS_MPV)) {\n- return get_field(env->henvcfg, HENVCFG_PMM);\n- } else {\n+ if (!virt) {\n+ if (riscv_cpu_cfg(env)->ext_smnpm) {\n return get_field(env->menvcfg, MENVCFG_PMM);\n }\n+ } else {\n+ if (riscv_cpu_cfg(env)->ext_ssnpm) {\n+ return get_field(env->henvcfg, HENVCFG_PMM);\n+ }\n }\n break;\n case PRV_U:\n@@ -171,6 +207,7 @@ RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env)\n default:\n g_assert_not_reached();\n }\n+\n return PMM_FIELD_DISABLED;\n #else\n return PMM_FIELD_DISABLED;\n", "prefixes": [ "PULL", "47/51" ] }