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GET /api/1.1/patches/2230011/?format=api
{ "id": 2230011, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230011/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-37-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-37-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:37", "name": "[PULL,36/51] target/riscv: rvv: Allow fractional LMUL on vector SHA instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "59ef60f9b5d4910cb3c206f1eeda36b603ab3e09", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-37-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230011/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230011/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=GMV8BAXx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pg1-x535.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Anton Blanchard <antonb@tenstorrent.com>\n\nVector SHA instructions incorrectly raise an illegal instruction exception\nwhen LMUL < 1. The ISA only states that LMUL*VLEN >= EGW:\n\n For element-group instructions, LMUL*VLEN must always be at least as\n large as EGW, otherwise an illegal-instruction exception is raised, even\n if vl=0.\n\nThere is already a check for this:\n\n MAXSZ(s) >= egw_bytes\n\nso just remove the check for a fractional LMUL.\n\nSigned-off-by: Anton Blanchard <antonb@tenstorrent.com>\nReviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\nMessage-ID: <20260104233724.192886-1-antonb@tenstorrent.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/insn_trans/trans_rvvk.c.inc | 3 +--\n 1 file changed, 1 insertion(+), 2 deletions(-)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvvk.c.inc b/target/riscv/insn_trans/trans_rvvk.c.inc\nindex 27bf3f0b68..32255d3aa0 100644\n--- a/target/riscv/insn_trans/trans_rvvk.c.inc\n+++ b/target/riscv/insn_trans/trans_rvvk.c.inc\n@@ -426,8 +426,7 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a)\n vsha_check_sew(s) &&\n MAXSZ(s) >= egw_bytes &&\n !is_overlapped(a->rd, mult, a->rs1, mult) &&\n- !is_overlapped(a->rd, mult, a->rs2, mult) &&\n- s->lmul >= 0;\n+ !is_overlapped(a->rd, mult, a->rs2, mult);\n }\n \n GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check, ZVKNH_EGS)\n", "prefixes": [ "PULL", "36/51" ] }