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GET /api/1.1/patches/2230007/?format=api
{ "id": 2230007, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230007/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-44-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-44-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:44", "name": "[PULL,43/51] target/riscv: Don't OR mip.SEIP when mvien is one", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5571f5b95c4657f92652b33b40a16a349182ca73", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-44-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230007/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230007/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=PwOtenrh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::631;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x631.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Alistair Francis <alistair.francis@wdc.com>\n\nThe RISC-V spec states that\n\n\"\"\"\nBut when bit 9 of mvien is one, bit SEIP in mip is read-only and does\nnot include the value of bit 9 of mvip. Rather, the value of mip.SEIP\nis simply the supervisor external interrupt signal from the hart’s\nexternal interrupt controller (APLIC or IMSIC).\n\"\"\"\n\nAs such let's mark the mip.SEIP in rmw_mip64().\n\nCc: qemu-stable@nongnu.org\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/2828\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nMessage-ID: <20260415233740.3027321-4-alistair.francis@wdc.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/csr.c | 8 ++++++++\n 1 file changed, 8 insertions(+)", "diff": "diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex 80727aa81e..da366cf562 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -3728,6 +3728,14 @@ static RISCVException rmw_mip64(CPURISCVState *env, int csrno,\n uint64_t old_mip, mask = wr_mask & delegable_ints;\n uint32_t gin;\n \n+ /*\n+ * When mvien[9]=1, mip.SEIP is read-only and reflects only\n+ * the external interrupt signal from the interrupt controller.\n+ */\n+ if (env->mvien & MIP_SEIP) {\n+ mask &= ~MIP_SEIP;\n+ }\n+\n if (mask & MIP_SEIP) {\n env->software_seip = new_val & MIP_SEIP;\n new_val |= env->external_seip * MIP_SEIP;\n", "prefixes": [ "PULL", "43/51" ] }