Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2230006/?format=api
{ "id": 2230006, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230006/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-40-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-40-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:40", "name": "[PULL,39/51] target/riscv: fix RV32 stateen CSR handling", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8a70770cf9c670ae2b7e18ff3775bf329d2a7891", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-40-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230006/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230006/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=nWpBmHzE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g54fS4S60z1xqf\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 14:52:16 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHwte-0008HE-Tk; Wed, 29 Apr 2026 00:51:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwtX-0007pF-SJ\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:51:35 -0400", "from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwtV-0000zY-Mp\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:51:31 -0400", "by mail-pl1-x62c.google.com with SMTP id\n d9443c01a7336-2ad9f316d68so53647335ad.2\n for <qemu-devel@nongnu.org>; Tue, 28 Apr 2026 21:51:27 -0700 (PDT)", "from toolbx.alistair23.me ([2403:581e:fdf9:0:6209:4521:6813:45b7])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b988772ae8sm7756145ad.7.2026.04.28.21.51.22\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 28 Apr 2026 21:51:26 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777438287; x=1778043087; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=YPyTNiL1ojeRuEHyY4Guho9lr/cm4Zx8gYkYg9AMqhc=;\n b=nWpBmHzEXyxAWOV8EgwOAx2LLyc7qmAQjoKM2r6AKxyN9In9udZ0zdO7tqOkzr1ric\n oKcDGt+4UE1ECQ4wcgNLf4GeW9DqEEPoJEd/tAIZqUyoRIWTABYpOBFmATtHGRQi1F7Q\n N1JQ89AU0IfJdP0SdWkh+7bsYDKQ2GbWMydifg74nWnmOsOn8RKwBFLgMb6d2Hxp5AWn\n 2DNlguFZcB9BsQgPVs1xu01P1BBu3I0L4o2HGeLiGaj41/IA+tFehmvRvV46txuu73+5\n m7UI+WO9X8MdS50mHzCmx3TU0Ae5+0T6VPFvlee18OfMaSQYYwLF9ilqBT7c185goLv2\n fXaQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777438287; x=1778043087;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=YPyTNiL1ojeRuEHyY4Guho9lr/cm4Zx8gYkYg9AMqhc=;\n b=MP8CK+25rhgh/WXfEjr81Ef9f3LdbERGZvhpCqUwEpABVut/jXI3nSEXi8GHa8rd0t\n scZfFp9AfzIrIjgAehl0sQgatM6nZN921iD7UFLK/KPf7u5syzq96COqsZa/t/0aE/2j\n aM3EU90EfibKU3l7L+BTYUR8xmkO3YtHA0YbTDqHOEAF1ZDvPyl5lD7ZyxnvfJKzEda3\n +n3/AmHubmI9QLGvvj89+BXfFO+dswrnNu09c2P1BUxevHUI9/Dq5LPJt83dpc/GzC3N\n 5o+jj/bpC9m0/7S4DqaxtidQ14lNMNb8mFrtQIJyQv48mRHQbrGVf5wXv/E/L3fRVYmJ\n kx6Q==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ/nD493LjCiS9KI2V9iyH9kRPmFflr+14coAE2aSRpj0gUeRT85D7i0TS4GAfo7Got9tNC0fNJej+Qv@nongnu.org", "X-Gm-Message-State": "AOJu0YwrnpPZZMpr6vwbzROq2yajVDNQTmWMuPp4cPzU2ZUrmNwx42pH\n uAk8t+waUk06brbPfPwwzRznU5rJOe5xoJJ26t3NmpJvTCaBE3CKXv9/", "X-Gm-Gg": "AeBDiesQcr9cvc875aLtCyLeAxP2Z0l29T2J1NNzo8DisaKZL9gDqfIwzdZSO3RYQml\n y1210U5Qed5TC8l2Vec9uAtV4Y9nNDtLwe4GV2Ep8DAMOxI+nWYfoII3OoJy+DyPZIDVxs4vQJm\n SHgLoTdsAUYd9v3WLMtNK+AcbANifsVMgvSVOlgT/cfVzyvkWcJX+Yy2qJwXRbjJIAv1gua8vE+\n 2nzYSgyq8Jon8fe+R5hFNayovNsTkcnrEUwQPy47rkmRkbSPmwPZmEVxisgd6UInA64ZjlugIPH\n UytC8uW+IrqEVw0PakibWl07d6aCS0ipoErrMuVQbsgcbUId7hdh9FHXPGSo+JP2093AGkh6i6T\n w6RE8yqRR/meZ46Kq4MfMYsKOxjJau5cBOtWedxlBGXLHusovTPgGTDSGyjfkrJCqLqbTaB0KtS\n KJPnLAeC7MLr23M7BBSEosRaXu90vpk6MCfuEApjRGMoBtoHUXNJOZ", "X-Received": "by 2002:a17:903:1a2b:b0:2b0:9101:1b77 with SMTP id\n d9443c01a7336-2b987391b1bmr23101075ad.17.1777438286621;\n Tue, 28 Apr 2026 21:51:26 -0700 (PDT)", "From": "alistair23@gmail.com", "X-Google-Original-From": "alistair.francis@wdc.com", "To": "palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org", "Cc": "alistair23@gmail.com, Bruno Sa <bruno.vilaca.sa@gmail.com>,\n Alistair Francis <alistair.francis@wdc.com>", "Subject": "[PULL 39/51] target/riscv: fix RV32 stateen CSR handling", "Date": "Wed, 29 Apr 2026 14:47:40 +1000", "Message-ID": "<20260429044752.4176397-40-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "References": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62c;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x62c.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Bruno Sa <bruno.vilaca.sa@gmail.com>\n\nThe RV32 stateen CSRs are split between the low-half CSR and the\ncorresponding xH CSR, but the current implementation still handles some\nupper-half bits through the low-half write paths and also accepts the\nxH CSRs on RV64.\n\nFix this by:\n- rejecting mstateen*h and hstateen*h accesses on RV64\n- keeping the RV64-only writable bits in the low-half write paths\n- handling the RV32 upper-half writable bits in write_mstateen0h() and\n write_hstateen0h()\n- dropping unsupported writable bits from write_sstateen0()\n\nSigned-off-by: Bruno Sa <bruno.vilaca.sa@gmail.com>\nMessage-ID: <20260410110928.1014170-1-bruno.vilaca.sa@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/csr.c | 117 ++++++++++++++++++++++++++++++++-------------\n 1 file changed, 83 insertions(+), 34 deletions(-)", "diff": "diff --git a/target/riscv/csr.c b/target/riscv/csr.c\nindex cfd076b368..80727aa81e 100644\n--- a/target/riscv/csr.c\n+++ b/target/riscv/csr.c\n@@ -502,6 +502,15 @@ static RISCVException mstateen(CPURISCVState *env, int csrno)\n return any(env, csrno);\n }\n \n+static RISCVException mstateen_32(CPURISCVState *env, int csrno)\n+{\n+ if (riscv_cpu_mxl(env) != MXL_RV32) {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+\n+ return mstateen(env, csrno);\n+}\n+\n static RISCVException hstateen_pred(CPURISCVState *env, int csrno, int base)\n {\n if (!riscv_cpu_cfg(env)->ext_smstateen) {\n@@ -533,6 +542,10 @@ static RISCVException hstateen(CPURISCVState *env, int csrno)\n \n static RISCVException hstateenh(CPURISCVState *env, int csrno)\n {\n+ if (riscv_cpu_mxl(env) != MXL_RV32) {\n+ return RISCV_EXCP_ILLEGAL_INST;\n+ }\n+\n return hstateen_pred(env, csrno, CSR_HSTATEEN0H);\n }\n \n@@ -3447,25 +3460,29 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,\n wr_mask |= SMSTATEEN0_FCSR;\n }\n \n- if (env->priv_ver >= PRIV_VERSION_1_13_0) {\n- wr_mask |= SMSTATEEN0_P1P13;\n- }\n+ if (riscv_cpu_mxl(env) == MXL_RV64) {\n+ if (env->priv_ver >= PRIV_VERSION_1_13_0) {\n+ wr_mask |= SMSTATEEN0_P1P13;\n+ }\n \n- if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) {\n- wr_mask |= SMSTATEEN0_SVSLCT;\n- }\n+ if (riscv_cpu_cfg(env)->ext_smaia ||\n+ riscv_cpu_cfg(env)->ext_smcsrind) {\n+ wr_mask |= SMSTATEEN0_SVSLCT;\n+ }\n \n- /*\n- * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is\n- * implemented. However, that information is with MachineState and we can't\n- * figure that out in csr.c. Just enable if Smaia is available.\n- */\n- if (riscv_cpu_cfg(env)->ext_smaia) {\n- wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n- }\n+ /*\n+ * As per the AIA specification, SMSTATEEN0_IMSIC is valid\n+ * only if IMSIC is implemented. However, that information is\n+ * with MachineState and we can't figure that out in csr.c.\n+ * Just enable if Smaia is available.\n+ */\n+ if (riscv_cpu_cfg(env)->ext_smaia) {\n+ wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n+ }\n \n- if (riscv_cpu_cfg(env)->ext_ssctr) {\n- wr_mask |= SMSTATEEN0_CTR;\n+ if (riscv_cpu_cfg(env)->ext_ssctr) {\n+ wr_mask |= SMSTATEEN0_CTR;\n+ }\n }\n \n return write_mstateen(env, csrno, wr_mask, new_val);\n@@ -3507,6 +3524,20 @@ static RISCVException write_mstateen0h(CPURISCVState *env, int csrno,\n wr_mask |= SMSTATEEN0_P1P13;\n }\n \n+ if (riscv_cpu_cfg(env)->ext_smaia || riscv_cpu_cfg(env)->ext_smcsrind) {\n+ wr_mask |= SMSTATEEN0_SVSLCT;\n+ }\n+\n+ /*\n+ * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if\n+ * IMSIC is implemented. However, that information is with\n+ * MachineState and we can't figure that out in csr.c. Just enable\n+ * if Smaia is available.\n+ */\n+ if (riscv_cpu_cfg(env)->ext_smaia) {\n+ wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n+ }\n+\n if (riscv_cpu_cfg(env)->ext_ssctr) {\n wr_mask |= SMSTATEEN0_CTR;\n }\n@@ -3552,21 +3583,25 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,\n wr_mask |= SMSTATEEN0_FCSR;\n }\n \n- if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) {\n- wr_mask |= SMSTATEEN0_SVSLCT;\n- }\n+ if (riscv_cpu_mxl(env) == MXL_RV64) {\n+ if (riscv_cpu_cfg(env)->ext_ssaia ||\n+ riscv_cpu_cfg(env)->ext_sscsrind) {\n+ wr_mask |= SMSTATEEN0_SVSLCT;\n+ }\n \n- /*\n- * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if IMSIC is\n- * implemented. However, that information is with MachineState and we can't\n- * figure that out in csr.c. Just enable if Ssaia is available.\n- */\n- if (riscv_cpu_cfg(env)->ext_ssaia) {\n- wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n- }\n+ /*\n+ * As per the AIA specification, SMSTATEEN0_IMSIC is valid\n+ * only if IMSIC is implemented. However, that information is\n+ * with MachineState and we can't figure that out in csr.c.\n+ * Just enable if Ssaia is available.\n+ */\n+ if (riscv_cpu_cfg(env)->ext_ssaia) {\n+ wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n+ }\n \n- if (riscv_cpu_cfg(env)->ext_ssctr) {\n- wr_mask |= SMSTATEEN0_CTR;\n+ if (riscv_cpu_cfg(env)->ext_ssctr) {\n+ wr_mask |= SMSTATEEN0_CTR;\n+ }\n }\n \n return write_hstateen(env, csrno, wr_mask, new_val);\n@@ -3608,6 +3643,20 @@ static RISCVException write_hstateen0h(CPURISCVState *env, int csrno,\n {\n uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;\n \n+ if (riscv_cpu_cfg(env)->ext_ssaia || riscv_cpu_cfg(env)->ext_sscsrind) {\n+ wr_mask |= SMSTATEEN0_SVSLCT;\n+ }\n+\n+ /*\n+ * As per the AIA specification, SMSTATEEN0_IMSIC is valid only if\n+ * IMSIC is implemented. However, that information is with\n+ * MachineState and we can't figure that out in csr.c. Just enable\n+ * if Ssaia is available.\n+ */\n+ if (riscv_cpu_cfg(env)->ext_ssaia) {\n+ wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC);\n+ }\n+\n if (riscv_cpu_cfg(env)->ext_ssctr) {\n wr_mask |= SMSTATEEN0_CTR;\n }\n@@ -3657,7 +3706,7 @@ static RISCVException write_sstateen(CPURISCVState *env, int csrno,\n static RISCVException write_sstateen0(CPURISCVState *env, int csrno,\n target_ulong new_val, uintptr_t ra)\n {\n- uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;\n+ uint64_t wr_mask = 0;\n \n if (!riscv_has_ext(env, RVF)) {\n wr_mask |= SMSTATEEN0_FCSR;\n@@ -5937,25 +5986,25 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {\n /* Smstateen extension CSRs */\n [CSR_MSTATEEN0] = { \"mstateen0\", mstateen, read_mstateen, write_mstateen0,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n- [CSR_MSTATEEN0H] = { \"mstateen0h\", mstateen, read_mstateenh,\n+ [CSR_MSTATEEN0H] = { \"mstateen0h\", mstateen_32, read_mstateenh,\n write_mstateen0h,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n [CSR_MSTATEEN1] = { \"mstateen1\", mstateen, read_mstateen,\n write_mstateen_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n- [CSR_MSTATEEN1H] = { \"mstateen1h\", mstateen, read_mstateenh,\n+ [CSR_MSTATEEN1H] = { \"mstateen1h\", mstateen_32, read_mstateenh,\n write_mstateenh_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n [CSR_MSTATEEN2] = { \"mstateen2\", mstateen, read_mstateen,\n write_mstateen_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n- [CSR_MSTATEEN2H] = { \"mstateen2h\", mstateen, read_mstateenh,\n+ [CSR_MSTATEEN2H] = { \"mstateen2h\", mstateen_32, read_mstateenh,\n write_mstateenh_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n [CSR_MSTATEEN3] = { \"mstateen3\", mstateen, read_mstateen,\n write_mstateen_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n- [CSR_MSTATEEN3H] = { \"mstateen3h\", mstateen, read_mstateenh,\n+ [CSR_MSTATEEN3H] = { \"mstateen3h\", mstateen_32, read_mstateenh,\n write_mstateenh_1_3,\n .min_priv_ver = PRIV_VERSION_1_12_0 },\n [CSR_HSTATEEN0] = { \"hstateen0\", hstateen, read_hstateen, write_hstateen0,\n", "prefixes": [ "PULL", "39/51" ] }