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GET /api/1.1/patches/2230002/?format=api
{ "id": 2230002, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230002/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-30-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-30-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:30", "name": "[PULL,29/51] target/riscv: rvv: Add new VTYPE CSR field - altfmt", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "978eb505bd9c7e26a8bd5453057100afab1f65de", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-30-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230002/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230002/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ewBP4u3e;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x632.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Max Chou <max.chou@sifive.com>\n\nAccording to the Zvfbfa ISA spec v0.1, the vtype CSR adds a new field:\naltfmt for BF16 support.\nThis update changes the layout of the vtype CSR fields.\n\n- Removed VEDIV field (bits 8-9) since EDIV extension is not planned to\n be part of the base V extension\n- Added ALTFMT field at bit 8\n- Changed RESERVED field to start from bit 9 instead of bit 10\n\nWhen Zvfbfa is disabled, bits 8+ are treated as reserved (preserving\nexisting behavior for altfmt bit). When Zvfbfa is enabled, only bits 9+\nare reserved.\n\nReference:\n- https://github.com/riscvarchive/riscv-v-spec/blob/master/ediv.adoc\n\nReviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nSigned-off-by: Max Chou <max.chou@sifive.com>\nMessage-ID: <20260402125234.1371897-4-max.chou@sifive.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/cpu.h | 4 ++--\n target/riscv/vector_helper.c | 39 +++++++++++++++++++++++++++++++-----\n 2 files changed, 36 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 35d1f6362c..962cc45073 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -191,8 +191,8 @@ FIELD(VTYPE, VLMUL, 0, 3)\n FIELD(VTYPE, VSEW, 3, 3)\n FIELD(VTYPE, VTA, 6, 1)\n FIELD(VTYPE, VMA, 7, 1)\n-FIELD(VTYPE, VEDIV, 8, 2)\n-FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11)\n+FIELD(VTYPE, ALTFMT, 8, 1)\n+FIELD(VTYPE, RESERVED, 9, sizeof(target_ulong) * 8 - 10)\n \n typedef struct PMUCTRState {\n /* Current value of a counter */\ndiff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c\nindex 83dd26314d..63ca6fe16b 100644\n--- a/target/riscv/vector_helper.c\n+++ b/target/riscv/vector_helper.c\n@@ -33,6 +33,22 @@\n #include \"vector_internals.h\"\n #include <math.h>\n \n+static target_ulong vtype_reserved(CPURISCVState *env, target_ulong vtype)\n+{\n+ int xlen = riscv_cpu_xlen(env);\n+ target_ulong reserved = 0;\n+\n+ if (riscv_cpu_cfg(env)->ext_zvfbfa) {\n+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n+ xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n+ } else {\n+ reserved = vtype & MAKE_64BIT_MASK(R_VTYPE_ALTFMT_SHIFT,\n+ xlen - 1 - R_VTYPE_ALTFMT_SHIFT);\n+ }\n+\n+ return reserved;\n+}\n+\n target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n target_ulong s2, target_ulong x0)\n {\n@@ -41,12 +57,10 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n uint64_t vlmul = FIELD_EX64(s2, VTYPE, VLMUL);\n uint8_t vsew = FIELD_EX64(s2, VTYPE, VSEW);\n uint16_t sew = 8 << vsew;\n- uint8_t ediv = FIELD_EX64(s2, VTYPE, VEDIV);\n+ uint8_t altfmt = FIELD_EX64(s2, VTYPE, ALTFMT);\n+ bool ill_altfmt = true;\n int xlen = riscv_cpu_xlen(env);\n bool vill = (s2 >> (xlen - 1)) & 0x1;\n- target_ulong reserved = s2 &\n- MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,\n- xlen - 1 - R_VTYPE_RESERVED_SHIFT);\n uint16_t vlen = cpu->cfg.vlenb << 3;\n int8_t lmul;\n \n@@ -63,7 +77,22 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,\n }\n }\n \n- if ((sew > cpu->cfg.elen) || vill || (ediv != 0) || (reserved != 0)) {\n+ switch (vsew) {\n+ case MO_8:\n+ ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n+ break;\n+ case MO_16:\n+ ill_altfmt &= !(cpu->cfg.ext_zvfbfa);\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ if (altfmt && ill_altfmt) {\n+ vill = true;\n+ }\n+\n+ if ((sew > cpu->cfg.elen) || vill || (vtype_reserved(env, s2) != 0)) {\n /* only set vill bit. */\n env->vill = 1;\n env->vtype = 0;\n", "prefixes": [ "PULL", "29/51" ] }