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GET /api/1.1/patches/2230000/?format=api
{ "id": 2230000, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2230000/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-9-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-9-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:09", "name": "[PULL,08/51] target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again)", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9764b1a488f44d6787c3547e87147dd920e5e090", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-9-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2230000/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2230000/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com 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"<20260429044752.4176397-1-alistair.francis@wdc.com>", "References": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::630;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x630.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Philippe Mathieu-Daudé <philmd@linaro.org>\n\nFollowing commit 73ae67fd4e6, extract the implicit MO_TE\ndefinition in order to replace it.\n\nMechanical change using:\n\n $ for n in UW UL UQ UO SW SL SQ; do \\\n sed -i -e \"s/MO_TE$n/MO_TE | MO_$n/\" \\\n $(git grep -l MO_TE$n target/riscv); \\\n done\n\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260318103122.97244-6-philmd@linaro.org>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/insn_trans/trans_rvzalasr.c.inc | 12 ++++++------\n target/riscv/insn_trans/trans_xmips.c.inc | 16 ++++++++--------\n target/riscv/insn_trans/trans_zilsd.c.inc | 4 ++--\n 3 files changed, 16 insertions(+), 16 deletions(-)", "diff": "diff --git a/target/riscv/insn_trans/trans_rvzalasr.c.inc b/target/riscv/insn_trans/trans_rvzalasr.c.inc\nindex bf86805cef..525f01ca34 100644\n--- a/target/riscv/insn_trans/trans_rvzalasr.c.inc\n+++ b/target/riscv/insn_trans/trans_rvzalasr.c.inc\n@@ -49,20 +49,20 @@ static bool trans_lb_aqrl(DisasContext *ctx, arg_lb_aqrl *a)\n static bool trans_lh_aqrl(DisasContext *ctx, arg_lh_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESW));\n+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SW));\n }\n \n static bool trans_lw_aqrl(DisasContext *ctx, arg_lw_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TESL));\n+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_SL));\n }\n \n static bool trans_ld_aqrl(DisasContext *ctx, arg_ld_aqrl *a)\n {\n REQUIRE_64BIT(ctx);\n REQUIRE_ZALASR(ctx);\n- return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TEUQ));\n+ return gen_load_acquire(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));\n }\n \n static bool gen_store_release(DisasContext *ctx, arg_sb_aqrl *a, MemOp memop)\n@@ -96,18 +96,18 @@ static bool trans_sb_aqrl(DisasContext *ctx, arg_sb_aqrl *a)\n static bool trans_sh_aqrl(DisasContext *ctx, arg_sh_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESW));\n+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SW));\n }\n \n static bool trans_sw_aqrl(DisasContext *ctx, arg_sw_aqrl *a)\n {\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TESL));\n+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_SL));\n }\n \n static bool trans_sd_aqrl(DisasContext *ctx, arg_sd_aqrl *a)\n {\n REQUIRE_64BIT(ctx);\n REQUIRE_ZALASR(ctx);\n- return gen_store_release(ctx, a, (MO_ALIGN | MO_TEUQ));\n+ return gen_store_release(ctx, a, (MO_ALIGN | MO_TE | MO_UQ));\n }\ndiff --git a/target/riscv/insn_trans/trans_xmips.c.inc b/target/riscv/insn_trans/trans_xmips.c.inc\nindex 9a72f3392f..37572563ae 100644\n--- a/target/riscv/insn_trans/trans_xmips.c.inc\n+++ b/target/riscv/insn_trans/trans_xmips.c.inc\n@@ -56,11 +56,11 @@ static bool trans_ldp(DisasContext *ctx, arg_ldp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_y);\n- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESQ);\n+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SQ);\n gen_set_gpr(ctx, a->rd, dest0);\n \n tcg_gen_addi_tl(addr, addr, 8);\n- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESQ);\n+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SQ);\n gen_set_gpr(ctx, a->rs3, dest1);\n \n return true;\n@@ -77,11 +77,11 @@ static bool trans_lwp(DisasContext *ctx, arg_lwp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_x);\n- tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TESL);\n+ tcg_gen_qemu_ld_tl(dest0, addr, ctx->mem_idx, MO_TE | MO_SL);\n gen_set_gpr(ctx, a->rd, dest0);\n \n tcg_gen_addi_tl(addr, addr, 4);\n- tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TESL);\n+ tcg_gen_qemu_ld_tl(dest1, addr, ctx->mem_idx, MO_TE | MO_SL);\n gen_set_gpr(ctx, a->rs3, dest1);\n \n return true;\n@@ -99,10 +99,10 @@ static bool trans_sdp(DisasContext *ctx, arg_sdp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_w);\n- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TEUQ);\n+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_UQ);\n \n tcg_gen_addi_tl(addr, addr, 8);\n- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TEUQ);\n+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_UQ);\n \n return true;\n }\n@@ -118,10 +118,10 @@ static bool trans_swp(DisasContext *ctx, arg_swp *a)\n TCGv addr = tcg_temp_new();\n \n tcg_gen_addi_tl(addr, src, a->imm_v);\n- tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TESL);\n+ tcg_gen_qemu_st_tl(data0, addr, ctx->mem_idx, MO_TE | MO_SL);\n \n tcg_gen_addi_tl(addr, addr, 4);\n- tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TESL);\n+ tcg_gen_qemu_st_tl(data1, addr, ctx->mem_idx, MO_TE | MO_SL);\n \n return true;\n }\ndiff --git a/target/riscv/insn_trans/trans_zilsd.c.inc b/target/riscv/insn_trans/trans_zilsd.c.inc\nindex 369c33004b..445406cf01 100644\n--- a/target/riscv/insn_trans/trans_zilsd.c.inc\n+++ b/target/riscv/insn_trans/trans_zilsd.c.inc\n@@ -30,7 +30,7 @@ static bool gen_load_i64(DisasContext *ctx, arg_ld *a)\n TCGv addr = get_address(ctx, a->rs1, a->imm);\n TCGv_i64 tmp = tcg_temp_new_i64();\n \n- tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TESQ);\n+ tcg_gen_qemu_ld_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);\n \n if (a->rd == 0) {\n return true;\n@@ -85,7 +85,7 @@ static bool gen_store_i64(DisasContext *ctx, arg_sd *a)\n } else {\n tcg_gen_concat_tl_i64(tmp, data_low, data_high);\n }\n- tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TESQ);\n+ tcg_gen_qemu_st_i64(tmp, addr, ctx->mem_idx, MO_TE | MO_SQ);\n \n return true;\n }\n", "prefixes": [ "PULL", "08/51" ] }