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GET /api/1.1/patches/2229999/?format=api
{ "id": 2229999, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229999/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-25-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-25-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:25", "name": "[PULL,24/51] hw/intc: fix heap OOB in ACLINT MTIMER multi-socket", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "36c3c56495b3a4c1a6ec6919bea31d0723bb18c0", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-25-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229999/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229999/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rmD0JejQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62e;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x62e.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Sebastián Alba Vives <sebasjosue84@gmail.com>\n\nThe MMIO read/write handlers index timecmp[] with the absolute hartid\n(hartid_base + offset) but the array is allocated with num_harts\nelements. In multi-socket configurations with hartid_base > 0 this\ncauses heap OOB access in the QEMU process.\n\nFix by using the relative offset for array indexing.\n\nCc: qemu-security@nongnu.org\nSigned-off-by: Sebastián Alba Vives <sebasjosue84@gmail.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260401053853.10473-2-sebasjosue84@gmail.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n hw/intc/riscv_aclint.c | 10 ++++++----\n 1 file changed, 6 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c\nindex 9c1491bd04..e27e5fb394 100644\n--- a/hw/intc/riscv_aclint.c\n+++ b/hw/intc/riscv_aclint.c\n@@ -131,6 +131,7 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,\n addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {\n size_t hartid = mtimer->hartid_base +\n ((addr - mtimer->timecmp_base) >> 3);\n+ size_t hartid_offset = hartid - mtimer->hartid_base;\n CPUState *cpu = cpu_by_arch_id(hartid);\n CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;\n if (!env) {\n@@ -138,11 +139,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, hwaddr addr,\n \"aclint-mtimer: invalid hartid: %zu\", hartid);\n } else if ((addr & 0x7) == 0) {\n /* timecmp_lo for RV32/RV64 or timecmp for RV64 */\n- uint64_t timecmp = mtimer->timecmp[hartid];\n+ uint64_t timecmp = mtimer->timecmp[hartid_offset];\n return (size == 4) ? (timecmp & 0xFFFFFFFF) : timecmp;\n } else if ((addr & 0x7) == 4) {\n /* timecmp_hi */\n- uint64_t timecmp = mtimer->timecmp[hartid];\n+ uint64_t timecmp = mtimer->timecmp[hartid_offset];\n return (timecmp >> 32) & 0xFFFFFFFF;\n } else {\n qemu_log_mask(LOG_UNIMP,\n@@ -174,6 +175,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,\n addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) {\n size_t hartid = mtimer->hartid_base +\n ((addr - mtimer->timecmp_base) >> 3);\n+ size_t hartid_offset = hartid - mtimer->hartid_base;\n CPUState *cpu = cpu_by_arch_id(hartid);\n CPURISCVState *env = cpu ? cpu_env(cpu) : NULL;\n if (!env) {\n@@ -182,7 +184,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,\n } else if ((addr & 0x7) == 0) {\n if (size == 4) {\n /* timecmp_lo for RV32/RV64 */\n- uint64_t timecmp_hi = mtimer->timecmp[hartid] >> 32;\n+ uint64_t timecmp_hi = mtimer->timecmp[hartid_offset] >> 32;\n riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,\n timecmp_hi << 32 | (value & 0xFFFFFFFF));\n } else {\n@@ -193,7 +195,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwaddr addr,\n } else if ((addr & 0x7) == 4) {\n if (size == 4) {\n /* timecmp_hi for RV32/RV64 */\n- uint64_t timecmp_lo = mtimer->timecmp[hartid];\n+ uint64_t timecmp_lo = mtimer->timecmp[hartid_offset];\n riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hartid,\n value << 32 | (timecmp_lo & 0xFFFFFFFF));\n } else {\n", "prefixes": [ "PULL", "24/51" ] }