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GET /api/1.1/patches/2229998/?format=api
{ "id": 2229998, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229998/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-22-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-22-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:22", "name": "[PULL,21/51] hw/riscv/riscv-iommu: Add IPSR.PMIP RW1C support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "29b3d276d089d41c78b5ec6558059c8df41cb372", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-22-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229998/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229998/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=YhuOmwpP;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pl1-x631.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jay Chang <jay.chang@sifive.com>\n\nAdd proper RW1C (Read/Write 1 to Clear) support for the IPSR.PMIP\n(Performance Monitor Interrupt Pending) bit, which was missing from\nthe IPSR register implementation.\n\nSigned-off-by: Jay Chang <jay.chang@sifive.com>\nReviewed-by: Frank Chang <frank.chang@sifive.com>\nReviewed-by: Nutty Liu <nutty.liu@hotmail.com>\nReviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>\nMessage-ID: <20260325050011.66722-3-jay.chang@sifive.com>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n hw/riscv/riscv-iommu-bits.h | 1 +\n hw/riscv/riscv-iommu.c | 4 ++++\n 2 files changed, 5 insertions(+)", "diff": "diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h\nindex 47fe01bee5..a938fd3eb4 100644\n--- a/hw/riscv/riscv-iommu-bits.h\n+++ b/hw/riscv/riscv-iommu-bits.h\n@@ -189,6 +189,7 @@ enum riscv_iommu_ddtp_modes {\n #define RISCV_IOMMU_REG_IPSR 0x0054\n #define RISCV_IOMMU_IPSR_CIP BIT(0)\n #define RISCV_IOMMU_IPSR_FIP BIT(1)\n+#define RISCV_IOMMU_IPSR_PMIP BIT(2)\n #define RISCV_IOMMU_IPSR_PIP BIT(3)\n \n enum {\ndiff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c\nindex 8476405d0e..7ba3240552 100644\n--- a/hw/riscv/riscv-iommu.c\n+++ b/hw/riscv/riscv-iommu.c\n@@ -2150,6 +2150,10 @@ static void riscv_iommu_update_ipsr(RISCVIOMMUState *s, uint64_t data)\n ipsr_clr |= RISCV_IOMMU_IPSR_FIP;\n }\n \n+ if (!(data & RISCV_IOMMU_IPSR_PMIP)) {\n+ ipsr_clr |= RISCV_IOMMU_IPSR_PMIP;\n+ }\n+\n if (data & RISCV_IOMMU_IPSR_PIP) {\n pqcsr = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_PQCSR);\n \n", "prefixes": [ "PULL", "21/51" ] }