Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2229995/?format=api
{ "id": 2229995, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229995/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-19-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-19-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:19", "name": "[PULL,18/51] target/riscv: Use MO_LE for instruction fetch", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "29ac6d49a29bb9427b2ae9319b488e9b6cfc48eb", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-19-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229995/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229995/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=VRY9+Cyo;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g54cP3Xdhz1xvV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 14:50:29 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHwrt-0003Eb-4i; Wed, 29 Apr 2026 00:49:49 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwrn-00034l-9z\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:49:44 -0400", "from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwrl-0008UO-NP\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:49:43 -0400", "by mail-pg1-x535.google.com with SMTP id\n 41be03b00d2f7-c7961d7bc09so4937177a12.1\n for <qemu-devel@nongnu.org>; Tue, 28 Apr 2026 21:49:41 -0700 (PDT)", "from toolbx.alistair23.me ([2403:581e:fdf9:0:6209:4521:6813:45b7])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b988772ae8sm7756145ad.7.2026.04.28.21.49.35\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 28 Apr 2026 21:49:39 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777438180; x=1778042980; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=RnyPHQlUiDDCph8rrdK6ut5dk8ag4T7nwEwsUHMnquw=;\n b=VRY9+CyoHqlIhAs3MQU6RNhWmymeWGzEfeCoKYZSP4fcQvH/j+jfwbXDEbKnXi368x\n nOy5tYiqBOBDpjwmtDY3Hi+KQbq5HpwTedrIVKbWc9FXlupjaoYQOWvy258sbrtIouAu\n 2kAOc4fq9dQxHl/FvTRenuW4tTt5XWBQ6+BbfwZttXnCCEI67ux+jZqdHUs2n9Fstq7O\n 02ucuNTosfxYrS29qb4VeZEnmcG5zflltOrHXeX1vv9MLIULtGmnF4JTrW4Jvl47vbxp\n xQ/Kh+pGLoxDIKtdpwLajZoNNsj88hF4gX6U9mxdcc+HgquIAzC4YH27ZM6KMkCPIGeU\n aoIg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777438180; x=1778042980;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=RnyPHQlUiDDCph8rrdK6ut5dk8ag4T7nwEwsUHMnquw=;\n b=GRQgnLHCfiHMZ0+Me62/XB2twI4++vI90zjcgS4roEUv8ejYpBvSDw3kpCH+eJWrmN\n f4BQHutFTkmC0Rn37d9RtT7P0cQ4wz5YBZz1gMiiNx13LWJGYW45ISBHerNjWsqWbLL0\n n6tT24pSc1s7WxL+NXZCpFPkPiz7OzaN8AcuTxbw4++sr6+Kq3zhyzTz4NCoYFY+4XRj\n M+0Eu6vPId7pmAuObp6wjRNotwVvU758SueisUZDcUs77ncK6rtY5UpQSUiWScKhUXwT\n vyezYPhsUmkFCPTan8wZ6kNXGcpuSJJV9bFXoifU2jZCjtVlLiS4TlMIcRwPZjxrkQQc\n FFNw==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ8a4vNmSQrU/qXURgX7cWWfkEAWhAyqWksOPfNy0Y2rHy7z5RVbZsuakBym2zoj4DoBYeHRZgvblYAX@nongnu.org", "X-Gm-Message-State": "AOJu0YzmYfON3NfrwHKPyvxGoQX1YNG3tNQCHByGLJofjR2V4WfPbBrI\n swd62Rai/yM7I+wMFUuxr7Swfyc1kdrRBN0aQ+6OJ870A8+7VWJd/ehe", "X-Gm-Gg": "AeBDievN5BT6CAaRnDtAPA7IiqJJ4Jl2YcAHjNQlLkN2dsu4wVGcXaOmom0SRh11YYZ\n yacgBfSn3KuPxpo9uZmKQLQgl4dhRyO/LGyGzk5uqgfzns5dW+F5LF2fk3Gk/ro6RlzSfQL/v5Z\n o9+hrRKD/RoDDdQjOtOCYY6htqaniofmkueqBJIDKjoUkd34vsWXeKjcJxZDdaIXlTObUYxLS9n\n Vsf8tkCxsbyds4rQ29NfpTUmCLSaPWlGDlR7shNhnOHmcc5uxC5Hk3h+NUvkj6oOJlH73kF4KuB\n yE9MTjZtU+2bEPzkU6MiyIE3vDF+UWGdhgkR8rVfWMY3LlRmOy/CFqvGgDZZ3DPOVndnrCnvG9A\n QfzeBKAdDf8HHSYOUF8MK8evMQZ737dX7VnM1Ip5ghvSxWygcG3/rq2CFqNrdopaW/npfXMSUcX\n GyumoOgcivR9FjBpnuTC+GB8X31F3AWSlRCQdoC+ubYmskcHQTzUoq", "X-Received": "by 2002:a17:902:ebca:b0:2b2:5704:5715 with SMTP id\n d9443c01a7336-2b97c43d4d3mr56814955ad.15.1777438180374;\n Tue, 28 Apr 2026 21:49:40 -0700 (PDT)", "From": "alistair23@gmail.com", "X-Google-Original-From": "alistair.francis@wdc.com", "To": "palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org", "Cc": "alistair23@gmail.com, Djordje Todorovic <Djordje.Todorovic@htecgroup.com>,\n Alistair Francis <alistair.francis@wdc.com>, =?utf-8?q?Philippe_Mathieu-Dau?=\n\t=?utf-8?q?d=C3=A9?= <philmd@linaro.org>", "Subject": "[PULL 18/51] target/riscv: Use MO_LE for instruction fetch", "Date": "Wed, 29 Apr 2026 14:47:19 +1000", "Message-ID": "<20260429044752.4176397-19-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "References": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::535;\n envelope-from=alistair23@gmail.com; helo=mail-pg1-x535.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>\n\nRISC-V instructions are always little-endian regardless of the data\nendianness mode configured via mstatus SBE/MBE/UBE bits.\n\nCurrently, instruction fetches in decode_opc() and the page boundary\ncheck use mo_endian(ctx), which returns MO_TE. This happens to work\ntoday because RISC-V targets are little-endian only, but is\nsemantically incorrect and will break once mo_endian() is updated to\nrespect runtime data endianness for big-endian support.\n\nUse MO_LE explicitly for all instruction fetch paths. Data memory\noperations (AMOs, loads/stores via mxl_memop) continue to use\nmo_endian(ctx) as they should respect the configured data endianness.\n\nNot-Signed-off-by: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260311115910.564481-3-djordje.todorovic@htecgroup.com>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-ID: <20260318103122.97244-16-philmd@linaro.org>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n target/riscv/translate.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/riscv/translate.c b/target/riscv/translate.c\nindex 1a25c517a2..f6b915a7fb 100644\n--- a/target/riscv/translate.c\n+++ b/target/riscv/translate.c\n@@ -1258,7 +1258,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n * additional page fault.\n */\n opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n } else {\n /*\n * For unaligned pc, instruction preload may trigger additional\n@@ -1266,7 +1266,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n */\n opcode = (uint32_t) translator_lduw_end(env, &ctx->base,\n ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n }\n ctx->ol = ctx->xl;\n \n@@ -1288,7 +1288,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)\n opcode = deposit32(opcode, 16, 16,\n translator_lduw_end(env, &ctx->base,\n ctx->base.pc_next + 2,\n- mo_endian(ctx)));\n+ MO_LE));\n }\n ctx->opcode = opcode;\n \n@@ -1404,7 +1404,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {\n uint16_t next_insn =\n translator_lduw_end(env, &ctx->base, ctx->base.pc_next,\n- mo_endian(ctx));\n+ MO_LE);\n int len = insn_len(next_insn);\n \n if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {\n", "prefixes": [ "PULL", "18/51" ] }