Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.1/patches/2229987/?format=api
{ "id": 2229987, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229987/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-5-alistair.francis@wdc.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260429044752.4176397-5-alistair.francis@wdc.com>", "date": "2026-04-29T04:47:05", "name": "[PULL,04/51] disas: diassemble RISC-V xlrbr (crc32) instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0c201168b12b3c8cd02a13e1fedb070182f59a47", "submitter": { "id": 64571, "url": "http://patchwork.ozlabs.org/api/1.1/people/64571/?format=api", "name": "Alistair Francis", "email": "alistair23@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260429044752.4176397-5-alistair.francis@wdc.com/mbox/", "series": [ { "id": 501983, "url": "http://patchwork.ozlabs.org/api/1.1/series/501983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501983", "date": "2026-04-29T04:47:05", "name": "[PULL,01/51] hw/riscv/riscv-iommu: Use standard EN_PRI bit for PRI", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501983/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229987/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229987/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=gWUIgn2h;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g54Zk0hsHz1yHX\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 14:49:00 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wHwqk-00010I-TU; Wed, 29 Apr 2026 00:48:38 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwqi-0000zv-Ld\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:48:38 -0400", "from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <alistair23@gmail.com>)\n id 1wHwqf-0008FQ-Og\n for qemu-devel@nongnu.org; Wed, 29 Apr 2026 00:48:36 -0400", "by mail-pl1-x633.google.com with SMTP id\n d9443c01a7336-2b25cf1b5f0so66518875ad.3\n for <qemu-devel@nongnu.org>; Tue, 28 Apr 2026 21:48:33 -0700 (PDT)", "from toolbx.alistair23.me ([2403:581e:fdf9:0:6209:4521:6813:45b7])\n by smtp.gmail.com with ESMTPSA id\n d9443c01a7336-2b988772ae8sm7756145ad.7.2026.04.28.21.48.27\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 28 Apr 2026 21:48:31 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1777438112; x=1778042912; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=W3qddBomdwVPgXcvkN5q95ic1E8DF7L9b2VLQtgxH/4=;\n b=gWUIgn2hGr+cIsN40PJdFOdieVnjuMR9O8+8/sDRdE8dpUiHDRgkgK2nnRXhA1PNNh\n 8VGKdPlSXxTuuRHA5YlpQMgD1Lu9ntgcZ77nIz7pLApAU9GYwvqdtR+/nA38ppso0LPw\n PFJw6lt09HzBKpKTdruca86Zby0Kft+IPenYCPF9RUjdrNIJflcmOcXjJIlhJwfFaykQ\n 41JZruUtHdmJrnOsMkyGDhsETbsgPBP5EVX73eBqxI5238QXxTM07wfbO5x2Lu+BQg8w\n ia+4BpkaQLT2dssMBj0O/rFEKv0P3tEQQg1dpSCrsJ4YSS/jW+NuGSDXlIYbsURZGXoM\n hJYg==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1777438112; x=1778042912;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=W3qddBomdwVPgXcvkN5q95ic1E8DF7L9b2VLQtgxH/4=;\n b=SaA6lagaDTX7fC1VV2m2UnI9VhcSzEzIzeMZD5Zpl2cA5wcFTtWRbhz9mbsS/h/FBL\n /jwSBYFKcMwZacaq4MAnDklHsyAn8g5qI9nBQg+nLnoe7VOZD1n0yDLSh2oaCjwvZz2l\n hhB1pI7w97ZUmDzo9+VVHvTnFSoUCb5f/fGVm5nWkQUhIJdbyWEQ9vZ5DxSugt982s/G\n ljsvIUmCKZ3bd2WqjTWH5INHXwh606pToJ3VIsTHkzm5s3gvlAG7eilxgOWPeZ9RlTyj\n vreY3Wth5ZgziEgHU5b9p1CphAcGhbfN9V0pXfuj1+RLf1yeR1b/lxLRVlgL+jqKsaUD\n /C5A==", "X-Forwarded-Encrypted": "i=1;\n AFNElJ9m6ZhcCKPlzPsIHG8fEgxaXwzgUBPTpn2ekQ6R55l7l9aHPmx1iQGfrjKZg82kdFJB7dPgQAyqLtaK@nongnu.org", "X-Gm-Message-State": "AOJu0YzOnmLgdgJrWIpoKe9TY1EtZ63ZhfLXrIA0Su/ZQm28onF5GzEf\n idiwefGNnj+B4/Vs5jXoJLjzqfwI7CcNmF8/UtqUEIiR0NpFZGCo4hCV", "X-Gm-Gg": "AeBDieuf9YtYbMCAbVfWAE9YIoqeadenQQGIsnIvVHoy151xk62ppWPkU2EkdkJtK1P\n qAc3YMxPhUQMX+we5u6JorLCUav9ENKg4n7Hx0dxvFNBZr6IN3Z7Skj5xqs83t8EEjHRrQ5KloU\n KDuuCv5ERsVlW+MrTjB6Q30+pN9DQEiUUJ0Y6XpJ+JRAvtR4NwwHzR1V+aBIjqI+hHr1RBpR1ur\n 6LzVuyoLo9W0M/hW5h0lqxxRi/EsGvmfxWpw7H7iP2OSTO3VfTCMjJOQKPFblWLuX+oLNTs/f7M\n 6D5LdvXasxJwo1bQsiph+KMg/mV/dhOxPVy7HEYpY7DU1dOUxO+J+4TT6miV6lW68QAtsY1e4P+\n MbA7MRbuh7VYPrLR+MmKAqRfkg1mNDPnQAj3d7JQ87TdnaUNnpELLhXdIi6/Cna24yxXVH8b/YG\n GemOU10FwLITuawO9mLe7pbMyznGIKk793YxeA2hfrYxc6byScWp4Q", "X-Received": "by 2002:a17:902:f08d:b0:2ae:46b9:c653 with SMTP id\n d9443c01a7336-2b98744d1bdmr14639225ad.33.1777438112103;\n Tue, 28 Apr 2026 21:48:32 -0700 (PDT)", "From": "alistair23@gmail.com", "X-Google-Original-From": "alistair.francis@wdc.com", "To": "palmer@dabbelt.com, liwei1518@gmail.com, daniel.barboza@oss.qualcomm.com,\n zhiwei_liu@linux.alibaba.com, chao.liu.zevorn@gmail.com,\n qemu-riscv@nongnu.org, qemu-devel@nongnu.org", "Cc": "alistair23@gmail.com, Emmanuel Blot <eblot@rivosinc.com>,\n James Wainwright <james.wainwright@lowrisc.org>,\n Alistair Francis <alistair.francis@wdc.com>", "Subject": "[PULL 04/51] disas: diassemble RISC-V xlrbr (crc32) instructions", "Date": "Wed, 29 Apr 2026 14:47:05 +1000", "Message-ID": "<20260429044752.4176397-5-alistair.francis@wdc.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "References": "<20260429044752.4176397-1-alistair.francis@wdc.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::633;\n envelope-from=alistair23@gmail.com; helo=mail-pl1-x633.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Emmanuel Blot <eblot@rivosinc.com>\n\nPlaced in a separate file as a vendor extension.\n\nSigned-off-by: James Wainwright <james.wainwright@lowrisc.org>\nReviewed-by: Alistair Francis <alistair.francis@wdc.com>\nMessage-ID: <20260320134254.217123-4-james.wainwright@lowrisc.org>\nSigned-off-by: Alistair Francis <alistair.francis@wdc.com>\n---\n MAINTAINERS | 2 +-\n disas/riscv-xlrbr.h | 19 +++++++++++\n disas/riscv-xlrbr.c | 79 +++++++++++++++++++++++++++++++++++++++++++++\n disas/riscv.c | 2 ++\n disas/meson.build | 3 +-\n 5 files changed, 103 insertions(+), 2 deletions(-)\n create mode 100644 disas/riscv-xlrbr.h\n create mode 100644 disas/riscv-xlrbr.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex f7e835cf55..e41f0eb92c 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -4135,7 +4135,7 @@ R: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>\n L: qemu-riscv@nongnu.org\n S: Maintained\n F: tcg/riscv64/\n-F: disas/riscv.[ch]\n+F: disas/riscv*.[ch]\n \n S390 TCG target\n M: Richard Henderson <richard.henderson@linaro.org>\ndiff --git a/disas/riscv-xlrbr.h b/disas/riscv-xlrbr.h\nnew file mode 100644\nindex 0000000000..939a69ea6d\n--- /dev/null\n+++ b/disas/riscv-xlrbr.h\n@@ -0,0 +1,19 @@\n+/*\n+ * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32\n+ * bitmanip extension v0.93.\n+ *\n+ * Copyright (c) 2023 Rivos Inc\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#ifndef DISAS_RISCV_XLRBR_H\n+#define DISAS_RISCV_XLRBR_H\n+\n+#include \"disas/riscv.h\"\n+\n+extern const rv_opcode_data rv_xlrbr_opcode_data[];\n+\n+void decode_xlrbr(rv_decode *, rv_isa);\n+\n+#endif /* DISAS_RISCV_XLRBR_H */\ndiff --git a/disas/riscv-xlrbr.c b/disas/riscv-xlrbr.c\nnew file mode 100644\nindex 0000000000..57cb434523\n--- /dev/null\n+++ b/disas/riscv-xlrbr.c\n@@ -0,0 +1,79 @@\n+/*\n+ * QEMU RISC-V Disassembler for xlrbr matching the unratified Zbr CRC32\n+ * bitmanip extension v0.93.\n+ *\n+ * Copyright (c) 2023 Rivos Inc\n+ *\n+ * SPDX-License-Identifier: GPL-2.0-or-later\n+ */\n+\n+#include \"qemu/osdep.h\"\n+\n+#include \"disas/riscv.h\"\n+#include \"disas/riscv-xlrbr.h\"\n+\n+typedef enum {\n+ /* 0 is reserved for rv_op_illegal. */\n+ rv_op_crc32_b = 1,\n+ rv_op_crc32_h = 2,\n+ rv_op_crc32_w = 3,\n+ rv_op_crc32_d = 4,\n+ rv_op_crc32c_b = 5,\n+ rv_op_crc32c_h = 6,\n+ rv_op_crc32c_w = 7,\n+ rv_op_crc32c_d = 8,\n+} rv_xlrbr_op;\n+\n+const rv_opcode_data rv_xlrbr_opcode_data[] = {\n+ { \"illegal\", rv_codec_illegal, rv_fmt_none, NULL, 0, 0, 0 },\n+ { \"crc32.b\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32.h\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32.w\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32.d\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32c.b\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32c.h\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32c.w\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+ { \"crc32c.d\", rv_codec_r, rv_fmt_rd_rs1, NULL, 0, 0, 0 },\n+};\n+\n+void decode_xlrbr(rv_decode *dec, rv_isa isa)\n+{\n+ rv_inst inst = dec->inst;\n+ rv_opcode op = rv_op_illegal;\n+\n+ switch ((inst >> 0) & 0b1111111) {\n+ case 0b0010011:\n+ switch ((inst >> 12) & 0b111) {\n+ case 0b001:\n+ switch ((inst >> 20 & 0b111111111111)) {\n+ case 0b011000010000:\n+ op = rv_op_crc32_b;\n+ break;\n+ case 0b011000010001:\n+ op = rv_op_crc32_h;\n+ break;\n+ case 0b011000010010:\n+ op = rv_op_crc32_w;\n+ break;\n+ case 0b011000010011:\n+ op = rv_op_crc32_d;\n+ break;\n+ case 0b011000011000:\n+ op = rv_op_crc32c_b;\n+ break;\n+ case 0b011000011001:\n+ op = rv_op_crc32c_h;\n+ break;\n+ case 0b011000011010:\n+ op = rv_op_crc32c_w;\n+ break;\n+ case 0b011000011011:\n+ op = rv_op_crc32c_d;\n+ break;\n+ }\n+ break;\n+ }\n+ break;\n+ }\n+ dec->op = op;\n+}\ndiff --git a/disas/riscv.c b/disas/riscv.c\nindex 6f2667482d..d416a4d6b3 100644\n--- a/disas/riscv.c\n+++ b/disas/riscv.c\n@@ -26,6 +26,7 @@\n /* Vendor extensions */\n #include \"disas/riscv-xthead.h\"\n #include \"disas/riscv-xventana.h\"\n+#include \"disas/riscv-xlrbr.h\"\n \n typedef enum {\n /* 0 is reserved for rv_op_illegal. */\n@@ -5434,6 +5435,7 @@ static GString *disasm_inst(rv_isa isa, uint64_t pc, rv_inst inst,\n { has_xtheadmempair_p, xthead_opcode_data, decode_xtheadmempair },\n { has_xtheadsync_p, xthead_opcode_data, decode_xtheadsync },\n { has_XVentanaCondOps_p, ventana_opcode_data, decode_xventanacondops },\n+ { has_xlrbr_p, rv_xlrbr_opcode_data, decode_xlrbr },\n };\n \n for (size_t i = 0; i < ARRAY_SIZE(decoders); i++) {\ndiff --git a/disas/meson.build b/disas/meson.build\nindex bbfa119783..42977a1f74 100644\n--- a/disas/meson.build\n+++ b/disas/meson.build\n@@ -7,7 +7,8 @@ common_ss.add(when: 'CONFIG_MIPS_DIS', if_true: files('mips.c', 'nanomips.c'))\n common_ss.add(when: 'CONFIG_RISCV_DIS', if_true: files(\n 'riscv.c',\n 'riscv-xthead.c',\n- 'riscv-xventana.c'\n+ 'riscv-xventana.c',\n+ 'riscv-xlrbr.c'\n ))\n common_ss.add(when: 'CONFIG_SH4_DIS', if_true: files('sh4.c'))\n common_ss.add(when: 'CONFIG_SPARC_DIS', if_true: files('sparc.c'))\n", "prefixes": [ "PULL", "04/51" ] }