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GET /api/1.1/patches/2229981/?format=api
{ "id": 2229981, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229981/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428-ax3005_scm3005-v1-2-7fed19ee6fe0@axiado.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428-ax3005_scm3005-v1-2-7fed19ee6fe0@axiado.com>", "date": "2026-04-29T02:32:37", "name": "[2/2] arm: axiado: Add AX3005 based SCM3005 board support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d926c4fbcadecb76f570f567168bb501cf4fc149", "submitter": { "id": 93280, "url": "http://patchwork.ozlabs.org/api/1.1/people/93280/?format=api", "name": "Karthikeyan Mitran", "email": "kmitran@axiado.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428-ax3005_scm3005-v1-2-7fed19ee6fe0@axiado.com/mbox/", "series": [ { "id": 501976, "url": "http://patchwork.ozlabs.org/api/1.1/series/501976/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501976", "date": "2026-04-29T02:32:35", "name": "Adding Axiado ax3005 based scm3005 board support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501976/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229981/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229981/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=axiado.com header.i=@axiado.com header.a=rsa-sha256\n header.s=selector1 header.b=ZXaMvPBa;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=axiado.com;", "Received-SPF": "Fail (protection.outlook.com: domain of axiado.com does not\n designate 64.62.143.114 as permitted sender) receiver=protection.outlook.com;\n client-ip=64.62.143.114; helo=smtp.corp.axiado.com;", "From": "Karthikeyan Mitran <kmitran@axiado.com>", "Date": "Tue, 28 Apr 2026 19:32:37 -0700", "Subject": "[PATCH 2/2] arm: axiado: Add AX3005 based SCM3005 board support", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "<20260428-ax3005_scm3005-v1-2-7fed19ee6fe0@axiado.com>", "References": "<20260428-ax3005_scm3005-v1-0-7fed19ee6fe0@axiado.com>", "In-Reply-To": "<20260428-ax3005_scm3005-v1-0-7fed19ee6fe0@axiado.com>", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Siu Ming Tong <smtong@axiado.com>,\n Prasad Bolisetty <pbolisetty@axiado.com>,\n Andre Przywara <andre.przywara@arm.com>, Tzu-Hao Wei <twei@axiado.com>,\n Simon Glass <sjg@chromium.org>, Neil Armstrong <neil.armstrong@linaro.org>,\n Sumit Garg <sumit.garg@kernel.org>, Karthikeyan Mitran <kmitran@axiado.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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Ip=[64.62.143.114];\n Helo=[smtp.corp.axiado.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH1PEPF0000A346.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM3PPF516449E88", "X-Mailman-Approved-At": "Wed, 29 Apr 2026 04:43:59 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Siu Ming Tong <smtong@axiado.com>\n\nAdd U-Boot board support for the Axiado AX3005 based targets, a quad-core\nARM Cortex-A53 (ARMv8) platform.\n\nBoard Kconfig introduces ARCH_AX3005, which selects ARM64, driver\nmodel, GIC-v3, and Zynq UART. TARGET_SCM3005 selects ARCH_AX3005,\nallowing future SoC variants to share the platform configuration.\n\nSecondary cores use spin-table boot. ft_board_setup() corrects\nthe cpu-release-addr in the FDT, which arch_fixup_fdt() overwrites\nwith the post-relocation address. The board linker script pins\nspin_table_v8.o at offset 0x2fa0 from text base to match the\naddress declared in the device tree.\n\nTested-by: Siu Ming Tong <smtong@axiado.com>\nSigned-off-by: Siu Ming Tong <smtong@axiado.com>\nSigned-off-by: Tzu-Hao Wei <twei@axiado.com>\nSigned-off-by: Karthikeyan Mitran <kmitran@axiado.com>\n---\n MAINTAINERS | 10 +++\n arch/arm/Kconfig | 17 ++++\n board/axiado/scm3005/Kconfig | 15 ++++\n board/axiado/scm3005/Makefile | 5 ++\n board/axiado/scm3005/scm3005.c | 128 +++++++++++++++++++++++++++\n board/axiado/scm3005/u-boot.lds | 183 +++++++++++++++++++++++++++++++++++++++\n configs/ax3005_scm3005_defconfig | 73 ++++++++++++++++\n include/configs/ax3005-scm3005.h | 29 +++++++\n 8 files changed, 460 insertions(+)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 056902f6ef2..b8ca2c39a8e 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -213,6 +213,16 @@ F:\tdrivers/reset/reset-ast2500.c\n F:\tdrivers/watchdog/ast_wdt.c\n N:\taspeed\n \n+ARM AXIADO AX3005 SCM3005\n+M:\tSiu Ming Tong <smtong@axiado.com>\n+M:\tKarthikeyan Mitran <kmitran@axiado.com>\n+M:\tPrasad Bolisetty <pbolisetty@axiado.com>\n+S:\tMaintained\n+F:\tarch/arm/dts/ax3005*\n+F:\tboard/axiado/scm3005/\n+F:\tconfigs/ax3005_scm3005_defconfig\n+F:\tinclude/configs/ax3005-scm3005.h\n+\n ARM BROADCOM BCM283X / BCM27XX\n M:\tMatthias Brugger <mbrugger@suse.com>\n M:\tPeter Robinson <pbrobinson@gmail.com>\ndiff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex f624675eadf..c22bba24db0 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -1941,6 +1941,13 @@ config ARCH_SC5XX\n \tselect SUPPORT_SPL\n \tselect TIMER\n \n+config TARGET_SCM3005\n+\tbool \"Support Axiado AX3005 SCM3005\"\n+\tselect ARCH_AX3005\n+\thelp\n+\t Support for the Axiado AX3005 SCM3005 board.\n+\t Based on the Axiado AX3005 quad-core ARMv8 Cortex-A53 SoC.\n+\n config TARGET_SL28\n \tbool \"Support sl28\"\n \tselect ARCH_LS1028A\n@@ -2203,6 +2210,15 @@ config ARCH_GXP\n \n endchoice\n \n+config ARCH_AX3005\n+\tbool\n+\tselect ARM64\n+\tselect ARMV8_SWITCH_TO_EL1\n+\tselect DM\n+\tselect DM_SERIAL\n+\tselect GICV3\n+\tselect ZYNQ_SERIAL\n+\n config SUPPORT_PASSING_ATAGS\n \tbool \"Support pre-devicetree ATAG-based booting\"\n \tdepends on !ARM64\n@@ -2421,6 +2437,7 @@ source \"board/Marvell/octeontx/Kconfig\"\n source \"board/Marvell/octeontx2/Kconfig\"\n source \"board/armltd/vexpress/Kconfig\"\n source \"board/armltd/vexpress64/Kconfig\"\n+source \"board/axiado/scm3005/Kconfig\"\n source \"board/cortina/presidio-asic/Kconfig\"\n source \"board/broadcom/bcmns/Kconfig\"\n source \"board/broadcom/bcmns3/Kconfig\"\ndiff --git a/board/axiado/scm3005/Kconfig b/board/axiado/scm3005/Kconfig\nnew file mode 100644\nindex 00000000000..d6f4f311f55\n--- /dev/null\n+++ b/board/axiado/scm3005/Kconfig\n@@ -0,0 +1,15 @@\n+if TARGET_SCM3005\n+\n+config SYS_BOARD\n+\tstring\n+\tdefault \"scm3005\"\n+\n+config SYS_VENDOR\n+\tstring\n+\tdefault \"axiado\"\n+\n+config SYS_CONFIG_NAME\n+\tstring\n+\tdefault \"ax3005-scm3005\"\n+\n+endif\ndiff --git a/board/axiado/scm3005/Makefile b/board/axiado/scm3005/Makefile\nnew file mode 100644\nindex 00000000000..3d35713bab9\n--- /dev/null\n+++ b/board/axiado/scm3005/Makefile\n@@ -0,0 +1,5 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+#\n+# Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+\n+obj-y := scm3005.o\ndiff --git a/board/axiado/scm3005/scm3005.c b/board/axiado/scm3005/scm3005.c\nnew file mode 100644\nindex 00000000000..4643ba4a55c\n--- /dev/null\n+++ b/board/axiado/scm3005/scm3005.c\n@@ -0,0 +1,128 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+ */\n+\n+#include <config.h>\n+#include <dm.h>\n+#include <init.h>\n+#include <asm/global_data.h>\n+#include <asm/armv8/mmu.h>\n+#include <asm/io.h>\n+#include <asm/spin_table.h>\n+#include <asm/system.h>\n+#include <fdt_support.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct mm_region axiado_ax3005_mem_map[] = {\n+\t{ /* Peripherals including UART */\n+\t .virt = 0x00000000UL,\n+\t .phys = 0x00000000UL,\n+\t .size = 0x4A000000UL, /* 0 to 0x4A000000: peripherals */\n+\t .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE |\n+\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN },\n+\t{ .virt = 0x80000000UL,\n+\t .phys = 0x80000000UL,\n+\t .size = 0x80000000UL,\n+\t .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE },\n+\t{\n+\t\t0,\n+\t}\n+};\n+\n+struct mm_region *mem_map = axiado_ax3005_mem_map;\n+\n+/*\n+ * Accept any FIT configuration name - the board loads a single FIT image\n+ * and the first matching config is used.\n+ */\n+int board_fit_config_name_match(const char *name)\n+{\n+\treturn 0;\n+}\n+\n+/*\n+ * ft_board_setup - restore cpu-release-addr after relocation\n+ *\n+ * arch_fixup_fdt() / spin_table_update_dt() overwrites cpu-release-addr\n+ * with U-Boot's relocated address. Restore the pre-relocation physical\n+ * address so secondary cores spin on the correct location.\n+ */\n+int ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\tint cpus_offset, offset;\n+\tconst char *prop;\n+\tint ret;\n+\tu64 cpu_release_addr = (u64)&spin_table_cpu_release_addr - gd->reloc_off;\n+\n+\tcpus_offset = fdt_path_offset(blob, \"/cpus\");\n+\tif (cpus_offset < 0)\n+\t\treturn 0;\n+\n+\tfor (offset = fdt_first_subnode(blob, cpus_offset); offset >= 0;\n+\t offset = fdt_next_subnode(blob, offset)) {\n+\t\tprop = fdt_getprop(blob, offset, \"device_type\", NULL);\n+\t\tif (!prop || strcmp(prop, \"cpu\"))\n+\t\t\tcontinue;\n+\n+\t\tprop = fdt_getprop(blob, offset, \"enable-method\", NULL);\n+\t\tif (!prop || strcmp(prop, \"spin-table\"))\n+\t\t\tcontinue;\n+\n+\t\tret = fdt_setprop_u64(blob, offset, \"cpu-release-addr\",\n+\t\t\t\t cpu_release_addr);\n+\t\tif (ret) {\n+\t\t\tprintf(\"WARNING: Failed to restore cpu-release-addr\\n\");\n+\t\t\treturn ret;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * dram_init - DDR is initialized by firmware, just setting size\n+ */\n+int dram_init(void)\n+{\n+\tgd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,\n+\t\t\t\t CFG_SYS_SDRAM_SIZE);\n+\treturn 0;\n+}\n+\n+/*\n+ * the SOC uses single bank, non-interleaving\n+ */\n+int dram_init_banksize(void)\n+{\n+\tgd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;\n+\tgd->bd->bi_dram[0].size = CFG_SYS_SDRAM_SIZE;\n+\treturn 0;\n+}\n+\n+/*\n+ * timer_init - enable the AX3005 platform system timer\n+ *\n+ * CNTFRQ_EL0 is already set by arch/arm/cpu/armv8/start.S using\n+ * CONFIG_COUNTER_FREQUENCY from the defconfig.\n+ *\n+ * SYS_TIMER_CTRL (0x48016000) is the AX3005 system timer control\n+ * register — writing SYS_TIMER_ENABLE starts the counter that feeds\n+ * the ARM generic timer.\n+ */\n+int timer_init(void)\n+{\n+\twritel(SYS_TIMER_ENABLE, SYS_TIMER_CTRL);\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\treturn 0;\n+}\n+\n+void reset_cpu(void)\n+{\n+\t/* For later ARM_PSCI_FW or watchdog reset */\n+}\ndiff --git a/board/axiado/scm3005/u-boot.lds b/board/axiado/scm3005/u-boot.lds\nnew file mode 100644\nindex 00000000000..8e56535fdf9\n--- /dev/null\n+++ b/board/axiado/scm3005/u-boot.lds\n@@ -0,0 +1,183 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+ *\n+ * Based on arch/arm/cpu/armv8/u-boot.lds\n+ */\n+\n+#include <config.h>\n+#include <asm/psci.h>\n+\n+OUTPUT_FORMAT(\"elf64-littleaarch64\", \"elf64-littleaarch64\", \"elf64-littleaarch64\")\n+OUTPUT_ARCH(aarch64)\n+ENTRY(_start)\n+SECTIONS\n+{\n+#ifdef CONFIG_ARMV8_SECURE_BASE\n+\t/DISCARD/ : { *(.rela._secure*) }\n+#endif\n+\t. = 0x00000000;\n+\n+\t. = ALIGN(8);\n+\t__image_copy_start = ADDR(.text);\n+\t.text :\n+\t{\n+\t\tCPUDIR/start.o (.text*)\n+\t\t. = ALIGN(0x2000);\n+\t\t. = . + 3984;\n+\t\tKEEP(*spin_table_v8.o(.text*))\n+\t}\n+\n+\t__text_section_end = ABSOLUTE(.);\n+\n+\t/* This needs to come before *(.text*) */\n+\t.efi_runtime : {\n+\t\t__efi_runtime_start = .;\n+\t\t*(.text.efi_runtime*)\n+\t\t*(.rodata.efi_runtime*)\n+\t\t*(.data.efi_runtime*)\n+\t\t__efi_runtime_stop = .;\n+\t}\n+\n+#ifdef CONFIG_MMU_PGPROT\n+\t.text_rest ALIGN(CONSTANT(COMMONPAGESIZE)) :\n+#else\n+\t.text_rest :\n+#endif\n+\t{\n+\t\t__text_start = .;\n+\t\t*(.text*)\n+#ifdef CONFIG_MMU_PGPROT\n+\t\t. = ALIGN(CONSTANT(COMMONPAGESIZE));\n+#endif\n+\t\t__text_end = .;\n+\t}\n+\n+#ifdef CONFIG_ARMV8_PSCI\n+\t.__secure_start :\n+#ifndef CONFIG_ARMV8_SECURE_BASE\n+\t\tALIGN(CONSTANT(COMMONPAGESIZE))\n+#endif\n+\t{\n+\t\tKEEP(*(.__secure_start))\n+\t}\n+\n+#ifndef CONFIG_ARMV8_SECURE_BASE\n+#define __ARMV8_SECURE_BASE\n+#define __ARMV8_PSCI_STACK_IN_RAM\n+#else\n+#define __ARMV8_SECURE_BASE\tCONFIG_ARMV8_SECURE_BASE\n+#endif\n+\t.secure_text __ARMV8_SECURE_BASE :\n+\t\tAT(ADDR(.__secure_start) + SIZEOF(.__secure_start))\n+\t{\n+\t\t*(._secure.text)\n+\t\t. = ALIGN(8);\n+\t\t__secure_svc_tbl_start = .;\n+\t\tKEEP(*(._secure_svc_tbl_entries))\n+\t\t__secure_svc_tbl_end = .;\n+\t}\n+\n+\t.secure_data : AT(LOADADDR(.secure_text) + SIZEOF(.secure_text))\n+\t{\n+\t\t*(._secure.data)\n+\t}\n+\n+\t.secure_stack ALIGN(ADDR(.secure_data) + SIZEOF(.secure_data),\n+\t\t\t CONSTANT(COMMONPAGESIZE)) (NOLOAD) :\n+#ifdef __ARMV8_PSCI_STACK_IN_RAM\n+\t\tAT(ADDR(.secure_stack))\n+#else\n+\t\tAT(LOADADDR(.secure_data) + SIZEOF(.secure_data))\n+#endif\n+\t{\n+\t\tKEEP(*(.__secure_stack_start))\n+\n+\t\t. = . + CONFIG_ARMV8_PSCI_NR_CPUS * ARM_PSCI_STACK_SIZE;\n+\n+\t\t. = ALIGN(CONSTANT(COMMONPAGESIZE));\n+\n+\t\tKEEP(*(.__secure_stack_end))\n+\t}\n+\n+#ifndef __ARMV8_PSCI_STACK_IN_RAM\n+\t. = LOADADDR(.secure_stack);\n+#endif\n+\n+\t.__secure_end : AT(ADDR(.__secure_end)) {\n+\t\tKEEP(*(.__secure_end))\n+\t\tLONG(0x1d1071c);\t/* Must output something to reset LMA */\n+\t}\n+#endif\n+\t.efi_runtime_rel : {\n+\t\t__efi_runtime_rel_start = .;\n+\t\t*(.rel*.efi_runtime)\n+\t\t*(.rel*.efi_runtime.*)\n+\t\t__efi_runtime_rel_stop = .;\n+\t}\n+\n+#ifdef CONFIG_MMU_PGPROT\n+\t.rodata ALIGN(CONSTANT(COMMONPAGESIZE)): {\n+#else\n+\t.rodata ALIGN(8) : {\n+#endif\n+\t\t__start_rodata = .;\n+\t\t*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))\n+\t}\n+\n+\t__u_boot_list ALIGN(8) : {\n+\t\tKEEP(*(SORT(__u_boot_list*)));\n+#ifdef CONFIG_MMU_PGPROT\n+\t\t. = ALIGN(CONSTANT(COMMONPAGESIZE));\n+#endif\n+\t\t__end_rodata = .;\n+\t}\n+\n+#ifdef CONFIG_MMU_PGPROT\n+\t.data ALIGN(CONSTANT(COMMONPAGESIZE)) : {\n+#else\n+\t.data ALIGN(8) : {\n+#endif\n+\t\t__start_data = .;\n+\t\t*(.data*)\n+\t}\n+\n+\t. = ALIGN(8);\n+\t__image_copy_end = .;\n+\n+\t.rela.dyn ALIGN(8) : {\n+\t\t__rel_dyn_start = .;\n+\t\t*(.rela*)\n+\t\t__rel_dyn_end = .;\n+\t\t. = ALIGN(8);\n+\t}\n+\n+\t_end = .;\n+\n+\t/*\n+\t * arch/arm/lib/crt0_64.S assumes __bss_start - __bss_end % 8 == 0\n+\t */\n+\t.bss ADDR(.rela.dyn) (OVERLAY) : {\n+\t\t__bss_start = .;\n+\t\t*(.bss*)\n+\t\t. = ALIGN(8);\n+\t\t__bss_end = .;\n+#ifdef CONFIG_MMU_PGPROT\n+\t\t. = ALIGN(CONSTANT(COMMONPAGESIZE));\n+#endif\n+\t\t__end_data = .;\n+\t}\n+\n+\t/DISCARD/ : { *(.dynsym) }\n+\t/DISCARD/ : { *(.dynstr*) }\n+\t/DISCARD/ : { *(.dynamic*) }\n+\t/DISCARD/ : { *(.plt*) }\n+\t/DISCARD/ : { *(.interp*) }\n+\t/DISCARD/ : { *(.gnu*) }\n+\n+#ifdef CONFIG_LINUX_KERNEL_IMAGE_HEADER\n+#include \"linux-kernel-image-header-vars.h\"\n+#endif\n+}\n+\n+ASSERT(_end % 8 == 0, \"_end must be 8-byte aligned for device tree\");\ndiff --git a/configs/ax3005_scm3005_defconfig b/configs/ax3005_scm3005_defconfig\nnew file mode 100644\nindex 00000000000..447151522c1\n--- /dev/null\n+++ b/configs/ax3005_scm3005_defconfig\n@@ -0,0 +1,73 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+CONFIG_TEXT_BASE=0x80000000\n+CONFIG_SYS_MONITOR_BASE=0x80000000\n+CONFIG_SYS_LOAD_ADDR=0x80100000\n+CONFIG_SYS_MALLOC_F_LEN=0x8000\n+CONFIG_SYS_MALLOC_LEN=0x20000\n+CONFIG_SYS_BOOTM_LEN=0x20000000\n+CONFIG_ENV_SIZE=0x10000\n+CONFIG_ENV_OFFSET=0x5000\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_COUNTER_FREQUENCY=1000000000\n+CONFIG_ARMV8_MULTIENTRY=y\n+CONFIG_ARMV8_SET_SMPEN=y\n+CONFIG_ARMV8_SPIN_TABLE=y\n+CONFIG_SYS_CUSTOM_LDSCRIPT=y\n+CONFIG_SYS_LDSCRIPT=\"board/axiado/scm3005/u-boot.lds\"\n+CONFIG_BOOTDELAY=5\n+CONFIG_FIT=y\n+CONFIG_OF_BOARD_SETUP=y\n+CONFIG_USE_PREBOOT=y\n+CONFIG_DEFAULT_FDT_FILE=\"ax3005-scm3005.dtb\"\n+# CONFIG_DISPLAY_CPUINFO is not set\n+CONFIG_HUSH_PARSER=y\n+CONFIG_SYS_PROMPT=\"Axiado> \"\n+CONFIG_AUTOBOOT_KEYED=y\n+CONFIG_AUTOBOOT_PROMPT=\"Press \\\"<Esc><Esc>\\\" to stop autobooting in %d seconds\\n\"\n+CONFIG_AUTOBOOT_STOP_STR=\"\\x1b\\x1b\"\n+CONFIG_USE_BOOTARGS=y\n+CONFIG_BOOTARGS=\"console=ttyPS3,115200 maxcpus=4 nr_cpus=4 earlycon hugepages=16 root=/dev/ram rw phram.phram=ramrofs,0x80B00000,0x6400000\"\n+CONFIG_USE_BOOTCOMMAND=y\n+CONFIG_BOOTCOMMAND=\"bootm ${loadaddr}\"\n+CONFIG_SYS_VENDOR=\"axiado\"\n+CONFIG_SYS_BOARD=\"scm3005\"\n+CONFIG_SYS_CONFIG_NAME=\"ax3005-scm3005\"\n+# CONFIG_CMD_BOOTEFI is not set\n+# CONFIG_CMD_ELF is not set\n+# CONFIG_CMD_GO is not set\n+CONFIG_CMD_NVEDIT_EFI=y\n+CONFIG_CMD_MEMTEST=y\n+CONFIG_SYS_ALT_MEMTEST=y\n+CONFIG_CMD_CLK=y\n+CONFIG_CMD_DFU=y\n+CONFIG_CMD_DM=y\n+CONFIG_CMD_GPT=y\n+CONFIG_CMD_GPT_RENAME=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_TFTPPUT=y\n+CONFIG_CMD_CACHE=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_OF_CONTROL=y\n+CONFIG_OF_SEPARATE=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"ax3005-scm3005\"\n+CONFIG_MULTI_DTB_FIT=y\n+# CONFIG_ENV_IS_IN_MMC is not set\n+CONFIG_DM_MMC=y\n+# CONFIG_SUPPORT_EMMC_BOOT is not set\n+CONFIG_MMC_IO_VOLTAGE=y\n+CONFIG_MMC_UHS_SUPPORT=y\n+CONFIG_MMC_HS400_SUPPORT=y\n+CONFIG_TARGET_SCM3005=y\n+CONFIG_CLK=y\n+CONFIG_LZMA=y\n+CONFIG_XZ=y\n+CONFIG_ZYNQ_SERIAL=y\n+# CONFIG_AUTO_COMPLETE is not set\n+# CONFIG_SYS_LONGHELP is not set\n+# CONFIG_TOOLS_MKEFICAPSULE is not set\ndiff --git a/include/configs/ax3005-scm3005.h b/include/configs/ax3005-scm3005.h\nnew file mode 100644\nindex 00000000000..4eead2910c8\n--- /dev/null\n+++ b/include/configs/ax3005-scm3005.h\n@@ -0,0 +1,29 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+ */\n+\n+#ifndef __AX3005_SCM3005_H\n+#define __AX3005_SCM3005_H\n+\n+#include <linux/sizes.h>\n+\n+#define GICD_BASE\t\t0x40400000\n+#define GICR_BASE\t\t0x40500000\n+\n+#define SYS_TIMER_CTRL\t\t0x48016000\n+#define SYS_TIMER_ENABLE\t0x1\n+#define SYS_TIMER_DISABLE\t0x0\n+\n+/* DRAM: 2 GB at 0x80000000 */\n+#define CFG_SYS_SDRAM_BASE\t0x80000000\n+#define CFG_SYS_SDRAM_SIZE\tSZ_2G\n+#define CFG_SYS_INIT_SP_ADDR\t(CFG_SYS_SDRAM_BASE + SZ_1M)\n+\n+#define CFG_SYS_MAXARGS\t\t64\n+#define CFG_SYS_BARGSIZE\tCFG_SYS_CBSIZE\n+\n+#define CFG_SYS_BAUDRATE_TABLE\t\\\n+\t{ 4800, 9600, 19200, 38400, 57600, 115200 }\n+\n+#endif /* __AX3005_SCM3005_H */\n", "prefixes": [ "2/2" ] }