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GET /api/1.1/patches/2229980/?format=api
{ "id": 2229980, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229980/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428-ax3005_scm3005-v1-1-7fed19ee6fe0@axiado.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428-ax3005_scm3005-v1-1-7fed19ee6fe0@axiado.com>", "date": "2026-04-29T02:32:36", "name": "[1/2] arm64: dts: axiado: Add AX3005 SCM3005 device tree", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3fbc38f2146a212161d552cdad57b25a92365bb7", "submitter": { "id": 93280, "url": "http://patchwork.ozlabs.org/api/1.1/people/93280/?format=api", "name": "Karthikeyan Mitran", "email": "kmitran@axiado.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428-ax3005_scm3005-v1-1-7fed19ee6fe0@axiado.com/mbox/", "series": [ { "id": 501976, "url": "http://patchwork.ozlabs.org/api/1.1/series/501976/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501976", "date": "2026-04-29T02:32:35", "name": "Adding Axiado ax3005 based scm3005 board support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501976/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229980/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229980/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=axiado.com header.i=@axiado.com header.a=rsa-sha256\n header.s=selector1 header.b=OKaGBPm/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=axiado.com;", "Received-SPF": "Fail (protection.outlook.com: domain of axiado.com does not\n designate 64.62.143.114 as permitted sender) receiver=protection.outlook.com;\n client-ip=64.62.143.114; helo=smtp.corp.axiado.com;", "From": "Karthikeyan Mitran <kmitran@axiado.com>", "Date": "Tue, 28 Apr 2026 19:32:36 -0700", "Subject": "[PATCH 1/2] arm64: dts: axiado: Add AX3005 SCM3005 device tree", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260428-ax3005_scm3005-v1-1-7fed19ee6fe0@axiado.com>", "References": "<20260428-ax3005_scm3005-v1-0-7fed19ee6fe0@axiado.com>", "In-Reply-To": "<20260428-ax3005_scm3005-v1-0-7fed19ee6fe0@axiado.com>", "To": "u-boot@lists.denx.de", "Cc": "Tom Rini <trini@konsulko.com>, Siu Ming Tong <smtong@axiado.com>,\n Prasad Bolisetty <pbolisetty@axiado.com>,\n Andre Przywara <andre.przywara@arm.com>, Tzu-Hao Wei <twei@axiado.com>,\n Simon Glass <sjg@chromium.org>, Neil Armstrong <neil.armstrong@linaro.org>,\n Sumit Garg <sumit.garg@kernel.org>, Karthikeyan Mitran <kmitran@axiado.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; 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Ip=[64.62.143.114];\n Helo=[smtp.corp.axiado.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH1PEPF0000A345.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "SA1PR18MB4760", "X-Mailman-Approved-At": "Wed, 29 Apr 2026 04:43:59 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Siu Ming Tong <smtong@axiado.com>\n\nAdd device tree source files for the Axiado AX3005 SCM3005 board.\nThe AX3005 is a quad-core 64-bit ARMv8 Cortex-A53 SoC.\n\nThe DTSI describes the SoC-level nodes: GIC-v3 interrupt controller,\nCadence/Zynq UART, fixed reference clock, and spin-table secondary\nCPU boot. A /memreserve/ directive protects the spin-table release\naddress at 0x80002fa0 from being overwritten during boot.\n\nThe SCM3005 DTS sets the console to uart3 at 115200 baud and declares\n2 GB of DRAM starting at 0x80000000.\n\nTested-by: Siu Ming Tong <smtong@axiado.com>\nSigned-off-by: Siu Ming Tong <smtong@axiado.com>\nSigned-off-by: Tzu-Hao Wei <twei@axiado.com>\nSigned-off-by: Karthikeyan Mitran <kmitran@axiado.com>\n---\n arch/arm/dts/Makefile | 1 +\n arch/arm/dts/ax3005-scm3005.dts | 28 +++++++++++\n arch/arm/dts/ax3005.dtsi | 100 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 129 insertions(+)", "diff": "diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex bff341d6118..fcc62505987 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -4,6 +4,7 @@ dtb-$(CONFIG_TARGET_SMARTWEB) += at91sam9260-smartweb.dtb\n dtb-$(CONFIG_TARGET_TAURUS) += at91sam9g20-taurus.dtb\n dtb-$(CONFIG_TARGET_CORVUS) += at91sam9g45-corvus.dtb\n dtb-$(CONFIG_TARGET_GURNARD) += at91sam9g45-gurnard.dtb\n+dtb-$(CONFIG_TARGET_SCM3005) += ax3005-scm3005.dtb\n \n dtb-$(CONFIG_TARGET_SMDKC100) += s5pc1xx-smdkc100.dtb\n dtb-$(CONFIG_TARGET_S5P_GONI) += s5pc1xx-goni.dtb\ndiff --git a/arch/arm/dts/ax3005-scm3005.dts b/arch/arm/dts/ax3005-scm3005.dts\nnew file mode 100644\nindex 00000000000..b684602176c\n--- /dev/null\n+++ b/arch/arm/dts/ax3005-scm3005.dts\n@@ -0,0 +1,28 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+ */\n+\n+/dts-v1/;\n+\n+#include \"ax3005.dtsi\"\n+\n+/ {\n+\tmodel = \"Axiado AX3005 SCM3005\";\n+\tcompatible = \"axiado,ax3005-scm3005\", \"axiado,ax3005\";\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tchosen {\n+\t\tstdout-path = \"serial3:115200\";\n+\t};\n+\n+\tmemory@80000000 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x00 0x80000000 0x00 0x80000000>;\n+\t};\n+};\n+\n+&uart3 {\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/ax3005.dtsi b/arch/arm/dts/ax3005.dtsi\nnew file mode 100644\nindex 00000000000..6df2e4a821c\n--- /dev/null\n+++ b/arch/arm/dts/ax3005.dtsi\n@@ -0,0 +1,100 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (c) 2021-2026 Axiado Corporation (or its affiliates).\n+ */\n+\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/memreserve/ 0x80002fa0 0x00000008;\n+\n+/ {\n+\taliases {\n+\t\tserial3 = &uart3;\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x0 0x0>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0x80002fa0>;\n+\t\t};\n+\t\tcpu1: cpu@1 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x0 0x1>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0x80002fa0>;\n+\t\t};\n+\t\tcpu2: cpu@2 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x0 0x2>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0x80002fa0>;\n+\t\t};\n+\t\tcpu3: cpu@3 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x0 0x3>;\n+\t\t\tenable-method = \"spin-table\";\n+\t\t\tcpu-release-addr = <0x0 0x80002fa0>;\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupt-parent = <&gic500>;\n+\t\tinterrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,\n+\t\t\t <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,\n+\t\t\t <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,\n+\t\t\t <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;\n+\t\tclock-frequency = <1000000000>;\n+\t};\n+\n+\tclocks {\n+\t\trefclk: refclk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <125000000>;\n+\t\t\tbootph-pre-reloc;\n+\t\t};\n+\t};\n+\n+\tsoc: soc {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tinterrupt-parent = <&gic500>;\n+\t\tranges;\n+\n+\t\tgic500: interrupt-controller@40400000 {\n+\t\t\tcompatible = \"arm,gic-v3\";\n+\t\t\t#address-cells = <2>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tranges;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#redistributor-regions = <1>;\n+\t\t\treg = <0x00 0x40400000 0x00 0x10000>,\n+\t\t\t <0x00 0x40500000 0x00 0xc0000>;\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\n+\t\tuart3: serial@33020800 {\n+\t\t\tcompatible = \"cdns,uart-r1p12\", \"xlnx,xuartps\";\n+\t\t\tinterrupt-parent = <&gic500>;\n+\t\t\tinterrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\treg = <0x00 0x33020800 0x00 0x100>;\n+\t\t\tclock-names = \"uart_clk\", \"pclk\";\n+\t\t\tclocks = <&refclk &refclk>;\n+\t\t\tbootph-pre-reloc;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\t};\n+};\n", "prefixes": [ "1/2" ] }