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GET /api/1.1/patches/2229977/?format=api
{ "id": 2229977, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229977/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/a784563f-82e0-4de3-a2a9-4e9123e61125@hygon.cn/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<a784563f-82e0-4de3-a2a9-4e9123e61125@hygon.cn>", "date": "2026-04-29T02:25:46", "name": "[v2] i386: Support HYGON c86-4g series processors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "30829fd9015ad4a79ece7708e6754487c9ac45c2", "submitter": { "id": 92962, "url": "http://patchwork.ozlabs.org/api/1.1/people/92962/?format=api", "name": "Kewen Lin", "email": "linkewen@hygon.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/a784563f-82e0-4de3-a2a9-4e9123e61125@hygon.cn/mbox/", "series": [ { "id": 501974, "url": "http://patchwork.ozlabs.org/api/1.1/series/501974/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501974", "date": "2026-04-29T02:25:46", "name": "[v2] i386: Support HYGON c86-4g series processors", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501974/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229977/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229977/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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Wed, 29 Apr 2026 02:26:11 +0000 (GMT)", "from maildlp1.hygon.cn (unknown [127.0.0.1])\n by mailgw1.hygon.cn (Postfix) with ESMTP id 4g51Pl4dd7zvbvD;\n Wed, 29 Apr 2026 10:26:03 +0800 (CST)", "from maildlp1.hygon.cn (unknown [172.23.18.60])\n by mailgw1.hygon.cn (Postfix) with ESMTP id 4g51Pj0Q1XzvbvD;\n Wed, 29 Apr 2026 10:26:01 +0800 (CST)", "from cncheex05.Hygon.cn (unknown [172.23.18.115])\n by maildlp1.hygon.cn (Postfix) with ESMTPS id 7304878B3;\n Wed, 29 Apr 2026 10:25:55 +0800 (CST)", "from cncheex04.Hygon.cn (172.23.18.114) by cncheex05.Hygon.cn\n (172.23.18.115) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Wed, 29 Apr\n 2026 10:25:46 +0800", "from cncheex04.Hygon.cn ([fe80::1b6f:6c58:58a4:430d]) by\n cncheex04.Hygon.cn ([fe80::1b6f:6c58:58a4:430d%10]) with mapi id\n 15.02.1544.036; Wed, 29 Apr 2026 10:25:46 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org B06CD4BB8F67", "OpenDKIM Filter v2.11.0 sourceware.org 790EE4BB1C0C" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 790EE4BB1C0C", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 790EE4BB1C0C", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1777429573; cv=none;\n b=TFslkuJhub9cEh10JJBoQFDR4yZfHAzW0cD5f0vSclxQjWaLNRaHm7F0Al5o9eB1rV8RlaYROoXYz9JavwpCTXLK2o3sI/lquqo33Dye1l3FkbZrBU79JontSLDI6C3nFGce7xZFnVbUP0FpdgyFd9PWnB4VIfYWGzXmvjntdW8=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1777429573; c=relaxed/simple;\n bh=7c9ybYgmVLK6GUoUmDPPTkL+ydpK2KTz/juDLcDgK0E=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=a+0AJVLVwgekEDkTtJRiALgBNXnivJxobxTbobDP34PnbASyX02/e2DCCb0rAyLs8uNxjuakwlboBvT63/agYR1sAZueuUs5q/UhUD9ZUZhttT+2z+4syoSR5cmBLITNJxvDUNh4s0/dgoY3oPzyK56PlMSF3n0HAPGLVTUQwA4=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Kewen Lin <linkewen@hygon.cn>", "To": "Uros Bizjak <ubizjak@gmail.com>", "CC": "\"gcc-patches@gcc.gnu.org\" <gcc-patches@gcc.gnu.org>, Liulxx\n <liulxx@hygon.cn>, Qingkuan Lai <laiqingkuan@hygon.cn>, Feng Xue\n <xuefeng@hygon.cn>, \"hubicka@ucw.cz\" <hubicka@ucw.cz>,\n \"hongtao.liu@intel.com\" <hongtao.liu@intel.com>, Kewen Lin\n <linkewen@hygon.cn>", "Subject": "[PATCH v2] i386: Support HYGON c86-4g series processors", "Thread-Topic": "[PATCH v2] i386: Support HYGON c86-4g series processors", "Thread-Index": "AQHc13986h3tGwfOk0yYa7RzDE/5EA==", "Date": "Wed, 29 Apr 2026 02:25:46 +0000", "Message-ID": "<a784563f-82e0-4de3-a2a9-4e9123e61125@hygon.cn>", "References": "<387794d9-199a-4373-97be-5e70e772e014@hygon.cn>\n <CAFULd4brt7kwJ7PRm0NjajD0jO63wRV+kdoo9rRorQvTYV8sfg@mail.gmail.com>", "In-Reply-To": "\n <CAFULd4brt7kwJ7PRm0NjajD0jO63wRV+kdoo9rRorQvTYV8sfg@mail.gmail.com>", "Accept-Language": "zh-CN, en-US", "Content-Language": "zh-CN", "X-MS-Has-Attach": "yes", "X-MS-TNEF-Correlator": "", "x-originating-ip": "[172.19.23.14]", "Content-Type": "multipart/mixed;\n boundary=\"_002_a784563f82e04de3a2a94e9123e61125hygoncn_\"", "MIME-Version": "1.0", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hi Uros,\n\n在 2026/4/28 15:46, Uros Bizjak 写道:\n> On Wed, Mar 25, 2026 at 7:17 AM Kewen Lin <linkewen@hygon.cn> wrote:\n>>\n>> Hi,\n>>\n>> This patch enables new x86 CPU vendor HYGON ID detection\n>> and adds c86-4g series c86-4g-m{4,6,7} processor supports.\n>> Without such support, if users use -march=native option on\n>> HYGON machines, they can get some old arch like core2, it\n>> would be suboptimal. It also enables -m{arch,tune}=c86-4g\n>> -m{4,6,7} supports. Based on the hardware characteristics,\n>> appropriate cost models and tuning parameters are provided.\n>>\n>> New machine description files are introduced: c86-4g.md is\n>> used to describe the pipeline for c86-4g-m4 and c86-4g-m6,\n>> while c86-4g-m7.md describes the pipeline for c86-4g-m7.\n>> To better model some pipeline information, it introduces\n>> new attrs c86_attr and c86_decode by following existing\n>> practice.\n>>\n>> Bootstrapped and regtested on hygon c86-4g-m4 and c86-4g-m7\n>> machine, as well as a cfarm x86-64 machine.\n>>\n>> It's late stage 4 now, I guess it has to be next stage 1\n>> materials? If so, is it ok for trunk once gcc-17 stage1\n>> opens?\n>>\n>> BR,\n>> Kewen\n>> -----\n>>\n>> From: Xin Liu <liulxx@hygon.cn>\n>> Co-authored-by: Zhaoling Bao <baozhaoling@hygon.cn>\n>> Signed-off-by: Xin Liu <liulxx@hygon.cn>\n>> Signed-off-by: Zhaoling Bao <baozhaoling@hygon.cn>\n>>\n>> gcc/ChangeLog:\n[snip]\n>> gcc/testsuite/ChangeLog:\n>>\n>> * gcc.target/i386/builtin_target.c: Add handling for HYGON CPUs by\n>> validating the vendor and invoking HYGON-specific CPU detection.\n>> * gcc.target/i386/funcspec-56.inc: Test function target attribute on\n>> {arch,tune}=c86-4g-m{4,6,7}.\n>> * g++.target/i386/mv33.C: New test.\n> \n> I didn't look at the new .md files and mostly mechanical changes in\n> .md files in detail, they all look good to me modulo some issues,\n> noticed below. Target specific tune definitions and costs also LGTM.\n> Common code follows established practices and is also well tested in\n> the testsuite.\n> \n> + (set (attr \"c86_attr\")\n> + (cond [(eq_attr \"alternative\" \"2,3\")\n> + (const_string \"sselogic\")\n> + ]\n> + (const_string \"*\")))\n> \n> the above can be simplified with if_then_else, which is preferred RTX\n> for single cond RTX:\n> \n> (set (attr \"c86_attr\")\n> (if_then_else (eq_attr \"alternative\" \"2,3\")\n> (const_string \"sselogic\")\n> (const_string \"*\")))\n> \n> here and at other places.\n> \n> + (set (attr \"c86_attr\")\n> + (cond [(eq_attr \"alternative\" \"8,9,10,11\")\n> + (if_then_else (and (match_test \"SSE_REG_P (operands[0])\")\n> + (match_test \"SSE_REG_P (operands[1])\"))\n> + (const_string \"vpmovx\")\n> + (const_string \"*\"))\n> + ]\n> + (const_string \"*\")))\n> \n> The above change applies to:\n> \n> (define_insn \"*zero_extendsidi2\"\n> [(set (match_operand:DI 0 \"nonimmediate_operand\"\n> \"=r,?r,?o,r ,o,?*y,?!*y,$r,$v,$x,*x,*v,?r,?k\")\n> (zero_extend:DI\n> (match_operand:SI 1 \"x86_64_zext_operand\"\n> \"0 ,rm,r ,rmWz,0,r ,m ,v ,r ,m ,*x,*v,?k,?km\")))]\n> \n> but both operands are SSE_REG_P only for alternatives 10 and 11, so\n> the above test can be simplified to just:\n> \n> (set (attr \"c86_attr\")\n> (if_then_else (eq_attr \"alternative\" \"10,11\")\n> (const_string \"vpmovx\")\n> (const_string \"*\")))\n> \n> Other than that, the patch is OK.\n\nThanks for the review!!\n\nThere are some changes in v2 comparing to v1:\n - In function host_detect_local_cpu: relaxed CPU model check\n from model == 7 to model >= 7 to make any potential future\n model adopt M7 at least.\n - Replaced multiple uses of cond with if_then_else where only\n a single condition is involved as suggested.\n - Removed redundant checks as alternative constraints ensure\n as suggested.\n - Fixed a few alignment formatting issues on c86_attr lines in mds.\n - Removed some unnecessary empty lines.\n\nBootstrapped and regtested as before.\n\nIs it ok for trunk?\n\nBR,\nKewen\n-----\nSubject: [PATCH] i386: Support HYGON c86-4g series processors\n\nThis patch enables new x86 CPU vendor HYGON ID detection\nand adds c86-4g series c86-4g-m{4,6,7} processor supports.\nWithout such support, if users use -march=native option on\nHYGON machines, they can get some old arch like core2, it\nwould be suboptimal. It also enables -m{arch,tune}=c86-4g\n-m{4,6,7} supports. Based on the hardware characteristics,\nappropriate cost models and tuning parameters are provided.\n\nNew machine description files are introduced: c86-4g.md is\nused to describe the pipeline for c86-4g-m4 and c86-4g-m6,\nwhile c86-4g-m7.md describes the pipeline for c86-4g-m7.\nTo better model some pipeline information, it introduces\nnew attrs c86_attr and c86_decode by following existing\npractice.\n\nBootstrapped and regtested on hygon c86-4g-m4 and c86-4g-m7\nmachine, as well as a cfarm x86-64 machine.\n\nFrom: Xin Liu <liulxx@hygon.cn>\nCo-authored-by: Zhaoling Bao <baozhaoling@hygon.cn>\nSigned-off-by: Xin Liu <liulxx@hygon.cn>\nSigned-off-by: Zhaoling Bao <baozhaoling@hygon.cn>\n\ngcc/ChangeLog:\n\n\t* common/config/i386/cpuinfo.h (get_hygon_cpu): Detect the specific\n\ttype of HYGON CPU and return HYGON CPU name.\n\t(cpu_indicator_init): Handle HYGON CPU.\n\t* common/config/i386/i386-common.cc (processor_names): Add HYGON\n\tC86-4G processors c86-4g-m{4,6,7}.\n\t(processor_alias_table): Add hygon, hygonfam18h and c86-4g-m{4,6,7}\n\tentries.\n\t(ARRAY_SIZE): Update as new entries added.\n\t* common/config/i386/i386-cpuinfo.h (enum processor_vendor): Add\n\tVENDOR_HYGON.\n\t(enum processor_types): Add HYGONFAM18H.\n\t(enum processor_subtypes): Add HYGONFAM18H_C86_4G_M{4,6,7}.\n\t* config.gcc: Add support for c86_4g_m{4,6,7}.\n\t* config/i386/cpuid.h (signature_HYGON_ebx): Add signature for HYGON.\n\t(signature_HYGON_ecx): Ditto.\n\t(signature_HYGON_edx): Ditto.\n\t* config/i386/driver-i386.cc (host_detect_local_cpu): Support HYGON\n\tc86-4g-m4{4,6,7} processors.\n\t* config/i386/i386-c.cc (ix86_target_macros_internal): Ditto.\n\t* config/i386/i386-options.cc (m_C86_4G_M4): New definition.\n\t(m_C86_4G_M6): Ditto.\n\t(m_C86_4G_M7): Ditto.\n\t(m_C86_4G): Ditto.\n\t(processor_cost_table): Add cost entries for c86-4g-m4{4,6,7}.\n\t* config/i386/i386.cc (ix86_reassociation_width): Add handlings for\n\tPROCESSOR_C86_4G_M{4,6,7}.\n\t* config/i386/i386.h (enum processor_type): Define\n\tPROCESSOR_C86_4G_M{4,6,7}.\n\t(PTA_C86_4G_M4): New define.\n\t(PTA_C86_4G_M6): Ditto.\n\t(PTA_C86_4G_M7): Ditto.\n\t* config/i386/x86-tune-costs.h (c86_4g_m4_memcpy): New stringop_algs.\n\t(c86_4g_m4_cost): New processor_costs.\n\t(c86_4g_m6_cost): Ditto.\n\t(c86_4g_m7_cost): Ditto.\n\t* config/i386/x86-tune-sched.cc (ix86_issue_rate): Handle\n\tPROCESSOR_C86_4G_M{4,6,7}.\n\t(ix86_adjust_cost): Ditto.\n\t* config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Handle m_C86_4G.\n\t(X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto.\n\t(X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto.\n\t(X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto.\n\t(X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto.\n\t(X86_TUNE_MEMORY_MISMATCH_STALL): Ditto.\n\t(X86_TUNE_FUSE_CMP_AND_BRANCH_32): Ditto.\n\t(X86_TUNE_FUSE_CMP_AND_BRANCH_64): Ditto.\n\t(X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS): Ditto.\n\t(X86_TUNE_USE_LEAVE): Ditto.\n\t(X86_TUNE_PUSH_MEMORY): Ditto.\n\t(X86_TUNE_INTEGER_DFMODE_MOVES): Ditto.\n\t(X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto.\n\t(X86_TUNE_USE_SAHF): Ditto.\n\t(X86_TUNE_USE_BT): Ditto.\n\t(X86_TUNE_AVOID_MFENCE): Ditto.\n\t(X86_TUNE_USE_FFREEP): Ditto.\n\t(X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto.\n\t(X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL): Ditto.\n\t(X86_TUNE_SSE_TYPELESS_STORES): Ditto.\n\t(X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto.\n\t(X86_TUNE_USE_GATHER_2PARTS): Ditto.\n\t(X86_TUNE_USE_GATHER_4PARTS): Ditto.\n\t(X86_TUNE_USE_GATHER_8PARTS): Ditto.\n\t(X86_TUNE_AVOID_128FMA_CHAINS): Ditto.\n\t(X86_TUNE_AVOID_256FMA_CHAINS): Ditto.\n\t(X86_TUNE_USE_RCR): Ditto.\n\t(X86_TUNE_AVX256_MOVE_BY_PIECES): Handle m_C86_4G_M{4,6}.\n\t(X86_TUNE_USE_SCATTER_2PARTS): Handle m_C86_4G_M7.\n\t(X86_TUNE_USE_SCATTER_4PARTS): Ditto.\n\t(X86_TUNE_USE_SCATTER_8PARTS): Ditto.\n\t(X86_TUNE_SSE_REDUCTION_PREFER_PSHUF): Ditto.\n\t(X86_TUNE_AVX512_SPLIT_REGS): Ditto.\n\t(X86_TUNE_AVX512_MOVE_BY_PIECES): Ditto.\n\t(X86_TUNE_AVX512_MASKED_EPILOGUES): Ditto.\n\t* doc/extend.texi: Document about hygonfam18h and c86-4g-m{4,6,7}.\n\t* doc/invoke.texi: Document about c86-4g-m{4,6,7}.\n\t* config/i386/c86-4g-m7.md: New file for c86-4g-m7 scheduling model\n\tinformation.\n\t* config/i386/c86-4g.md: New file for c86-4g-m{4,6} scheduling model\n\tinformation.\n\t* config/i386/i386.md (cpu attr): Add c86_4g_m{4,6,7}.\n\t(c86-4g.md): New include.\n\t(c86-4g-m7.md): Ditto.\n\t(*cmpi<unord>xf_i387): Set attr c86_decode.\n\t(*cmpi<unord><MODEF:mode>): Ditto.\n\t(swap<mode>): Ditto.\n\t(*swap<mode>): Ditto.\n\t(extendhisi2): Ditto.\n\t(floathi<mode>2): Ditto.\n\t(float<SWI48x:mode>xf2): Ditto.\n\t(*float<SWI48:mode><MODEF:mode>2): Ditto.\n\t(*floatdi<MODEF:mode>2_i387): Ditto.\n\t(*anddi_1_bt): Ditto.\n\t(*iordi_1_bts): Ditto.\n\t(*xordi_1_btc): Ditto.\n\t(*<btsc><mode>): Ditto.\n\t(*btr<mode>): Ditto.\n\t(*btsq_imm): Ditto.\n\t(*btrq_imm): Ditto.\n\t(*btcq_imm): Ditto.\n\t(*tzcnt<mode>_1): Ditto.\n\t(*tzcnt<mode>_1_falsedep): Ditto.\n\t(*bsf<mode>_1): Ditto.\n\t(*ctz<mode>2_falsedep): Ditto.\n\t(*ctzsi2_zext): Ditto.\n\t(*ctzsi2_zext_falsedep): Ditto.\n\t(bsr_rex64): Ditto.\n\t(bsr_rex64_1): Ditto.\n\t(bsr_rex64_1_zext): Ditto.\n\t(bsr): Ditto.\n\t(bsr_1): Ditto.\n\t(bsr_zext_1): Ditto.\n\t(*bswaphi2_movbe): Ditto.\n\t(*bswaphi2): Ditto.\n\t(bswaphisi2_lowpart): Ditto.\n\t(fpremxf4_i387): Ditto.\n\t(fprem1xf4_i387): Ditto.\n\t(<sincos>xf2): Ditto.\n\t(sincosxf3): Ditto.\n\t(fptanxf4_i387): Ditto.\n\t(atan2xf3): Ditto.\n\t(fyl2xxf3_i387): Ditto.\n\t(fyl2xp1xf3_i387): Ditto.\n\t(fxtractxf3_i387): Ditto.\n\t(*f2xm1xf2_i387): Ditto.\n\t(fscalexf4_i387): Ditto.\n\t(rintxf2): Ditto.\n\t(*movxi_internal_avx512f): Set attr c86_attr.\n\t(*movoi_internal_avx): Ditto.\n\t(*movti_internal): Ditto.\n\t(*movdi_internal): Ditto.\n\t(*movsi_internal): Ditto.\n\t(*movhi_internal): Ditto.\n\t(*movtf_internal): Ditto.\n\t(*movdf_internal): Ditto.\n\t(*movsf_internal): Ditto.\n\t(*zero_extendsidi2): Ditto.\n\t(sqrtxf2): Ditto.\n\t(<smaxmin:code><mode>3): Ditto.\n\t(*ieee_s<ieee_maxmin><mode>3): Ditto.\n\t* config/i386/mmx.md (*mmx_maskmovq): Set attr c86_decode.\n\t(*mmx_maskmovq): Ditto.\n\t(sse_movntq): Set attr c86_attr.\n\t(*mmx_blendps): Ditto.\n\t(mmx_blendvps): Ditto.\n\t(*mmx_pmaddwd): Ditto.\n\t(mmx_pblendvb_v8qi): Ditto.\n\t(mmx_pblendvb_<mode>): Ditto.\n\t(sse4_1_<code>v4qiv4hi2): Ditto.\n\t(sse4_1_<code>v2hiv2si2): Ditto.\n\t(sse4_1_<code>v2qiv2si2): Ditto.\n\t(sse4_1_<code>v2qiv2hi2): Ditto.\n\t(*mmx_pinsrd): Ditto.\n\t(*mmx_pinsrw): Ditto.\n\t(*mmx_pinsrb): Ditto.\n\t(*mmx_pextrw): Ditto.\n\t(*mmx_pextrw<mode>): Ditto.\n\t(*mmx_pextrw_zext): Ditto.\n\t(*mmx_pextrb): Ditto.\n\t(*mmx_pextrb_zext): Ditto.\n\t(*mmx_pblendw64): Ditto.\n\t(*mmx_pblendw32): Ditto.\n\t(*vec_extractv2si_1): Ditto.\n\t(*vec_extractv2si_1_zext): Ditto.\n\t(*pinsrw): Ditto.\n\t(*pinsrb): Ditto.\n\t(*pextrw): Ditto.\n\t(*pextrw<mode>): Ditto.\n\t(*pextrw_zext): Ditto.\n\t(*pextrb): Ditto.\n\t(*pextrb_zext): Ditto.\n\t(*mmx_psadbw): Ditto.\n\t* config/i386/sse.md (ktest<mode>): Set attr c86_decode.\n\t(*kortest<mode>): Ditto.\n\t(sse_cvtsi2ss<rex64namesuffix><round_name>): Ditto.\n\t(sse2_cvtsi2sd): Ditto.\n\t(sse2_maskmovdqu): Ditto.\n\t(*<sse>_dp<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(*<sse4_1_avx2>_mpsadbw): Ditto.\n\t(pclmulqdq): Ditto.\n\t(<mask_codefor>conflict<mode><mask_name>): Ditto.\n\t(<avx512>_blendm<mode>): Set attr c86_attr.\n\t(sse2_movnti<mode>): Ditto.\n\t(<sse>_movnt<mode>): Ditto.\n\t(<sse2>_movnt<mode>): Ditto.\n\t(<sse>_rcp<mode>2): Ditto.\n\t(sse_vmrcpv4sf2): Ditto.\n\t(<mask_codefor>rcp14<mode><mask_name>): Ditto.\n\t(srcp14<mode>): Ditto.\n\t(srcp14<mode>_mask): Ditto.\n\t(<sse>_sqrt<mode>2<mask_name><round_name>): Ditto.\n\t(<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.\n\t(*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>): Ditto.\n\t(<mask_codefor>rsqrt14<mode><mask_name>): Ditto.\n\t(rsqrt14<mode>): Ditto.\n\t(rsqrt14_<mode>_mask\"): Ditto.\n\t(*<code><mode>3<mask_name><round_saeonly_name>): Ditto.\n\t(ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>): Ditto.\n\t(*<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name>):\n\tDitto.\n\t(<sse>_ieee_vm<ieee_maxmin><mode>3<mask_scalar_name>\n\t<round_saeonly_scalar_name>): Ditto.\n\t(*ieee_<ieee_maxmin><mode>3): Ditto.\n\t(avx_h<insn>v4df3): Ditto.\n\t(*sse3_haddv2df3): Ditto.\n\t(sse3_hsubv2df3): Ditto.\n\t(*sse3_haddv2df3_low): Ditto.\n\t(*sse3_hsubv2df3_low): Ditto.\n\t(avx_h<insn>v8sf3): Ditto.\n\t(sse3_h<insn>v4sf3): Ditto.\n\t(*<mask_codefor>reducep<mode><mask_name><round_saeonly_name>): Ditto.\n\t(reduces<mode><mask_scalar_name><round_saeonly_scalar_name>): Ditto.\n\t(*<avx512>_eq<mode>3<mask_scalar_merge_name>_1): Ditto.\n\t(<sse>_andnot<mode>3<mask_name>): Ditto.\n\t(*<code><mode>3<mask_name>): Ditto.\n\t(*andnot<mode>3): Ditto.\n\t(<code><mode>3): Ditto.\n\t(*<code>tf3): Ditto.\n\t(vec_set<mode>_0): Ditto.\n\t(@vec_set<mode>_0): Ditto.\n\t(*sse4_1_extractps): Ditto.\n\t(vec_extract<mode>): Ditto.\n\t(<mask_codefor><avx512>_align<mode><mask_name>): Ditto.\n\t(avx512bw_pmaddwd512<mode><mask_name>): Ditto.\n\t(*avx2_pmaddw): Ditto.\n\t(*sse2_pmaddwd): Ditto.\n\t(*avx2_<code><mode>3): Ditto.\n\t(*avx512f_<code><mode>3<mask_name>): Ditto.\n\t(*avx512bw_<code><mode>3<mask_name>): Ditto.\n\t(*sse4_1_<code><mode>3<mask_name>): Ditto.\n\t(*<code>v8hi3): Ditto.\n\t(*<code>v16qi3): Ditto.\n\t(*andnot<mode>3_mask): Ditto.\n\t(*<code><mode>3): Ditto.\n\t(<code>v1ti3): Ditto.\n\t(<sse2p4_1>_pinsr<ssemodesuffix>): Ditto.\n\t(*<extract_type>_vinsert<shuffletype><extract_suf>_0): Ditto.\n\t(<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>\n\t_1<mask_name>): Ditto.\n\t(vec_set_lo_<mode><mask_name>): Ditto.\n\t(vec_set_hi_<mode><mask_name>): Ditto.\n\t(<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>): Ditto.\n\t(avx512f_shuf_<shuffletype>64x2_1<mask_name>): Ditto.\n\t(*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1): Ditto.\n\t(avx512vl_shuf_<shuffletype>32x4_1<mask_name>): Ditto.\n\t(avx512f_shuf_<shuffletype>32x4_1<mask_name>): Ditto.\n\t(*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1): Ditto.\n\t(*vec_extract<mode>): Ditto.\n\t(*vec_extract<PEXTR_MODE12:mode>_zext): Ditto.\n\t(*vec_extractv16qi_zext): Ditto.\n\t(*vec_extractv4si): Ditto.\n\t(*vec_extractv4si_zext): Ditto.\n\t(*vec_extractv2di_1): Ditto.\n\t(*vec_concatv2si_sse4_1): Ditto.\n\t(vec_concatv2di): Ditto.\n\t(*<sse2_avx2>_uavg<mode>3<mask_name>): Ditto.\n\t(*<sse2_avx2>_psadbw): Ditto.\n\t(<sse>_movmsk<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext): Ditto.\n\t(<sse2_avx2>_pmovmskb): Ditto.\n\t(*<sse2_avx2>_pmovmskb_zext): Ditto.\n\t(*sse2_maskmovdqu): Ditto.\n\t(avx2_ph<plusminus_mnemonic>wv16hi3): Ditto.\n\t(ssse3_ph<plusminus_mnemonic>wv8hi3): Ditto.\n\t(ssse3_ph<plusminus_mnemonic>dv4si3): Ditto.\n\t(avx2_ph<plusminus_mnemonic>dv8si3): Ditto.\n\t(avx2_pmaddubsw256): Ditto.\n\t(avx512bw_pmaddubsw512<mode><mask_name>): Ditto.\n\t(ssse3_pmaddubsw128): Ditto.\n\t(<ssse3_avx2>_psign<mode>3): Ditto.\n\t(ssse3_psign<mode>3): Ditto.\n\t(*abs<mode>2): Ditto.\n\t(abs<mode>2_mask): Ditto.\n\t(abs<mode>2_mask): Ditto.\n\t(sse4a_movnt<mode>): Ditto.\n\t(sse4a_vmmovnt<mode>): Ditto.\n\t(<sse4_1>_blend<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(sse4_1_blendv<ssemodesuffix>): Ditto.\n\t(<vi8_sse4_1_avx2_avx512>_movntdqa): Ditto.\n\t(<sse4_1_avx2>_pblendvb): Ditto.\n\t(sse4_1_pblend<ssemodesuffix>): Ditto.\n\t(*avx2_pblend<ssemodesuffix>): Ditto.\n\t(avx2_pblendd<mode>): Ditto.\n\t(avx2_<code>v16qiv16hi2<mask_name>): Ditto.\n\t(avx512bw_<code>v32qiv32hi2<mask_name>): Ditto.\n\t(sse4_1_<code>v8qiv8hi2<mask_name>): Ditto.\n\t(*sse4_1_<code>v8qiv8hi2<mask_name>_1): Ditto.\n\t(<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>): Ditto.\n\t(avx2_<code>v8qiv8si2<mask_name>): Ditto.\n\t(*avx2_<code>v8qiv8si2<mask_name>_1): Ditto.\n\t(sse4_1_<code>v4qiv4si2<mask_name>): Ditto.\n\t(*sse4_1_<code>v4qiv4si2<mask_name>_1): Ditto.\n\t(avx512f_<code>v16hiv16si2<mask_name>): Ditto.\n\t(avx2_<code>v8hiv8si2<mask_name>): Ditto.\n\t(sse4_1_<code>v4hiv4si2<mask_name>): Ditto.\n\t(*sse4_1_<code>v4hiv4si2<mask_name>_1): Ditto.\n\t(avx512f_<code>v8qiv8di2<mask_name>): Ditto.\n\t(*avx512f_<code>v8qiv8di2<mask_name>_1): Ditto.\n\t(avx2_<code>v4qiv4di2<mask_name>): Ditto.\n\t(*avx2_<code>v4qiv4di2<mask_name>_1): Ditto.\n\t(sse4_1_<code>v2qiv2di2<mask_name>): Ditto.\n\t(*sse4_1_<code>v2qiv2di2<mask_name>_1): Ditto.\n\t(avx512f_<code>v8hiv8di2<mask_name>): Ditto.\n\t(avx2_<code>v4hiv4di2<mask_name>): Ditto.\n\t(*avx2_<code>v4hiv4di2<mask_name>_1): Ditto.\n\t(sse4_1_<code>v2hiv2di2<mask_name>): Ditto.\n\t(*sse4_1_<code>v2hiv2di2<mask_name>_1): Ditto.\n\t(avx512f_<code>v8siv8di2<mask_name>): Ditto.\n\t(avx2_<code>v4siv4di2<mask_name>): Ditto.\n\t(sse4_1_<code>v2siv2di2<mask_name>): Ditto.\n\t(*sse4_1_<code>v2siv2di2<mask_name>_1): Ditto.\n\t(sse4_1_round<ssescalarmodesuffix>): Ditto.\n\t(*sse4_1_round<ssescalarmodesuffix>\"): Ditto.\n\t(sse4_2_pcmpestri): Ditto.\n\t(sse4_2_pcmpestrm): Ditto.\n\t(sse4_2_pcmpestr_cconly): Ditto.\n\t(sse4_2_pcmpistri): Ditto.\n\t(sse4_2_pcmpistrm): Ditto.\n\t(sse4_2_pcmpistr_cconly): Ditto.\n\t(xop_phadd<u>bw): Ditto.\n\t(xop_phadd<u>bd): Ditto.\n\t(xop_phadd<u>bq): Ditto.\n\t(xop_phadd<u>wd): Ditto.\n\t(xop_phadd<u>wq): Ditto.\n\t(xop_phadd<u>dq): Ditto.\n\t(xop_phsubbw): Ditto.\n\t(xop_phsubwd): Ditto.\n\t(xop_phsubdq): Ditto.\n\t(aesenc): Ditto.\n\t(aesenclast): Ditto.\n\t(aesdec): Ditto.\n\t(aesdeclast): Ditto.\n\t(aesimc): Ditto.\n\t(aeskeygenassist): Ditto.\n\t(<avx2_avx512>_permvar<mode><mask_name>): Ditto.\n\t(avx2_perm<mode>_1<mask_name>): Ditto.\n\t(<avx512>_permvar<mode><mask_name>): Ditto.\n\t(avx512f_perm<mode>_1<mask_name>): Ditto.\n\t(<mask_codefor>avx512f_broadcast<mode><mask_name>): Ditto.\n\t(avx_vbroadcastf128_<mode>): Ditto.\n\t(<mask_codefor>avx512vl_broadcast<mode><mask_name>_1): Ditto.\n\t(<mask_codefor>avx512dq_broadcast<mode><mask_name>_1): Ditto.\n\t(*<avx512>_vpermi2var<mode>3_mask): Ditto.\n\t(<avx512>_vpermt2var<mode>3<sd_maskz_name>): Ditto.\n\t(<avx512>_vpermt2var<mode>3_mask): Ditto.\n\t(*avx_vperm2f128<mode>_nozero): Ditto.\n\t(vec_set_lo_<mode><mask_name>): Ditto.\n\t(vec_set_hi_<mode><mask_name>): Ditto.\n\t(vec_set_lo_<mode>): Ditto.\n\t(vec_set_hi_<mode>): Ditto.\n\t(vec_set_lo_v32qi): Ditto.\n\t(<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>): Ditto.\n\t(avx_vec_concat<mode>): Ditto.\n\t(<avx512>_compress<mode>_mask): Ditto.\n\t(compress<mode>_mask): Ditto.\n\t(<avx512>_compressstore<mode>_mask): Ditto.\n\t(compressstore<mode>_mask): Ditto.\n\t(expand<mode>_mask): Ditto.\n\t(<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>): Ditto.\n\t(clz<mode>2<mask_name>): Ditto.\n\t(vpmadd52<vpmadd52type>v8di): Ditto.\n\t(vpmadd52<vpmadd52type><mode>): Ditto.\n\t(vpmadd52<vpmadd52type><mode>_maskz_1): Ditto.\n\t(vpmadd52<vpmadd52type><mode>_mask): Ditto.\n\t(vaesdec_<mode>): Ditto.\n\t(vaesdeclast_<mode>): Ditto.\n\t(vaesenc_<mode>): Ditto.\n\t(vaesenclast_<mode>): Ditto.\n\ngcc/testsuite/ChangeLog:\n\n\t* gcc.target/i386/builtin_target.c: Add handling for HYGON CPUs by\n\tvalidating the vendor and invoking HYGON-specific CPU detection.\n\t* gcc.target/i386/funcspec-56.inc: Test function target attribute on\n\t{arch,tune}=c86-4g-m{4,6,7}.\n\t* g++.target/i386/mv33.C: New test.\n---\n gcc/common/config/i386/cpuinfo.h | 57 +\n gcc/common/config/i386/i386-common.cc | 20 +-\n gcc/common/config/i386/i386-cpuinfo.h | 5 +\n gcc/config.gcc | 26 +-\n gcc/config/i386/c86-4g-m7.md | 1996 +++++++++++++++++\n gcc/config/i386/c86-4g.md | 1204 ++++++++++\n gcc/config/i386/cpuid.h | 4 +\n gcc/config/i386/driver-i386.cc | 19 +\n gcc/config/i386/i386-c.cc | 22 +-\n gcc/config/i386/i386-options.cc | 9 +-\n gcc/config/i386/i386.cc | 5 +-\n gcc/config/i386/i386.h | 18 +\n gcc/config/i386/i386.md | 85 +-\n gcc/config/i386/mmx.md | 31 +\n gcc/config/i386/sse.md | 238 ++\n gcc/config/i386/x86-tune-costs.h | 300 +++\n gcc/config/i386/x86-tune-sched.cc | 6 +\n gcc/config/i386/x86-tune.def | 85 +-\n gcc/doc/extend.texi | 12 +\n gcc/doc/invoke.texi | 21 +\n gcc/testsuite/g++.target/i386/mv33.C | 42 +\n .../gcc.target/i386/builtin_target.c | 6 +\n gcc/testsuite/gcc.target/i386/funcspec-56.inc | 6 +\n 23 files changed, 4172 insertions(+), 45 deletions(-)\n create mode 100644 gcc/config/i386/c86-4g-m7.md\n create mode 100644 gcc/config/i386/c86-4g.md\n create mode 100644 gcc/testsuite/g++.target/i386/mv33.C", "diff": "diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h\nindex 583e0acf8..62e9210b0 100644\n--- a/gcc/common/config/i386/cpuinfo.h\n+++ b/gcc/common/config/i386/cpuinfo.h\n@@ -349,6 +349,48 @@ get_amd_cpu (struct __processor_model *cpu_model,\n return cpu;\n }\n \n+/* Get the specific type of HYGON CPU and return HYGON CPU name. Return\n+ NULL for unknown HYGON CPU. */\n+\n+static inline const char *\n+get_hygon_cpu (struct __processor_model *cpu_model,\n+\t struct __processor_model2 *cpu_model2,\n+\t unsigned int *cpu_features2 __attribute__((unused)))\n+{\n+ const char *cpu = NULL;\n+ unsigned int family = cpu_model2->__cpu_family;\n+ unsigned int model = cpu_model2->__cpu_model;\n+\n+ switch (family)\n+ {\n+ case 0x18:\n+ cpu_model->__cpu_type = HYGONFAM18H;\n+ if (model == 0x4)\n+\t{\n+\t cpu = \"c86-4g-m4\";\n+\t CHECK___builtin_cpu_is (\"c86-4g-m4\");\n+\t cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M4;\n+\t}\n+ else if (model == 0x6)\n+\t{\n+\t cpu = \"c86-4g-m6\";\n+\t CHECK___builtin_cpu_is (\"c86-4g-m6\");\n+\t cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M6;\n+\t}\n+ else if (model == 0x7)\n+\t{\n+\t cpu = \"c86-4g-m7\";\n+\t CHECK___builtin_cpu_is (\"c86-4g-m7\");\n+\t cpu_model->__cpu_subtype = HYGONFAM18H_C86_4G_M7;\n+\t}\n+ break;\n+ default:\n+ break;\n+ }\n+\n+ return cpu;\n+}\n+\n /* Get the specific type of Intel CPU and return Intel CPU name. Return\n NULL for unknown Intel CPU. */\n \n@@ -1259,6 +1301,21 @@ cpu_indicator_init (struct __processor_model *cpu_model,\n cpu_model->__cpu_vendor = VENDOR_CYRIX;\n else if (vendor == signature_NSC_ebx)\n cpu_model->__cpu_vendor = VENDOR_NSC;\n+ else if (vendor == signature_HYGON_ebx)\n+ {\n+ /* Adjust model and family for HYGON CPUS. */\n+ if (family == 0x0f)\n+\t{\n+\t family += extended_family;\n+\t model += extended_model;\n+\t}\n+ cpu_model2->__cpu_family = family;\n+ cpu_model2->__cpu_model = model;\n+\n+ /* Get CPU type. */\n+ get_hygon_cpu (cpu_model, cpu_model2, cpu_features2);\n+ cpu_model->__cpu_vendor = VENDOR_HYGON;\n+ }\n else\n cpu_model->__cpu_vendor = VENDOR_OTHER;\n \ndiff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc\nindex 4b924e09b..1dd9819c3 100644\n--- a/gcc/common/config/i386/i386-common.cc\n+++ b/gcc/common/config/i386/i386-common.cc\n@@ -2205,7 +2205,10 @@ const char *const processor_names[] =\n \"znver3\",\n \"znver4\",\n \"znver5\",\n- \"znver6\"\n+ \"znver6\",\n+ \"c86-4g-m4\",\n+ \"c86-4g-m6\",\n+ \"c86-4g-m7\"\n };\n \n /* Guarantee that the array is aligned with enum processor_type. */\n@@ -2473,6 +2476,15 @@ const pta processor_alias_table[] =\n {\"btver2\", PROCESSOR_BTVER2, CPU_BTVER2,\n PTA_BTVER2,\n M_CPU_TYPE (AMD_BTVER2), P_PROC_BMI},\n+ {\"c86-4g-m4\", PROCESSOR_C86_4G_M4, CPU_C86_4G_M4,\n+ PTA_C86_4G_M4,\n+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M4), P_PROC_AVX2},\n+ {\"c86-4g-m6\", PROCESSOR_C86_4G_M6, CPU_C86_4G_M6,\n+ PTA_C86_4G_M6,\n+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M6), P_PROC_AVX2},\n+ {\"c86-4g-m7\", PROCESSOR_C86_4G_M7, CPU_C86_4G_M7,\n+ PTA_C86_4G_M7,\n+ M_CPU_SUBTYPE (HYGONFAM18H_C86_4G_M7), P_PROC_AVX512F},\n \n {\"generic\", PROCESSOR_GENERIC, CPU_GENERIC,\n PTA_64BIT\n@@ -2493,10 +2505,14 @@ const pta processor_alias_table[] =\n M_CPU_SUBTYPE (AMDFAM10H_SHANGHAI), P_NONE},\n {\"istanbul\", PROCESSOR_GENERIC, CPU_GENERIC, 0,\n M_CPU_SUBTYPE (AMDFAM10H_ISTANBUL), P_NONE},\n+ {\"hygon\", PROCESSOR_GENERIC, CPU_GENERIC, 0,\n+ M_VENDOR (VENDOR_HYGON), P_NONE},\n+ {\"hygonfam18h\", PROCESSOR_GENERIC, CPU_GENERIC, 0,\n+ M_CPU_TYPE (HYGONFAM18H), P_NONE},\n };\n \n /* NB: processor_alias_table stops at the \"generic\" entry. */\n-unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 7;\n+unsigned int const pta_size = ARRAY_SIZE (processor_alias_table) - 9;\n unsigned int const num_arch_names = ARRAY_SIZE (processor_alias_table);\n \n /* Provide valid option values for -march and -mtune options. */\ndiff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h\nindex 562942467..5407d9d9e 100644\n--- a/gcc/common/config/i386/i386-cpuinfo.h\n+++ b/gcc/common/config/i386/i386-cpuinfo.h\n@@ -30,6 +30,7 @@ enum processor_vendor\n VENDOR_INTEL = 1,\n VENDOR_AMD,\n VENDOR_ZHAOXIN,\n+ VENDOR_HYGON,\n VENDOR_OTHER,\n VENDOR_CENTAUR,\n VENDOR_CYRIX,\n@@ -62,6 +63,7 @@ enum processor_types\n INTEL_GRANDRIDGE,\n INTEL_CLEARWATERFOREST,\n AMDFAM1AH,\n+ HYGONFAM18H,\n CPU_TYPE_MAX,\n BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX\n };\n@@ -108,6 +110,9 @@ enum processor_subtypes\n INTEL_COREI7_DIAMONDRAPIDS,\n INTEL_COREI7_NOVALAKE,\n AMDFAM1AH_ZNVER6,\n+ HYGONFAM18H_C86_4G_M4,\n+ HYGONFAM18H_C86_4G_M6,\n+ HYGONFAM18H_C86_4G_M7,\n CPU_SUBTYPE_MAX\n };\n \ndiff --git a/gcc/config.gcc b/gcc/config.gcc\nindex 35958b170..5a672f85f 100644\n--- a/gcc/config.gcc\n+++ b/gcc/config.gcc\n@@ -766,7 +766,7 @@ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \\\n nano-x2 eden-x4 nano-x4 lujiazui yongfeng shijidadao x86-64 x86-64-v2 \\\n x86-64-v3 x86-64-v4 sierraforest graniterapids graniterapids-d grandridge \\\n arrowlake arrowlake-s clearwaterforest pantherlake diamondrapids novalake \\\n-native\"\n+c86-4g-m4 c86-4g-m6 c86-4g-m7 native\"\n \n # Additional x86 processors supported by --with-cpu=. Each processor\n # MUST be separated by exactly one space.\n@@ -4004,6 +4004,18 @@ case ${target} in\n \tcpu=pentiumpro\n \tarch_without_sse2=yes\n \t;;\n+ c86_4g_m4-*)\n+\tarch=c86-4g-m4\n+\tcpu=c86-4g-m4\n+\t;;\n+ c86_4g_m6-*)\n+\tarch=c86-4g-m6\n+\tcpu=c86-4g-m6\n+\t;;\n+ c86_4g_m7-*)\n+\tarch=c86-4g-m7\n+\tcpu=c86-4g-m7\n+\t;;\n *)\n \tarch=pentiumpro\n \tcpu=generic\n@@ -4106,6 +4118,18 @@ case ${target} in\n \tarch=corei7\n \tcpu=corei7\n \t;;\n+ c86_4g_m4-*)\n+\tarch=c86-4g-m4\n+\tcpu=c86-4g-m4\n+\t;;\n+ c86_4g_m6-*)\n+\tarch=c86-4g-m6\n+\tcpu=c86-4g-m6\n+\t;;\n+ c86_4g_m7-*)\n+\tarch=c86-4g-m7\n+\tcpu=c86-4g-m7\n+\t;;\n *)\n \tarch=x86-64\n \tcpu=generic\ndiff --git a/gcc/config/i386/c86-4g-m7.md b/gcc/config/i386/c86-4g-m7.md\nnew file mode 100644\nindex 000000000..7eda123ac\n--- /dev/null\n+++ b/gcc/config/i386/c86-4g-m7.md\n@@ -0,0 +1,1996 @@\n+;; Copyright (C) 2026 Free Software Foundation, Inc.\n+;;\n+;; This file is part of GCC.\n+;;\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+;;\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+;; GNU General Public License for more details.\n+;;\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; <http://www.gnu.org/licenses/>.\n+;;\n+\n+;; HYGON c86-4g-m7 Scheduling\n+;; Modeling automatons for decoders, integer execution pipes,\n+;; AGU pipes, branch, floating point execution and fp store units.\n+(define_automaton \"c86_4g_m7, c86_4g_m7_ieu, c86_4g_m7_agu, c86_4g_m7_fpu\")\n+\n+;; Decoders unit has 4 decoders and all of them can decode fast path\n+;; and vector type instructions.\n+(define_cpu_unit \"c86-4g-m7-decode0\" \"c86_4g_m7\")\n+(define_cpu_unit \"c86-4g-m7-decode1\" \"c86_4g_m7\")\n+(define_cpu_unit \"c86-4g-m7-decode2\" \"c86_4g_m7\")\n+(define_cpu_unit \"c86-4g-m7-decode3\" \"c86_4g_m7\")\n+\n+;; Currently blocking all decoders for vector path instructions as\n+;; they are dispatched separetely as microcode sequence.\n+(define_reservation \"c86-4g-m7-vector\" \"c86-4g-m7-decode0+c86-4g-m7-decode1+c86-4g-m7-decode2+c86-4g-m7-decode3\")\n+\n+;; Direct instructions can be issued to any of the four decoders.\n+(define_reservation \"c86-4g-m7-direct\" \"c86-4g-m7-decode0|c86-4g-m7-decode1|c86-4g-m7-decode2|c86-4g-m7-decode3\")\n+\n+;; Fix me: Need to revisit this later to simulate fast path double behavior.\n+(define_reservation \"c86-4g-m7-double\" \"c86-4g-m7-direct\")\n+\n+;; Integer unit 4 ALU pipes.\n+(define_cpu_unit \"c86-4g-m7-ieu0\" \"c86_4g_m7_ieu\")\n+(define_cpu_unit \"c86-4g-m7-ieu1\" \"c86_4g_m7_ieu\")\n+(define_cpu_unit \"c86-4g-m7-ieu2\" \"c86_4g_m7_ieu\")\n+(define_cpu_unit \"c86-4g-m7-ieu3\" \"c86_4g_m7_ieu\")\n+\n+;; c86-4g-m7 has an additional branch unit.\n+(define_cpu_unit \"c86-4g-m7-bru0\" \"c86_4g_m7_ieu\")\n+(define_reservation \"c86-4g-m7-ieu\" \"c86-4g-m7-ieu0|c86-4g-m7-ieu1|c86-4g-m7-ieu2|c86-4g-m7-ieu3\")\n+\n+;; 3 AGU pipes in c86-4g-m7\n+(define_cpu_unit \"c86-4g-m7-agu0\" \"c86_4g_m7_agu\")\n+(define_cpu_unit \"c86-4g-m7-agu1\" \"c86_4g_m7_agu\")\n+(define_cpu_unit \"c86-4g-m7-agu2\" \"c86_4g_m7_agu\")\n+(define_reservation \"c86-4g-m7-agu-reserve\" \"c86-4g-m7-agu0|c86-4g-m7-agu1|c86-4g-m7-agu2\")\n+\n+;; Load is 4 cycles. We do not model reservation of load unit.\n+(define_reservation \"c86-4g-m7-load\" \"c86-4g-m7-agu-reserve\")\n+(define_reservation \"c86-4g-m7-store\" \"c86-4g-m7-agu-reserve\")\n+\n+;; vectorpath (microcoded) instructions are single issue instructions.\n+;; So, they occupy all the integer units.\n+(define_reservation \"c86-4g-m7-ivector\" \"c86-4g-m7-ieu0+c86-4g-m7-ieu1\n+\t\t\t\t +c86-4g-m7-ieu2+c86-4g-m7-ieu3+c86-4g-m7-bru0\n+\t\t\t\t +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2\")\n+\n+;; Floating point unit 4 FP pipes.\n+(define_cpu_unit \"c86-4g-m7-fpu0\" \"c86_4g_m7_fpu\")\n+(define_cpu_unit \"c86-4g-m7-fpu1\" \"c86_4g_m7_fpu\")\n+(define_cpu_unit \"c86-4g-m7-fpu2\" \"c86_4g_m7_fpu\")\n+(define_cpu_unit \"c86-4g-m7-fpu3\" \"c86_4g_m7_fpu\")\n+(define_reservation \"c86-4g-m7-fpu\" \"c86-4g-m7-fpu0|c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+(define_reservation \"c86-4g-m7-fpu_0_2\" \"c86-4g-m7-fpu0|c86-4g-m7-fpu2\")\n+(define_reservation \"c86-4g-m7-fpu_1_3\" \"c86-4g-m7-fpu1|c86-4g-m7-fpu3\")\n+(define_reservation \"c86-4g-m7-fpu_0_1\" \"c86-4g-m7-fpu0|c86-4g-m7-fpu1\")\n+(define_reservation \"c86-4g-m7-fpu_0_2x2\" \"c86-4g-m7-fpu0*2|c86-4g-m7-fpu2*2\")\n+(define_reservation \"c86-4g-m7-fpu_0_2x4\" \"c86-4g-m7-fpu0*4|c86-4g-m7-fpu2*4\")\n+(define_reservation \"c86-4g-m7-fvector\" \"c86-4g-m7-fpu0+c86-4g-m7-fpu1\n+\t\t\t\t +c86-4g-m7-fpu2+c86-4g-m7-fpu3\n+\t\t\t\t +c86-4g-m7-agu0+c86-4g-m7-agu1+c86-4g-m7-agu2\")\n+\n+;; IMOV/IMOVX\n+(define_insn_reservation \"c86_4g_m7_imov_xchg\" 1\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imov\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct\")\n+\n+(define_insn_reservation \"c86_4g_m7_imov_xchg_load\" 5\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imov\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_imovx_cwde\" 2\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imovx\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_imov\" 1\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t \"c86-4g-m7-direct,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_imov_load\" 5\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"!vector\")\n+\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_imov_store\" 1\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"!vector\")\n+\t\t\t\t (eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu\")\n+\n+;; PUSH\n+(define_insn_reservation \"c86_4g_m7_push\" 1\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"push,sse\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store\")\n+\n+(define_insn_reservation \"c86_4g_m7_push_mem\" 5\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t\t (and (eq_attr \"type\" \"push\")\n+\t\t\t\t (eq_attr \"memory\" \"both\")))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store\")\n+\n+;; POP\n+(define_insn_reservation \"c86_4g_m7_pop\" 4\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"pop\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_pop_mem\" 5\n+\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t (and (eq_attr \"type\" \"pop\")\n+\t\t (eq_attr \"memory\" \"both\")))\n+\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store\")\n+\n+;; IMUL/IMULX\n+(define_insn_reservation \"c86_4g_m7_imul\" 3\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imul,imulx\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_imul_load\" 7\n+\t\t\t(and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"imul\")\n+\t\t\t\t (eq_attr \"memory\" \"!none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu1\")\n+\n+;; IDIV\n+(define_insn_reservation \"c86_4g_m7_idiv_DI\" 41\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*41\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_SI\" 25\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*25\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_HI\" 17\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"HI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu3*17\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_QI\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"QI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu3*15\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_DI_load\" 45\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*41\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_SI_load\" 29\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*25\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_HI_load\" 21\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"HI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-ieu3*17\")\n+\n+(define_insn_reservation \"c86_4g_m7_idiv_QI_load\" 19\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"QI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu3*15\")\n+\n+;; Integer/genaral Instructions\n+(define_insn_reservation \"c86_4g_m7_insn\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu,negnot,rotate1,ishift1,test,incdec,icmp,\n+\t\t\t\t\t\t rotate,rotatex,ishift,ishiftx,icmov\")\n+\t\t\t\t (eq_attr \"memory\" \"none,unknown\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_insn_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu,incdec,icmp,test,ishift,\n+\t\t\t\t\t\t ishiftx,icmov,rotate,rotatex\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_insn_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ishift1,rotate1,rotate,incdec,\n+\t\t\t\t\t\t alu,icmov,ishift,negnot,alu1\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store\")\n+\n+(define_insn_reservation \"c86_4g_m7_insn2_store\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"icmp\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu,c86-4g-m7-store\")\n+\n+(define_insn_reservation \"c86_4g_m7_insn_both\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu,negnot,rotate1,ishift1,incdec,rotate,\n+\t\t\t\t\t\t rotatex,ishift,ishiftx,icmov\")\n+\t\t\t\t (eq_attr \"memory\" \"both\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu,c86-4g-m7-store\")\n+\n+(define_insn_reservation \"c86_4g_m7_setcc\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"setcc\")\n+\t\t\t\t (eq_attr \"memory\" \"none,unknown\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-ieu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_setcc_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"setcc\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-ieu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_setcc_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"setcc\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-ieu0|c86-4g-m7-ieu3\")\n+\n+;; ALU1\n+(define_insn_reservation \"c86_4g_m7_alu1_double\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_alu1_double_load\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t\t(eq_attr \"memory\" \"both\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_alu1_vector\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-ivector*3\")\n+\n+(define_insn_reservation \"c86_4g_m7_alu1_vector_load\" 7\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t\t(eq_attr \"memory\" \"both\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ivector*3\")\n+\n+(define_insn_reservation \"c86_4g_m7_alu1_direct\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu\")\n+\n+(define_insn_reservation \"c86_4g_m7_alu1_direct_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t\t(eq_attr \"memory\" \"both\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-store,c86-4g-m7-ieu\")\n+\n+;; CALL/CALLV\n+(define_insn_reservation \"c86_4g_m7_call\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"call,callv\"))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu0|c86-4g-m7-bru0,c86-4g-m7-store\")\n+\n+;; IBR\n+(define_insn_reservation \"c86_4g_m7_branch\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ibr\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu0|c86-4g-m7-bru0\")\n+\n+(define_insn_reservation \"c86_4g_m7_branch_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ibr\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-ieu0|c86-4g-m7-bru0\")\n+\n+;; LEA\n+(define_insn_reservation \"c86_4g_m7_lea\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"lea\"))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-ieu\")\n+\n+;; LEAVE\n+(define_insn_reservation \"c86_4g_m7_leave\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"leave\"))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu,c86-4g-m7-store\")\n+\n+;; STR\n+(define_insn_reservation \"c86_4g_m7_str\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"str\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-ivector*3\")\n+\n+(define_insn_reservation \"c86_4g_m7_str_load\" 7\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"str\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*3\")\n+\n+\n+(define_insn_reservation \"c86_4g_m7_ieu_vector\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"other,multi\")\n+\t\t\t\t (and (eq_attr \"unit\" \"!i387\")\n+\t\t\t\t (eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-ivector*5\")\n+\n+(define_insn_reservation \"c86_4g_m7_ieu_vector_load\" 9\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"other,multi\")\n+\t\t\t\t (and (eq_attr \"unit\" \"!i387\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-ivector*5\")\n+\n+;; SSEINS\n+(define_insn_reservation \"c86_4g_m7_sse_insertimm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseins\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"length_immediate\" \"2\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu0|c86-4g-m7-fpu3,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_insert\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseins\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"length_immediate\" \"!2\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1\")\n+\n+;; FCMOV\n+(define_insn_reservation \"c86_4g_m7_fp_cmov\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"fcmov\"))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-fvector*3\")\n+\n+;; FLD\n+(define_insn_reservation \"c86_4g_m7_fp_mov_direct_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1\")\n+\n+;; FST\n+(define_insn_reservation \"c86_4g_m7_fp_mov_direct_store\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1,c86-4g-m7-store\")\n+\n+;; FILD\n+(define_insn_reservation \"c86_4g_m7_fp_mov_double_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1\")\n+\n+;; FIST\n+(define_insn_reservation \"c86_4g_m7_fp_mov_double_store\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-store\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_mov_direct\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1\")\n+\n+;; FSQRT\n+(define_insn_reservation \"c86_4g_m7fp_sqrt\" 22\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fpspc\")\n+\t\t\t\t (eq_attr \"c86_attr\" \"sqrt\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*22\")\n+\n+;; FPSPC\n+(define_insn_reservation \"c86_4g_m7_fp_spc_direct\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fpspc\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"store\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_spc\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fpspc\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-fvector*6\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_op_mul\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fop,fmul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_op_mul_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fop,fmul\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"false\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_op_imul_load\" 16\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fmul\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t\"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu_0_2\")\n+\n+;; FDIV\n+(define_insn_reservation \"c86_4g_m7_fp_div\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_div_load\" 22\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"false\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_idiv_load\" 26\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_fsgn\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"fsgn\"))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+;; FCMP\n+(define_insn_reservation \"c86_4g_m7_fp_fcmp\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu0,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_fp_fcmp_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"fcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu0,c86-4g-m7-fpu1\")\n+\n+;; MMX\n+(define_insn_reservation \"c86_4g_m7_fp_mmx\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (eq_attr \"type\" \"mmx\"))\n+\t\t\t \"c86-4g-m7-direct\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_add_cmp\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxadd,mmxcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_add_cmp_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxadd,mmxcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_cvt\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_cvt_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_shift\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_shift_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_shift_avg\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"avg\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_shift_avg_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"avg\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+;; SADBW\n+(define_insn_reservation \"c86_4g_m7_mmx_shift_sadbw\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_shift_sadbw_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_mov\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmov\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_mov_store\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_mov_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmov\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_mul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0\")\n+\n+(define_insn_reservation \"c86_4g_m7_mmx_mul_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0\")\n+\n+;; PINSR\n+(define_insn_reservation \"c86_4g_m7_sse_pinsr_reg\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-ieu2,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_pinsr_reg_load\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_vpinsr_reg\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu2*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_vpinsr_reg_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+;; PERM\n+(define_insn_reservation \"c86_4g_m7_avx512_perm_xmm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (ior (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"V4SF,V2DF,TI\"))\n+\t\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"V8SF,V4DF,TI,OI\")))\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_perm_xmm_opload\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (ior (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"V4SF,V2DF,TI\"))\n+\t\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"V8SF,V4DF,TI,OI\")))\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_permi2_ymm\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_permi2_zmm\" 16\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_permi2_ymm_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_permi2_zmm_load\" 23\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm2\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_perm_zmm_imm\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_operand 2 \"immediate_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_perm_zmm_imm_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_operand 2 \"immediate_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_perm_zmm_noimm\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_operand 2 \"nonimmediate_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_perm_zmm_noimm_load\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_operand 2 \"nonimmediate_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_perm_ymm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_perm_ymem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"perm\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; VINSERT\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_ymm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_ymem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load,both\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_zxmm\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_test \"GET_MODE_SIZE (GET_MODE (operands[2]))==16\")\n+\t\t\t\t\t (match_operand 2 \"register_operand\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_zxmem\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_test \"GET_MODE_SIZE (GET_MODE (operands[2]))==16\")\n+\t\t\t\t\t (match_operand 2 \"memory_operand\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_zymm\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_test \"GET_MODE_SIZE (GET_MODE (operands[2]))==32\")\n+\t\t\t\t\t (match_operand 2 \"register_operand\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_insertx_zymem\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (match_test \"GET_MODE_SIZE (GET_MODE (operands[2]))==32\")\n+\t\t\t\t\t (match_operand 2 \"memory_operand\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_insertx_ymm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_insertx_ymem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insertx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0*2\")\n+\n+;; SHUF/MULTISHIFTQB\n+(define_insn_reservation \"c86_4g_m7_avx512_shuf_xymm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"shufx\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V8DF,V16SF,XI\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_shuf_zmm\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"shufx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8DF,V16SF,XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_shuf_xymem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"shufx\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V8DF,V16SF,XI\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_shuf_zmem\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"shufx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V8DF,V16SF,XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; SSELOGIC\n+(define_insn_reservation \"c86_4g_m7_sselogic_xymm\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sselogic\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_sselogic_xymm_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sselogic\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+;; CMPESTR\n+(define_insn_reservation \"c86_4g_m7_avx512_cmpestr\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"cmpestr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_cmpestr_load\" 13\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"cmpestr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; SSELOG\n+(define_insn_reservation \"c86_4g_m7_avx512_log\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1,sseshuf,sseshuf1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_log_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog,sselog1,sseshuf,sseshuf1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+;; SSELOG1\n+;; VDBPSADBW\n+(define_insn_reservation \"c86_4g_m7_avx512_vdbpsadbw_xymm\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,TI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vdbpsadbw_xymem\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,TI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vdbpsadbw_zmm\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vdbpsadbw_zmem\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; ABS\n+(define_insn_reservation \"c86_4g_m7_avx512_abs\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"abs\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_abs_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"abs\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load,both\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+;; SIGN\n+(define_insn_reservation \"c86_4g_m7_avx_sign\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sign\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sign_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sign\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+;; BLEND/ABS/AES\n+(define_insn_reservation \"c86_4g_m7_avx_blend\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"abs,blend,aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_blend_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"abs,blend,aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_aes\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,ssecvt,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_aes_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,ssecvt,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_aes\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_aes_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"aes\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu1\")\n+\n+;; EXTR\n+(define_insn_reservation \"c86_4g_m7_extr\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,sselog,mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"extr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_extr_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1,sselog,mmxcvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"extr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-store,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1\")\n+\n+;; SSECOMI\n+(define_insn_reservation \"c86_4g_m7_avx_ssecomi_comi\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecomi_comi_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecomi_test\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecomi_test_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2\")\n+\n+;; SSEIMUL\n+(define_insn_reservation \"c86_4g_m7_avx512_imul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_imul_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_imul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_imul_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+;; SSEMOV\n+(define_insn_reservation \"c86_4g_m7_avx512_mov_vmov\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov,sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other,blend,maxmin\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mov_vmov_store\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mov_vmov_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov,sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other,blend,maxmin\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_y\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,V8SF,V4DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_y_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,V8SF,V4DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load,both\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_z\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_z_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2x4\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_x\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,SI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_vpmovx_x_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,SI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_vpmovx_xx\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1|c86-4g-m7-fpu2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_vpmovx_xx_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"vpmovx\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load,both\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1|c86-4g-m7-fpu2\")\n+\n+;; EXPAND\n+(define_insn_reservation \"c86_4g_m7_avx512_expand\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"expand,compress\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"XI,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_expand_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"expand,compress\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"XI,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_expand_z\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"expand,compress\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_expand_z_load\" 17\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"expand,compress\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; MOVNT\n+(define_insn_reservation \"c86_4g_m7_avx512_movnt_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_movnt_store\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"store\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_movnt_store\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov,mmxmov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"XI,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"!none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-store,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_movnt_xy\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"XI,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+;; BLENDV\n+(define_insn_reservation \"c86_4g_m7_avx512_blendv\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"blendv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_blendv_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"blendv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+;; SSEMOV2\n+(define_insn_reservation \"c86_4g_m7_sse_mov2\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov2\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_mov2_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemov2\")\n+\t\t\t\t (eq_attr \"memory\" \"!none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+;; SSEISHFT\n+(define_insn_reservation \"c86_4g_m7_avx512_sseishft_aligr\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseishft_aligr_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseishft_vshift\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"!1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseishft_vshift_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"!1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+\n+;; SSEADD\n+(define_insn_reservation \"c86_4g_m7_avx512_sseadd_maxmin_xy\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseadd_maxmin_xy_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (ior (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseadd_maxmin\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseadd_maxmin_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseadd_maxmin\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseadd_maxmin_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"maxmin\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+;; SUB/ADD\n+(define_insn_reservation \"c86_4g_m7_avx512_sseadd_xy\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseadd_xy_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3\")\n+\n+;; HADD/HSUB\n+(define_insn_reservation \"c86_4g_m7_avx_sseadd_hplus\" 7\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sseadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseadd_hplus_load\" 14\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd,sseadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; SSEIADD\n+(define_insn_reservation \"c86_4g_m7_avx512_sseiadd_madd\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw,madd\")\n+\t\t\t\t\t(and (ior (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"XI\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseiadd_madd_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw,madd\")\n+\t\t\t\t\t(and (ior (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t\t (eq_attr \"mode\" \"XI\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseiadd_sadbw\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex,maybe_evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseiadd_sadbw_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex,maybe_evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_sadbw\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_sadbw_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_madd\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"madd\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_madd_mem\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"madd\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0\")\n+\n+;; AVG\n+(define_insn_reservation \"c86_4g_m7_avx512_sseiadd_avg\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"avg\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sseiadd_avg_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"avg\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseiadd_hplus\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,sseiadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sseiadd_hplus_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,sseiadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_hplus\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,sseiadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-fpu0*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_sseiadd_hplus_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,sseiadd1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"hplus\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"orig\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load,c86-4g-m7-fpu0*2\")\n+\n+;; SSEMUL\n+(define_insn_reservation \"c86_4g_m7_avx512_ssemul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu0\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssemul_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu0\")\n+\n+;; SSEDIV\n+(define_insn_reservation \"c86_4g_m7_avx512_ssediv\" 13\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu3*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssediv_mem\" 20\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V16SF,V8DF\"))\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssediv_z\" 24\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu3*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssediv_zmem\" 31\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu3*7\")\n+\n+;; SSECMP\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V2DF,V4DF,V8SF,V4SF,SF,DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V2DF,V4DF,V8SF,V4SF,SF,DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_0_2,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_z\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_z_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V16SF,V8DF,XI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_vp\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_vp_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecmp_vp\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecmp_vp_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu\")\n+\n+;; VPTEST\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_test\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"ptest\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_test_load\" 13\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,OI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"ptest\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_test_z\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"ptest\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecmp_test_z_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"ptest\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+;; SSECVT\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_xy\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,V4SF,V2DF,OI,V8SF,V4DF\")\n+\t\t\t\t (and (not (ior (match_operand:V8DI 1 \"register_operand\")\n+\t\t\t\t\t\t (match_operand:V8DF 1 \"register_operand\")))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_xy_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI,V4SF,V2DF,OI,V8SF,V4DF\")\n+\t\t\t\t (and (not (ior (match_operand:V8DI 1 \"register_operand\")\n+\t\t\t\t\t\t (match_operand:V8DF 1 \"register_operand\")))\n+\t\t\t\t\t (eq_attr \"memory\" \"!none\")))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_y_z\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,V8SF,V4DF\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (ior (match_operand:V8DI 1 \"register_operand\")\n+\t\t\t\t\t (match_operand:V8DF 1 \"register_operand\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_y_z_load\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI,V8SF,V4DF\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (ior (match_operand:V8DI 1 \"memory_operand\")\n+\t\t\t\t\t (match_operand:V8DF 1 \"memory_operand\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"!none\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_z\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_ssecvt_z_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"!none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecvt\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t (and (eq_attr \"mmx_isa\" \"base\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_ssecvt_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t (and (eq_attr \"mmx_isa\" \"base\")\n+\t\t\t\t\t (eq_attr \"memory\" \"!none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu2|c86-4g-m7-fpu3\")\n+\n+;; CVTPI\n+(define_insn_reservation \"c86_4g_m7_sse_ssecvt_pspi\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SF,DI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_ssecvt_pspi_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SF,DI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_ssecvt_pi\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"SF,DI\"))\n+\t\t\t\t (and (eq_attr \"mmx_isa\" \"native\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_sse_ssecvt_pi_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"SF,DI\"))\n+\t\t\t\t (and (eq_attr \"mmx_isa\" \"native\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu1,c86-4g-m7-fpu_0_1\")\n+\n+;; SSEMULADD\n+(define_insn_reservation \"c86_4g_m7_avx512_muladd\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (not (eq_attr \"isa\" \"fma,fma4\"))\n+\t\t\t\t\t (eq_attr \"mode\" \"V32HF,V16SF,V8DF,XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_muladd_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (not (eq_attr \"isa\" \"fma,fma4\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_muladd_madd\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"madd,rcp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_muladd_madd_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd,sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"madd,rcp\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_fma_muladd\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (and (eq_attr \"isa\" \"fma,fma4\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_fma_muladd_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (and (eq_attr \"isa\" \"fma,fma4\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+;; SSE\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_range\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"!1\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_range_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"!1\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_x\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_x_load\" 9\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"TI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_y\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_y_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_z\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_conflict_z_load\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"mode\" \"XI\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_class\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"1\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V32HF,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_class_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"1\")\n+\t\t\t\t (and (not (eq_attr \"mode\" \"V32HF,V16SF,V8DF\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-load,c86-4g-m7-fpu_1_3,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_class_z\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"1\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V32HF,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_class_z_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t (and (eq_attr \"length_immediate\" \"1\")\n+\t\t\t\t (and (eq_attr \"mode\" \"V32HF,V16SF,V8DF\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\"))))))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-load\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sse\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"rcp,other\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx_sse_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"rcp,other\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!evex\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu_0_1\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt\" 16\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_sse_sqrt_load\" 23\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load,c86-4g-m7-fpu1*7|c86-4g-m7-fpu3*7\")\n+\n+;; MSKLOG/MSKMOV\n+(define_insn_reservation \"c86_4g_m7_avx512_msklog\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"msklog\")\n+\t\t\t\t (eq_attr \"c86_decode\" \"direct\")))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_msklog_vector\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"msklog\")\n+\t\t\t\t (eq_attr \"c86_decode\" \"vector\")))\n+\t\t\t \"c86-4g-m7-vector\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_reg_k\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (and (match_operand 0 \"register_operand\" \"r\")\n+\t\t\t\t (eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_xy_k\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (ior (match_operand:V2DI 0 \"register_operand\" \"v\")\n+\t\t\t\t\t(match_operand:V4DI 0 \"register_operand\" \"v\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu3,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_z_k\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (match_operand:V8DI 0 \"register_operand\" \"v\")))\n+\t\t\t \"c86-4g-m7-vector,c86-4g-m7-fpu3*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_k_k\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (and (match_operand 0 \"register_operand\" \"k\")\n+\t\t\t\t (match_operand 1 \"register_operand\" \"k\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-fpu_1_3\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_k_reg\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (and (match_operand 0 \"register_operand\" \"k\")\n+\t\t\t\t (match_operand 1 \"register_operand\" \"r\"))))\n+\t\t\t \"c86-4g-m7-double,c86-4g-m7-fpu1*2,c86-4g-m7-fpu1*2|c86-4g-m7-fpu3*2\")\n+\n+(define_insn_reservation \"c86_4g_m7_avx512_mskmov_k_m\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m7\")\n+\t\t\t (and (eq_attr \"type\" \"mskmov\")\n+\t\t\t\t (and (match_operand 0 \"register_operand\" \"k\")\n+\t\t\t\t (match_operand 1 \"memory_operand\"))))\n+\t\t\t \"c86-4g-m7-direct,c86-4g-m7-load\")\ndiff --git a/gcc/config/i386/c86-4g.md b/gcc/config/i386/c86-4g.md\nnew file mode 100644\nindex 000000000..66c4e2cf7\n--- /dev/null\n+++ b/gcc/config/i386/c86-4g.md\n@@ -0,0 +1,1204 @@\n+;; Copyright (C) 2026 Free Software Foundation, Inc.\n+;;\n+;; This file is part of GCC.\n+;;\n+;; GCC is free software; you can redistribute it and/or modify\n+;; it under the terms of the GNU General Public License as published by\n+;; the Free Software Foundation; either version 3, or (at your option)\n+;; any later version.\n+;;\n+;; GCC is distributed in the hope that it will be useful,\n+;; but WITHOUT ANY WARRANTY; without even the implied warranty of\n+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n+;; GNU General Public License for more details.\n+;;\n+;; You should have received a copy of the GNU General Public License\n+;; along with GCC; see the file COPYING3. If not see\n+;; <http://www.gnu.org/licenses/>.\n+;;\n+\n+\n+(define_attr \"c86_decode\" \"direct,vector,double\"\n+ (const_string \"direct\"))\n+\n+(define_attr \"c86_attr\" \"other,abs,sqrt,maxmin,blend,blendv,rcp,movnt,avg,\n+\t\t\t sign,sadbw,insr,perm2,perm,insertx,shufx,madd,\n+\t\t\t compress,sselogic,cmpestr,extr,vpmovx,expand,aes,\n+\t\t\t hplus,ptest\"\n+ (const_string \"other\"))\n+\n+;; HYGON Scheduling\n+;; Modeling automatons for decoders, integer execution pipes,\n+;; AGU pipes and floating point execution units.\n+(define_automaton \"c86_4g, c86_4g_ieu, c86_4g_fp, c86_4g_agu\")\n+\n+;; Decoders unit has 4 decoders and all of them can decode fast path\n+;; and vector type instructions.\n+(define_cpu_unit \"c86-4g-decode0\" \"c86_4g\")\n+(define_cpu_unit \"c86-4g-decode1\" \"c86_4g\")\n+(define_cpu_unit \"c86-4g-decode2\" \"c86_4g\")\n+(define_cpu_unit \"c86-4g-decode3\" \"c86_4g\")\n+\n+;; Currently blocking all decoders for vector path instructions as\n+;; they are dispatched separetely as microcode sequence.\n+;; Fix me: Need to revisit this.\n+(define_reservation \"c86-4g-vector\" \"c86-4g-decode0+c86-4g-decode1+c86-4g-decode2+c86-4g-decode3\")\n+\n+;; Direct instructions can be issued to any of the four decoders.\n+(define_reservation \"c86-4g-direct\" \"c86-4g-decode0|c86-4g-decode1|c86-4g-decode2|c86-4g-decode3\")\n+\n+;; Fix me: Need to revisit this later to simulate fast path double behavior.\n+(define_reservation \"c86-4g-double\" \"c86-4g-direct\")\n+\n+\n+;; Integer unit 4 ALU pipes.\n+(define_cpu_unit \"c86-4g-ieu0\" \"c86_4g_ieu\")\n+(define_cpu_unit \"c86-4g-ieu1\" \"c86_4g_ieu\")\n+(define_cpu_unit \"c86-4g-ieu2\" \"c86_4g_ieu\")\n+(define_cpu_unit \"c86-4g-ieu3\" \"c86_4g_ieu\")\n+(define_reservation \"c86-4g-ieu\" \"c86-4g-ieu0|c86-4g-ieu1|c86-4g-ieu2|c86-4g-ieu3\")\n+\n+;; 2 AGU pipes in c86_4g\n+;; According to CPU diagram last AGU unit is used only for stores.\n+(define_cpu_unit \"c86-4g-agu0\" \"c86_4g_agu\")\n+(define_cpu_unit \"c86-4g-agu1\" \"c86_4g_agu\")\n+(define_reservation \"c86-4g-agu-reserve\" \"c86-4g-agu0|c86-4g-agu1\")\n+\n+;; Load is 4 cycles. We do not model reservation of load unit.\n+;;(define_reservation \"c86-4g-load\" \"c86-4g-agu-reserve, nothing, nothing, nothing\")\n+(define_reservation \"c86-4g-load\" \"c86-4g-agu-reserve\")\n+(define_reservation \"c86-4g-store\" \"c86-4g-agu-reserve\")\n+\n+;; vectorpath (microcoded) instructions are single issue instructions.\n+;; So, they occupy all the integer units.\n+(define_reservation \"c86-4g-ivector\" \"c86-4g-ieu0+c86-4g-ieu1\n+\t\t\t\t +c86-4g-ieu2+c86-4g-ieu3\n+\t\t\t\t +c86-4g-agu0+c86-4g-agu1\")\n+\n+;; Floating point unit 4 FP pipes.\n+(define_cpu_unit \"c86-4g-fp0\" \"c86_4g_fp\")\n+(define_cpu_unit \"c86-4g-fp1\" \"c86_4g_fp\")\n+(define_cpu_unit \"c86-4g-fp2\" \"c86_4g_fp\")\n+(define_cpu_unit \"c86-4g-fp3\" \"c86_4g_fp\")\n+\n+(define_reservation \"c86-4g-fpu\" \"c86-4g-fp0|c86-4g-fp1|c86-4g-fp2|c86-4g-fp3\")\n+\n+(define_reservation \"c86-4g-fvector\" \"c86-4g-fp0+c86-4g-fp1\n+\t\t\t\t +c86-4g-fp2+c86-4g-fp3\n+\t\t\t\t +c86-4g-agu0+c86-4g-agu1\")\n+\n+;; Call instruction\n+(define_insn_reservation \"c86_4g_call\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"call,callv\"))\n+\t\t\t \"c86-4g-double,c86-4g-store,c86-4g-ieu0+c86-4g-ieu3\")\n+\n+;; General instructions\n+(define_insn_reservation \"c86_4g_push\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"push\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-direct,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_push_load\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"push\")\n+\t\t\t\t (eq_attr \"memory\" \"both\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load+c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_pop\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"pop\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load\")\n+\n+(define_insn_reservation \"c86_4g_pop_mem\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"pop\")\n+\t\t\t\t (eq_attr \"memory\" \"both\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-store\")\n+\n+;; Leave\n+(define_insn_reservation \"c86_4g_leave\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"leave\"))\n+\t\t\t \"c86-4g-double,c86-4g-ieu+c86-4g-store\")\n+\n+;; Integer Instructions or General instructions\n+;; Multiplications\n+;; Reg operands\n+(define_insn_reservation \"c86_4g_imul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"imul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu1\")\n+\n+(define_insn_reservation \"c86_4g_imul_mem\" 7\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"imul\")\n+\t\t\t\t (eq_attr \"memory\" \"!none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load, c86-4g-ieu1\")\n+\n+;; Divisions\n+;; Reg operands\n+(define_insn_reservation \"c86_4g_idiv_DI\" 41\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu2*41\")\n+\n+(define_insn_reservation \"c86_4g_idiv_SI\" 25\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu2*25\")\n+\n+(define_insn_reservation \"c86_4g_idiv_HI\" 17\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"HI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu2*17\")\n+\n+(define_insn_reservation \"c86_4g_idiv_QI\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"QI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu2*15\")\n+\n+;; Mem operands\n+(define_insn_reservation \"c86_4g_idiv_mem_DI\" 45\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*41\")\n+\n+(define_insn_reservation \"c86_4g_idiv_mem_SI\" 29\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*25\")\n+\n+(define_insn_reservation \"c86_4g_idiv_mem_HI\" 21\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"HI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu2*17\")\n+\n+(define_insn_reservation \"c86_4g_idiv_mem_QI\" 19\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"idiv\")\n+\t\t\t\t (and (eq_attr \"mode\" \"QI\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-ieu2*15\")\n+\n+;; STR ISHIFT which are micro coded.\n+;; Fix me: Latency need to be rechecked.\n+(define_insn_reservation \"c86_4g_str_ishift\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"str,ishift\")\n+\t\t\t\t (eq_attr \"memory\" \"both,store\")))\n+\t\t\t \"c86-4g-vector,c86-4g-ivector\")\n+\n+;; MOV - integer moves\n+(define_insn_reservation \"c86_4g_load_imov_double\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu\")\n+\n+(define_insn_reservation \"c86_4g_load_imov_direct\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"!double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu\")\n+\n+(define_insn_reservation \"c86_4g_load_imov_double_store\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_load_imov_direct_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"!double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t\t \"c86-4g-direct,c86-4g-ieu,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_load_imov_double_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-ieu\")\n+\n+(define_insn_reservation \"c86_4g_load_imov_direct_load\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"!double\")\n+\t\t\t\t (and (eq_attr \"type\" \"imov,imovx\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load\")\n+\n+;; INTEGER/GENERAL instructions\n+;; register/imm operands only: ALU, ICMP, NEG, NOT, ROTATE, ISHIFT, TEST\n+(define_insn_reservation \"c86_4g_insn\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov\")\n+\t\t\t\t (eq_attr \"memory\" \"none,unknown\")))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu\")\n+\n+(define_insn_reservation \"c86_4g_insn_load\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"alu,icmp,negnot,rotate,rotate1,ishift,ishift1,test,setcc,incdec,icmov\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-ieu\")\n+\n+;; FIXME: The instructions matched here has only two operands, which means memory type can only be none, load or both.\n+;; Store memory type handling should never take effect here?\n+(define_insn_reservation \"c86_4g_insn_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec\")\n+\t\t\t\t (eq_attr \"memory\" \"store\")))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_insn_both\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"alu,icmp,negnot,rotate,rotate1,ishift1,test,setcc,incdec\")\n+\t\t\t\t (eq_attr \"memory\" \"both\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-ieu,c86-4g-store\")\n+\n+;; Special latency for multi type.\n+(define_insn_reservation \"c86_4g_fp_fcomp\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t (and (eq_attr \"unit\" \"i387\")\n+\t\t\t\t\t(eq_attr \"type\" \"multi\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp0|c86-4g-fp2\")\n+\n+;; Fix me: Other vector type insns keeping latency 6 as of now.\n+(define_insn_reservation \"c86_4g_ieu_vector\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t (and (eq_attr \"unit\" \"!i387\")\n+\t\t\t\t\t(eq_attr \"type\" \"other,str,multi\"))))\n+\t\t\t \"c86-4g-vector,c86-4g-ivector\")\n+\n+;; ALU1 register operands.\n+(define_insn_reservation \"c86_4g_alu1_vector\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"vector\")\n+\t\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-vector,c86-4g-ivector\")\n+\n+(define_insn_reservation \"c86_4g_alu1_double\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-double,c86-4g-ieu\")\n+\n+(define_insn_reservation \"c86_4g_alu1_direct\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"alu1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none,unknown\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu\")\n+\n+;; Branches : Fix me need to model conditional branches.\n+(define_insn_reservation \"c86_4g_branch\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ibr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct\")\n+\n+;; Indirect branches check latencies.\n+(define_insn_reservation \"c86_4g_indirect_branch_mem\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ibr\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-vector,c86-4g-ivector\")\n+\n+;; LEA executes in ALU units with 1 cycle latency.\n+(define_insn_reservation \"c86_4g_lea\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"lea\"))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu\")\n+\n+;; Floating point\n+(define_insn_reservation \"c86_4g_fp_cmov\" 6\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"fcmov\"))\n+\t\t\t \"c86-4g-vector,c86-4g-fvector\")\n+\n+\n+(define_insn_reservation \"c86_4g_fp_mov_direct_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_fp_mov_direct_store\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp2|c86-4g-fp3,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_fp_mov_double\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_fp_mov_double_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_fp_mov_direct\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fmov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+;; SQRT\n+(define_insn_reservation \"c86_4g_fp_sqrt\" 22\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fpspc\")\n+\t\t\t\t (eq_attr \"c86_attr\" \"sqrt\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*22\")\n+\n+(define_insn_reservation \"c86_4g_sse_sqrt_sf\" 14\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SF,V4SF,V8SF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none,unknown\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*14\")\n+\n+(define_insn_reservation \"c86_4g_sse_sqrt_sf_mem\" 21\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SF,V4SF,V8SF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*14\")\n+\n+(define_insn_reservation \"c86_4g_sse_sqrt_df\" 20\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"DF,V2DF,V4DF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none,unknown\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*20\")\n+\n+(define_insn_reservation \"c86_4g_sse_sqrt_df_mem\" 27\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"DF,V2DF,V4DF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"sqrt\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*20\")\n+\n+;; RCP\n+(define_insn_reservation \"c86_4g_sse_rcp\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V4SF,V8SF,SF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"rcp\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_rcp_mem\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V4SF,V8SF,SF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(and (eq_attr \"c86_attr\" \"rcp\")\n+\t\t\t\t\t (eq_attr \"type\" \"sse\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+;; TODO: AGU?\n+(define_insn_reservation \"c86_4g_fp_spc_direct\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_decode\" \"direct\")\n+\t\t\t\t (and (eq_attr \"type\" \"fpspc\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp3\")\n+\n+;; FABS\n+(define_insn_reservation \"c86_4g_fp_absneg\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"fsgn\"))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1|c86-4g-fp3\")\n+\n+;; FCMP\n+(define_insn_reservation \"c86_4g_fp_fcmp\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t (eq_attr \"type\" \"fcmp\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp0,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_fp_fcmp_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t (and (eq_attr \"c86_decode\" \"double\")\n+\t\t\t\t\t(eq_attr \"type\" \"fcmp\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load, c86-4g-fp0,c86-4g-fp1\")\n+\n+;;FADD FSUB FMUL\n+(define_insn_reservation \"c86_4g_fp_op_mul\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fop,fmul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_fp_op_mul_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fop,fmul\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"false\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_fp_op_imul_load\" 16\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fop,fmul\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t\"c86-4g-double,c86-4g-load,c86-4g-fp0,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_fp_op_div\" 15\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*15\")\n+\n+(define_insn_reservation \"c86_4g_fp_op_div_load\" 22\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*15\")\n+\n+(define_insn_reservation \"c86_4g_fp_op_idiv_load\" 27\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"fdiv\")\n+\t\t\t\t (and (eq_attr \"fp_int_src\" \"true\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*19\")\n+\n+;; MMX, SSE, SSEn.n, AVX, AVX2 instructions\n+(define_insn_reservation \"c86_4g_fp_insn\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (eq_attr \"type\" \"mmx\"))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_mmx_add\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxadd\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_mmx_add_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxadd\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_mmx_hadd\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd1\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_mmx_hadd_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd1\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_mmx_cmp\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_mmx_cmp_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcmp\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_mmx_cvt_pck_shuf\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcvt,sseshuf,sseshuf1\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_cvt_pck_shuf_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxcvt,sseshuf,sseshuf1\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_shift\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_move\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmov\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_shift_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_move_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_mmx_move_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxshft,mmxmov\")\n+\t\t\t\t (eq_attr \"memory\" \"store,both\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp2,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_mmx_mul\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_mmx_mul_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"mmxmul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0\")\n+\n+;; sseabs\n+(define_insn_reservation \"c86_4g_sse_abs\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_attr\" \"abs\")\n+\t\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sse_pinsr_reg\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t\t(and (match_operand 2 \"register_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu2,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_pinsr\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"insr\")\n+\t\t\t\t\t(and (not (match_operand 2 \"register_operand\"))\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_log\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_log_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_sign\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sign\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sse_sign_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sign\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fpu\")\n+\n+\n+(define_insn_reservation \"c86_4g_sse_log1\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_log1_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"!none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_extrq\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"prefix_data16\" \"1\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_movsdup\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sse\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"prefix\" \"vex\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_alignr\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"prefix_extra\" \"1\"))\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_ishift\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"prefix_extra\" \"!1\"))\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_ishift_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"prefix_extra\" \"!1\"))\n+\t\t\t (and (eq_attr \"type\" \"sseishft\")\n+\t\t\t\t (eq_attr \"memory\" \"!none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_insertimm\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseins\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"length_immediate\" \"2\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sse_insert\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseins\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"length_immediate\" \"!2\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sse_comi\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SF,DF,V4SF,V2DF\")\n+\t\t\t\t (and (eq_attr \"prefix\" \"!vex\")\n+\t\t\t\t\t(and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_comi_load\" 12\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_comi_double\" 2\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t\t(and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-double,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_comi_double_load\" 10\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"prefix\" \"vex\")\n+\t\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t\t(and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_test\" 4\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_test_load\" 11\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_avx256_test\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V8SF,V4DF,OI\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_avx256_test_load\" 15\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V8SF,V4DF,OI\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"1\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecomi\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp1,c86-4g-fp1\")\n+\n+;; SSE moves\n+;; Fix me: Need to revist this again some of the moves may be restricted\n+;; to some fpu pipes.\n+\n+;; movnt doesn't touch cache, so latency modeling has little impact.\n+(define_insn_reservation \"c86_4g_sse_movnt_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov,mmxmov,ssecvt\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load\")\n+\n+(define_insn_reservation \"c86_4g_sse_movnt_store\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"c86_attr\" \"movnt\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov,mmxmov,ssecvt\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_sse_mov\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t (and (eq_attr \"isa\" \"avx\")\n+\t\t\t\t\t(and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu0\")\n+\n+(define_insn_reservation \"c86_4g_avx_mov\" 2\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"TI\")\n+\t\t\t\t (and (eq_attr \"isa\" \"avx\")\n+\t\t\t\t\t(and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t (and (match_operand:SI 1 \"register_operand\")\n+\t\t\t\t\t\t (eq_attr \"memory\" \"none\"))))))\n+\t\t\t \"c86-4g-direct,c86-4g-ieu2\")\n+\n+(define_insn_reservation \"c86_4g_sseavx_mov\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"prefix_extra\" \"0\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sseavx_blend\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"SF,DF,V4SF,V2DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemov,sselog1\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"blend,blendv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sseavx_mov_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SF,DF,V4SF,V2DF,TI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t\"c86-4g-direct,c86-4g-fpu,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_sseavx_mov_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF,TI\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_avx256_mov\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_avx256_mov_store\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"store\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fpu,c86-4g-store\")\n+\n+(define_insn_reservation \"c86_4g_avx256_mov_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF,OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssemov\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fpu\")\n+\n+;; SSE max & min\n+(define_insn_reservation \"c86_4g_sse_maxmin\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"SF,DF,V4SF,V8SF,V2DF,V4DF,TI\"))\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"maxmin\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_maxmin_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"SF,DF,V4SF,V8SF,V2DF,V4DF,TI\"))\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"maxmin\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_pmaxmin\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"TI,OI\"))\n+\t\t\t (and (eq_attr \"type\" \"mmxadd,sseiadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"maxmin\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sse_pmaxmin_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"TI,OI\"))\n+\t\t\t (and (eq_attr \"type\" \"mmxadd,sseiadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"maxmin\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fpu\")\n+\n+;; SSE avg\n+(define_insn_reservation \"c86_4g_sse_avg\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"c86_attr\" \"avg\"))\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,mmxshft\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sse_avg_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"c86_attr\" \"avg\"))\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,mmxshft\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp3\")\n+\n+;;MMX sadbw\n+(define_insn_reservation \"c86_4g_sse_sadbw\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sse_sadbw_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd,mmxshft\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"sadbw\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0\")\n+\n+;; SSE add\n+(define_insn_reservation \"c86_4g_sse_add\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"other\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_sse_add_load\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseadd\")\n+\t\t\t\t (and (eq_attr \"memory\" \"load\")\n+\t\t\t\t\t(eq_attr \"c86_attr\" \"!maxmin\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1|c86-4g-fp3\")\n+\n+(define_insn_reservation \"c86_4g_sse_fma\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_fma_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ssemuladd\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t\"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_iadd\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+(define_insn_reservation \"c86_4g_sse_iadd_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"sseiadd\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fpu\")\n+\n+;; SSE conversions.\n+(define_insn_reservation \"c86_4g_ssecvtsf_si_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t (and (eq_attr \"type\" \"sseicvt\")\n+\t\t\t\t\t(and (match_operand:SF 1 \"memory_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0\")\n+\n+(define_insn_reservation \"c86_4g_ssecvtdf_si\" 5\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t (and (match_operand:DF 1 \"register_operand\")\n+\t\t\t\t\t(and (eq_attr \"type\" \"sseicvt\")\n+\t\t\t\t\t (eq_attr \"memory\" \"none\")))))\n+\t\t\t \"c86-4g-double,c86-4g-fp3,c86-4g-ieu0\")\n+\n+(define_insn_reservation \"c86_4g_ssecvtdf_si_load\" 12\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"SI\")\n+\t\t\t\t (and (eq_attr \"type\" \"sseicvt\")\n+\t\t\t\t\t(and (match_operand:DF 1 \"memory_operand\")\n+\t\t\t\t\t (eq_attr \"memory\" \"load\")))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp3,c86-4g-ieu0\")\n+\n+;; All other used ssecvt fp3 pipes\n+;; Check: Need to revisit this again.\n+;; Some SSE converts may use different pipe combinations.\n+(define_insn_reservation \"c86_4g_ssecvt\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1\")\n+\n+(define_insn_reservation \"c86_4g_ssecvt_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"type\" \"ssecvt\")\n+\t\t\t\t (and (eq_attr \"c86_attr\" \"other\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1\")\n+\n+;; SSE div\n+(define_insn_reservation \"c86_4g_ssediv_ss_ps\" 10\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V4SF,SF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*10\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_ss_ps_load\" 17\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V4SF,SF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*10\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_sd_pd\" 13\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"V2DF,DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp1*13\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_sd_pd_load\" 20\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t (eq_attr \"mode\" \"V2DF,DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp1*13\")\n+\n+\n+(define_insn_reservation \"c86_4g_ssediv_avx256_ps\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"type\" \"ssediv\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp1*10\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_avx256_ps_load\" 17\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*10\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_avx256_pd\" 13\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V4DF\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp1*13\")\n+\n+(define_insn_reservation \"c86_4g_ssediv_avx256_pd_load\" 20\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V4DF\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssediv\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp1*13\")\n+;; SSE MUL\n+(define_insn_reservation \"c86_4g_ssemul_ss_ps\" 3\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"V8SF,V4SF,SF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_ssemul_ss_ps_load\" 10\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"V8SF,V4SF,SF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_ssemul_sd_pd\" 4\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"V4DF,V2DF,DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_ssemul_sd_pd_load\" 11\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"V4DF,V2DF,DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssemul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+;;SSE imul\n+(define_insn_reservation \"c86_4g_sseimul\" 3\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"TI\"))\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sseimul_avx256\" 4\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sseimul_load\" 10\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"TI\"))\n+\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sseimul_avx256_load\" 11\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sseimul_di\" 3\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t (and (eq_attr \"memory\" \"none\")\n+\t\t\t\t\t(eq_attr \"type\" \"sseimul\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0\")\n+\n+(define_insn_reservation \"c86_4g_sseimul_load_di\" 10\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"DI\")\n+\t\t\t\t (and (eq_attr \"type\" \"sseimul\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0\")\n+\n+;; SSE compares\n+(define_insn_reservation \"c86_4g_sse_cmp\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t(eq_attr \"mode\" \"SF,DF,V4SF,V2DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_cmp_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t\t (eq_attr \"mode\" \"SF,DF,V4SF,V2DF\"))\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+\n+(define_insn_reservation \"c86_4g_sse_cmp_avx256\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t\"c86-4g-double,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_cmp_avx256_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"V8SF,V4DF\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fp0|c86-4g-fp2\")\n+\n+(define_insn_reservation \"c86_4g_sse_icmp\" 1\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"QI,HI,SI,DI,TI\"))\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (eq_attr \"memory\" \"none\")))\n+\t\t\t \"c86-4g-direct,c86-4g-fpu\")\n+\n+\n+(define_insn_reservation \"c86_4g_sse_icmp_load\" 8\n+\t\t\t (and (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t\t (eq_attr \"mode\" \"QI,HI,SI,DI,TI\"))\n+\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t (eq_attr \"memory\" \"load\")))\n+\t\t\t \"c86-4g-direct,c86-4g-load,c86-4g-fpu\")\n+\n+\n+(define_insn_reservation \"c86_4g_sse_icmp_avx256\" 1\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t\t(eq_attr \"memory\" \"none\"))))\n+\t\t\t \"c86-4g-double,c86-4g-fpu\")\n+\n+\n+(define_insn_reservation \"c86_4g_sse_icmp_avx256_load\" 8\n+\t\t\t (and (eq_attr \"cpu\" \"c86_4g_m4,c86_4g_m6\")\n+\t\t\t (and (eq_attr \"mode\" \"OI\")\n+\t\t\t\t (and (eq_attr \"type\" \"ssecmp\")\n+\t\t\t\t\t(eq_attr \"memory\" \"load\"))))\n+\t\t\t \"c86-4g-double,c86-4g-load,c86-4g-fpu\")\ndiff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h\nindex f493360b1..c48556afa 100644\n--- a/gcc/config/i386/cpuid.h\n+++ b/gcc/config/i386/cpuid.h\n@@ -235,6 +235,10 @@\n #define signature_SHANGHAI_ecx\t0x20206961\n #define signature_SHANGHAI_edx\t0x68676e61\n \n+#define signature_HYGON_ebx\t0x6f677948\n+#define signature_HYGON_ecx\t0x656e6975\n+#define signature_HYGON_edx\t0x6e65476e\n+\n #ifndef __x86_64__\n /* At least one cpu (Winchip 2) does not set %ebx and %ecx\n for cpuid leaf 1. Forcibly zero the two registers before\ndiff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc\nindex 1d0ad950a..cd6a25e87 100644\n--- a/gcc/config/i386/driver-i386.cc\n+++ b/gcc/config/i386/driver-i386.cc\n@@ -501,6 +501,16 @@ const char *host_detect_local_cpu (int argc, const char **argv)\n else\n \tprocessor = PROCESSOR_PENTIUM;\n }\n+ else if (vendor == VENDOR_HYGON)\n+ {\n+ processor = PROCESSOR_GENERIC;\n+ if (model == 4)\n+\tprocessor = PROCESSOR_C86_4G_M4;\n+ else if (model == 6)\n+\tprocessor = PROCESSOR_C86_4G_M6;\n+ else if (model >= 7)\n+\tprocessor = PROCESSOR_C86_4G_M7;\n+ }\n else if (vendor == VENDOR_CENTAUR)\n {\n processor = PROCESSOR_GENERIC;\n@@ -850,6 +860,15 @@ const char *host_detect_local_cpu (int argc, const char **argv)\n case PROCESSOR_SHIJIDADAO:\n cpu = \"shijidadao\";\n break;\n+ case PROCESSOR_C86_4G_M4:\n+ cpu = \"c86-4g-m4\";\n+ break;\n+ case PROCESSOR_C86_4G_M6:\n+ cpu = \"c86-4g-m6\";\n+ break;\n+ case PROCESSOR_C86_4G_M7:\n+ cpu = \"c86-4g-m7\";\n+ break;\n \n default:\n /* Use something reasonable. */\ndiff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc\nindex 15e82956d..bf686c359 100644\n--- a/gcc/config/i386/i386-c.cc\n+++ b/gcc/config/i386/i386-c.cc\n@@ -303,7 +303,18 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,\n def_or_undef (parse_in, \"__novalake\");\n def_or_undef (parse_in, \"__novalake__\");\n break;\n-\n+ case PROCESSOR_C86_4G_M4:\n+ def_or_undef (parse_in, \"__c86_4g_m4\");\n+ def_or_undef (parse_in, \"__c86_4g_m4__\");\n+ break;\n+ case PROCESSOR_C86_4G_M6:\n+ def_or_undef (parse_in, \"__c86_4g_m6\");\n+ def_or_undef (parse_in, \"__c86_4g_m6__\");\n+ break;\n+ case PROCESSOR_C86_4G_M7:\n+ def_or_undef (parse_in, \"__c86_4g_m7\");\n+ def_or_undef (parse_in, \"__c86_4g_m7__\");\n+ break;\n /* use PROCESSOR_max to not set/unset the arch macro. */\n case PROCESSOR_max:\n break;\n@@ -512,6 +523,15 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,\n case PROCESSOR_NOVALAKE:\n def_or_undef (parse_in, \"__tune_novalake__\");\n break;\n+ case PROCESSOR_C86_4G_M4:\n+ def_or_undef (parse_in, \"__tune_c86_4g_m4__\");\n+ break;\n+ case PROCESSOR_C86_4G_M6:\n+ def_or_undef (parse_in, \"__tune_c86_4g_m6__\");\n+ break;\n+ case PROCESSOR_C86_4G_M7:\n+ def_or_undef (parse_in, \"__tune_c86_4g_m7__\");\n+ break;\n case PROCESSOR_INTEL:\n case PROCESSOR_GENERIC:\n break;\ndiff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc\nindex 7459cde4b..7ffe9cd2a 100644\n--- a/gcc/config/i386/i386-options.cc\n+++ b/gcc/config/i386/i386-options.cc\n@@ -185,6 +185,10 @@ along with GCC; see the file COPYING3. If not see\n #define m_ZNVER (m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6)\n #define m_AMD_MULTIPLE (m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER \\\n \t\t\t| m_ZNVER)\n+#define m_C86_4G_M4 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M4)\n+#define m_C86_4G_M6 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M6)\n+#define m_C86_4G_M7 (HOST_WIDE_INT_1U<<PROCESSOR_C86_4G_M7)\n+#define m_C86_4G (m_C86_4G_M4 | m_C86_4G_M6 | m_C86_4G_M7)\n \n #define m_GENERIC (HOST_WIDE_INT_1U<<PROCESSOR_GENERIC)\n \n@@ -814,7 +818,10 @@ static const struct processor_costs *processor_cost_table[] =\n &znver3_cost,\t\t/* PROCESSOR_ZNVER3.\t\t*/\n &znver4_cost,\t\t/* PROCESSOR_ZNVER4.\t\t*/\n &znver5_cost,\t\t/* PROCESSOR_ZNVER5.\t\t*/\n- &znver5_cost\t\t/* PROCESSOR_ZNVER6.\t\t*/\n+ &znver5_cost,\t\t/* PROCESSOR_ZNVER6.\t\t*/\n+ &c86_4g_m4_cost,\t/* PROCESSOR_C86_4G_M4.\t\t*/\n+ &c86_4g_m6_cost,\t/* PROCESSOR_C86_4G_M6.\t\t*/\n+ &c86_4g_m7_cost\t/* PROCESSOR_C86_4G_M7.\t\t*/\n };\n \n /* Guarantee that the array is aligned with enum processor_type. */\ndiff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc\nindex 4c32e2178..f61ec9e4f 100644\n--- a/gcc/config/i386/i386.cc\n+++ b/gcc/config/i386/i386.cc\n@@ -25691,7 +25691,10 @@ ix86_reassociation_width (unsigned int op, machine_mode mode)\n /* Znver1-4 Integer vector instructions execute in FP unit\n \t and can execute 3 additions and one multiplication per cycle. */\n if ((ix86_tune == PROCESSOR_ZNVER1 || ix86_tune == PROCESSOR_ZNVER2\n-\t || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4)\n+\t || ix86_tune == PROCESSOR_ZNVER3 || ix86_tune == PROCESSOR_ZNVER4\n+\t || ix86_tune == PROCESSOR_C86_4G_M4\n+\t || ix86_tune == PROCESSOR_C86_4G_M6\n+\t || ix86_tune == PROCESSOR_C86_4G_M7)\n \t && INTEGRAL_MODE_P (mode) && op != PLUS && op != MINUS)\n \treturn 1;\n /* Znver5 can do 2 integer multiplications per cycle with latency\ndiff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h\nindex 888edfed8..80dafd1f9 100644\n--- a/gcc/config/i386/i386.h\n+++ b/gcc/config/i386/i386.h\n@@ -2384,6 +2384,9 @@ enum processor_type\n PROCESSOR_ZNVER4,\n PROCESSOR_ZNVER5,\n PROCESSOR_ZNVER6,\n+ PROCESSOR_C86_4G_M4,\n+ PROCESSOR_C86_4G_M6,\n+ PROCESSOR_C86_4G_M7,\n PROCESSOR_max\n };\n \n@@ -2547,6 +2550,21 @@ constexpr wide_int_bitmask PTA_LUJIAZUI = PTA_64BIT | PTA_MMX | PTA_SSE\n constexpr wide_int_bitmask PTA_YONGFENG = PTA_LUJIAZUI | PTA_AVX | PTA_AVX2\n | PTA_F16C | PTA_FMA | PTA_SHA;\n \n+constexpr wide_int_bitmask PTA_C86_4G_M4 = PTA_64BIT | PTA_MMX | PTA_SSE\n+ | PTA_SSE2 | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3\n+ | PTA_SSE4_1 | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2\n+ | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE\n+ | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX\n+ | PTA_RDSEED | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES\n+ | PTA_SHA | PTA_LZCNT | PTA_POPCNT;\n+constexpr wide_int_bitmask PTA_C86_4G_M6 = PTA_C86_4G_M4;\n+constexpr wide_int_bitmask PTA_C86_4G_M7 = PTA_C86_4G_M4 | PTA_AVX512F\n+ | PTA_AVX512DQ | PTA_AVX512IFMA | PTA_AVX512CD | PTA_AVX512BW | PTA_AVX512VL\n+ | PTA_AVX512BF16 | PTA_AVX512VBMI | PTA_AVX512VBMI2 | PTA_GFNI\n+ | PTA_AVX512VNNI | PTA_AVX512BITALG | PTA_AVX512VPOPCNTDQ\n+ | PTA_AVX512VP2INTERSECT | PTA_VAES | PTA_AVXVNNI | PTA_VPCLMULQDQ\n+ | PTA_WBNOINVD | PTA_CLWB;\n+\n #ifndef GENERATOR_FILE\n \n #include \"insn-attr-common.h\"\ndiff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md\nindex c05161fc8..6a00ba108 100644\n--- a/gcc/config/i386/i386.md\n+++ b/gcc/config/i386/i386.md\n@@ -530,7 +530,7 @@ (define_constants\n (define_attr \"cpu\" \"none,pentium,pentiumpro,geode,k6,athlon,k8,core2,nehalem,\n \t\t atom,slm,glm,haswell,generic,lujiazui,yongfeng,amdfam10,bdver1,\n \t\t bdver2,bdver3,bdver4,btver2,znver1,znver2,znver3,znver4,\n-\t\t znver5,znver6\"\n+\t\t znver5,znver6,c86_4g_m4,c86_4g_m6,c86_4g_m7\"\n (const (symbol_ref \"ix86_schedule\")))\n \n ;; A basic instruction type. Refinements due to arguments to be\n@@ -1427,6 +1427,8 @@ (define_mode_iterator PTR\n (include \"haswell.md\")\n (include \"lujiazui.md\")\n (include \"yongfeng.md\")\n+(include \"c86-4g.md\")\n+(include \"c86-4g-m7.md\")\n \n \f\n ;; Operand and operator predicates and constraints\n@@ -2038,6 +2040,7 @@ (define_insn \"*cmpi<unord>xf_i387\"\n (set_attr \"athlon_decode\" \"vector\")\n (set_attr \"amdfam10_decode\" \"direct\")\n (set_attr \"bdver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"znver1_decode\" \"double\")])\n \n (define_insn \"*cmpx<unord><MODEF:mode>\"\n@@ -2091,6 +2094,7 @@ (define_insn \"*cmpi<unord><MODEF:mode>\"\n (set_attr \"amdfam10_decode\" \"direct\")\n (set_attr \"bdver1_decode\" \"double\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set (attr \"enabled\")\n (if_then_else\n (match_test (\"SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH\"))\n@@ -2482,6 +2486,7 @@ (define_insn \"*movxi_internal_avx512f\"\n }\n }\n [(set_attr \"type\" \"sselog1,sselog1,ssemov,ssemov\")\n+ (set_attr \"c86_attr\" \"sselogic,sselogic,*,*\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -2506,6 +2511,7 @@ (define_insn \"*movoi_internal_avx\"\n }\n [(set_attr \"isa\" \"*,avx2,*,*\")\n (set_attr \"type\" \"sselog1,sselog1,ssemov,ssemov\")\n+ (set_attr \"c86_attr\" \"sselogic,sselogic,*,*\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"OI\")])\n \n@@ -2548,6 +2554,10 @@ (define_insn \"*movti_internal\"\n \t (const_string \"sselog1\")\n \t ]\n \t (const_string \"ssemov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"2,3\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"prefix\")\n (if_then_else (eq_attr \"type\" \"sselog1,ssemov\")\n (const_string \"maybe_vex\")\n@@ -2691,6 +2701,10 @@ (define_insn \"*movdi_internal\"\n \t (const_string \"lea\")\n \t ]\n \t (const_string \"imov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"12\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"modrm\")\n (if_then_else\n (and (eq_attr \"alternative\" \"4\") (eq_attr \"type\" \"imov\"))\n@@ -2911,6 +2925,10 @@ (define_insn \"*movsi_internal\"\n \t (const_string \"lea\")\n \t ]\n \t (const_string \"imov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"8\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"prefix\")\n (if_then_else (eq_attr \"type\" \"sselog1,ssemov\")\n (const_string \"maybe_vex\")\n@@ -3085,6 +3103,10 @@ (define_insn \"*movhi_internal\"\n \t (const_string \"imovx\")\n \t ]\n \t (const_string \"imov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"11\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"prefix\")\n \t(cond [(eq_attr \"alternative\" \"4,5,6,7,8\")\n \t\t (const_string \"vex\")\n@@ -3366,6 +3388,7 @@ (define_insn \"swap<mode>\"\n (set_attr \"pent_pair\" \"np\")\n (set_attr \"athlon_decode\" \"vector\")\n (set_attr \"amdfam10_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"bdver1_decode\" \"double\")])\n \n (define_insn \"*swap<mode>\"\n@@ -3391,6 +3414,7 @@ (define_insn \"*swap<mode>\"\n (set_attr \"pent_pair\" \"np\")\n (set_attr \"athlon_decode\" \"vector\")\n (set_attr \"amdfam10_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"bdver1_decode\" \"double\")])\n \n (define_peephole2\n@@ -4068,6 +4092,7 @@ (define_insn \"*movtf_internal\"\n }\n [(set_attr \"isa\" \"*,*,*,x64,x64\")\n (set_attr \"type\" \"sselog1,ssemov,ssemov,multi,multi\")\n+ (set_attr \"c86_attr\" \"sselogic,*,*,*,*\")\n (set (attr \"prefix\")\n (if_then_else (eq_attr \"type\" \"sselog1,ssemov\")\n (const_string \"maybe_vex\")\n@@ -4239,6 +4264,10 @@ (define_insn \"*movdf_internal\"\n \t\t (const_string \"sselog1\")\n \t ]\n \t (const_string \"ssemov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"12,16\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"modrm\")\n (if_then_else (eq_attr \"alternative\" \"11\")\n (const_string \"0\")\n@@ -4411,6 +4440,10 @@ (define_insn \"*movsf_internal\"\n \t\t (const_string \"mmxmov\")\n \t ]\n \t (const_string \"ssemov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"5\")\n+ (const_string \"sselogic\")\n+ (const_string \"*\")))\n (set (attr \"prefix\")\n (if_then_else (eq_attr \"type\" \"sselog1,ssemov\")\n (const_string \"maybe_vex\")\n@@ -4759,6 +4792,10 @@ (define_insn \"*zero_extendsidi2\"\n \t (const_string \"mskmov\")\n \t ]\n \t (const_string \"imovx\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"10,11\")\n+ (const_string \"vpmovx\")\n+ (const_string \"*\")))\n (set (attr \"prefix_extra\")\n (if_then_else (eq_attr \"alternative\" \"10,11\")\n (const_string \"1\")\n@@ -5168,6 +5205,10 @@ (define_insn \"extendhisi2\"\n (if_then_else (eq_attr \"prefix_0f\" \"0\")\n \t(const_string \"double\")\n \t(const_string \"direct\")))\n+ (set (attr \"c86_decode\")\n+ (if_then_else (eq_attr \"prefix_0f\" \"0\")\n+\t(const_string \"double\")\n+\t(const_string \"direct\")))\n (set (attr \"modrm\")\n (if_then_else (eq_attr \"prefix_0f\" \"0\")\n \t(const_string \"0\")\n@@ -6075,6 +6116,7 @@ (define_insn \"floathi<mode>2\"\n [(set_attr \"type\" \"fmov\")\n (set_attr \"mode\" \"<MODE>\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"fp_int_src\" \"true\")])\n \n (define_insn \"float<SWI48x:mode>xf2\"\n@@ -6085,6 +6127,7 @@ (define_insn \"float<SWI48x:mode>xf2\"\n [(set_attr \"type\" \"fmov\")\n (set_attr \"mode\" \"XF\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"fp_int_src\" \"true\")])\n \n (define_expand \"float<SWI48x:mode><MODEF:mode>2\"\n@@ -6119,6 +6162,7 @@ (define_insn \"*float<SWI48:mode><MODEF:mode>2\"\n (set_attr \"amdfam10_decode\" \"*,vector,double\")\n (set_attr \"bdver1_decode\" \"*,double,direct\")\n (set_attr \"znver1_decode\" \"double,*,*\")\n+ (set_attr \"c86_decode\" \"double,*,*\")\n (set_attr \"fp_int_src\" \"true\")\n (set (attr \"enabled\")\n (if_then_else\n@@ -6157,6 +6201,7 @@ (define_insn \"*floatdi<MODEF:mode>2_i387\"\n [(set_attr \"type\" \"fmov\")\n (set_attr \"mode\" \"<MODEF:MODE>\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"fp_int_src\" \"true\")])\n \n ;; Try TARGET_USE_VECTOR_CONVERTS, but not so hard as to require extra memory\n@@ -12929,6 +12974,7 @@ (define_insn_and_split \"*anddi_1_btr\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n ;; Turn *anddi_1 into *andsi_1_zext if possible.\n@@ -13964,6 +14010,7 @@ (define_insn_and_split \"*iordi_1_bts\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn_and_split \"*xordi_1_btc\"\n@@ -13988,6 +14035,7 @@ (define_insn_and_split \"*xordi_1_btc\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n ;; Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask)\n@@ -19167,6 +19215,7 @@ (define_insn \"*<btsc><mode>\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"<MODE>\")])\n \n ;; Avoid useless masking of count operand.\n@@ -19235,6 +19284,7 @@ (define_insn \"*btr<mode>\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"<MODE>\")])\n \n ;; Avoid useless masking of count operand.\n@@ -19376,6 +19426,7 @@ (define_insn \"*btsq_imm\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"*btrq_imm\"\n@@ -19389,6 +19440,7 @@ (define_insn \"*btrq_imm\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"*btcq_imm\"\n@@ -19402,6 +19454,7 @@ (define_insn \"*btcq_imm\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"DI\")])\n \n ;; Allow Nocona to avoid these instructions if a register is available.\n@@ -21379,6 +21432,7 @@ (define_insn_and_split \"*tzcnt<mode>_1\"\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"prefix_rep\" \"1\")\n (set_attr \"btver2_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"<MODE>\")])\n \n ; False dependency happens when destination is only updated by tzcnt,\n@@ -21398,6 +21452,7 @@ (define_insn \"*tzcnt<mode>_1_falsedep\"\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"prefix_rep\" \"1\")\n (set_attr \"btver2_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"*bsf<mode>_1\"\n@@ -21412,6 +21467,7 @@ (define_insn \"*bsf<mode>_1\"\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"btver2_decode\" \"double\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn_and_split \"ctz<mode>2\"\n@@ -21474,6 +21530,7 @@ (define_insn \"*ctz<mode>2_falsedep\"\n gcc_unreachable ();\n }\n [(set_attr \"type\" \"alu1\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"prefix_rep\" \"1\")\n (set_attr \"mode\" \"<MODE>\")])\n@@ -21499,6 +21556,7 @@ (define_insn_and_split \"*ctzsi2_zext\"\n (clobber (reg:CC FLAGS_REG))])]\n \"ix86_expand_clear (operands[0]);\"\n [(set_attr \"type\" \"alu1\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"prefix_rep\" \"1\")\n (set_attr \"mode\" \"SI\")])\n@@ -21519,6 +21577,7 @@ (define_insn \"*ctzsi2_zext_falsedep\"\n \"TARGET_BMI && TARGET_64BIT\"\n \"tzcnt{l}\\t{%1, %k0|%k0, %1}\"\n [(set_attr \"type\" \"alu1\")\n+ (set_attr \"c86_decode\" \"double\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"prefix_rep\" \"1\")\n (set_attr \"mode\" \"SI\")])\n@@ -21596,6 +21655,7 @@ (define_insn \"bsr_rex64\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"bsr_rex64_1\"\n@@ -21608,6 +21668,7 @@ (define_insn \"bsr_rex64_1\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"bsr_rex64_1_zext\"\n@@ -21623,6 +21684,7 @@ (define_insn \"bsr_rex64_1_zext\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"DI\")])\n \n (define_insn \"bsr\"\n@@ -21637,6 +21699,7 @@ (define_insn \"bsr\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"SI\")])\n \n (define_insn \"bsr_1\"\n@@ -21649,6 +21712,7 @@ (define_insn \"bsr_1\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"SI\")])\n \n (define_insn \"bsr_zext_1\"\n@@ -21663,6 +21727,7 @@ (define_insn \"bsr_zext_1\"\n [(set_attr \"type\" \"alu1\")\n (set_attr \"prefix_0f\" \"1\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"SI\")])\n \n ; As bsr is undefined behavior on zero and for other input\n@@ -22977,6 +23042,7 @@ (define_insn \"*bswaphi2_movbe\"\n (set_attr \"pent_pair\" \"np,*,*\")\n (set_attr \"athlon_decode\" \"vector,*,*\")\n (set_attr \"amdfam10_decode\" \"double,*,*\")\n+ (set_attr \"c86_decode\" \"vector,*,*\")\n (set_attr \"bdver1_decode\" \"double,*,*\")\n (set_attr \"mode\" \"QI,HI,HI\")])\n \n@@ -22989,6 +23055,7 @@ (define_insn \"*bswaphi2\"\n (set_attr \"pent_pair\" \"np\")\n (set_attr \"athlon_decode\" \"vector\")\n (set_attr \"amdfam10_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"bdver1_decode\" \"double\")\n (set_attr \"mode\" \"QI\")])\n \n@@ -23013,6 +23080,7 @@ (define_insn \"bswaphisi2_lowpart\"\n (set_attr \"pent_pair\" \"np\")\n (set_attr \"athlon_decode\" \"vector\")\n (set_attr \"amdfam10_decode\" \"double\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"bdver1_decode\" \"double\")\n (set_attr \"mode\" \"QI\")])\n \n@@ -24093,6 +24161,7 @@ (define_insn \"sqrtxf2\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"mode\" \"XF\")\n (set_attr \"athlon_decode\" \"direct\")\n+ (set_attr \"c86_attr\" \"sqrt\")\n (set_attr \"amdfam10_decode\" \"direct\")\n (set_attr \"bdver1_decode\" \"direct\")])\n \n@@ -24261,6 +24330,7 @@ (define_insn \"fpremxf4_i387\"\n \"fprem\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"fmodxf3\"\n@@ -24333,6 +24403,7 @@ (define_insn \"fprem1xf4_i387\"\n \"fprem1\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"remainderxf3\"\n@@ -24408,6 +24479,7 @@ (define_insn \"<sincos>xf2\"\n \"f<sincos>\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"<sincos><mode>2\"\n@@ -24439,6 +24511,7 @@ (define_insn \"sincosxf3\"\n \"fsincos\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"sincos<mode>3\"\n@@ -24472,6 +24545,7 @@ (define_insn \"fptanxf4_i387\"\n \"fptan\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"tanxf2\"\n@@ -24514,6 +24588,7 @@ (define_insn \"atan2xf3\"\n \"fpatan\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"atan2<mode>3\"\n@@ -24817,6 +24892,7 @@ (define_insn \"fyl2xxf3_i387\"\n \"fyl2x\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"logxf2\"\n@@ -24914,6 +24990,7 @@ (define_insn \"fyl2xp1xf3_i387\"\n \"fyl2xp1\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"log1pxf2\"\n@@ -24954,6 +25031,7 @@ (define_insn \"fxtractxf3_i387\"\n \"fxtract\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"logbxf2\"\n@@ -25034,6 +25112,7 @@ (define_insn \"*f2xm1xf2_i387\"\n \"f2xm1\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_insn \"fscalexf4_i387\"\n@@ -25049,6 +25128,7 @@ (define_insn \"fscalexf4_i387\"\n \"fscale\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"expNcorexf3\"\n@@ -25367,6 +25447,7 @@ (define_insn \"rintxf2\"\n \"frndint\"\n [(set_attr \"type\" \"fpspc\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"XF\")])\n \n (define_expand \"rinthf2\"\n@@ -27185,6 +27266,7 @@ (define_insn \"<code><mode>3\"\n v<maxmin_float><ssemodesuffix>\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"prefix\" \"orig,vex\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"type\" \"sseadd\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -27229,6 +27311,7 @@ (define_insn \"*ieee_s<ieee_maxmin><mode>3\"\n v<ieee_maxmin><ssemodesuffix>\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"prefix\" \"orig,maybe_evex\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"type\" \"sseadd\")\n (set_attr \"mode\" \"<MODE>\")])\n \ndiff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md\nindex a23474716..8c50480b7 100644\n--- a/gcc/config/i386/mmx.md\n+++ b/gcc/config/i386/mmx.md\n@@ -664,6 +664,7 @@ (define_insn \"sse_movntq\"\n [(set_attr \"isa\" \"*,x64\")\n (set_attr \"mmx_isa\" \"native,*\")\n (set_attr \"type\" \"mmxmov,ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"mode\" \"DI\")])\n \n (define_expand \"movq_<mode>_to_sse\"\n@@ -1324,6 +1325,7 @@ (define_insn \"*mmx_blendps\"\n vblendps\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*\")\n (set_attr \"prefix_extra\" \"1\")\n@@ -1344,6 +1346,7 @@ (define_insn \"mmx_blendvps\"\n vblendvps\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*\")\n (set_attr \"prefix_extra\" \"1\")\n@@ -3599,6 +3602,7 @@ (define_insn \"*mmx_pmaddwd\"\n [(set_attr \"isa\" \"*,sse2_noavx,avx\")\n (set_attr \"mmx_isa\" \"native,*,*\")\n (set_attr \"type\" \"mmxmul,sseiadd,sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"mode\" \"DI,TI,TI\")])\n \n (define_expand \"mmx_pmulhrwv4hi3\"\n@@ -4346,6 +4350,7 @@ (define_insn \"mmx_pblendvb_v8qi\"\n vpblendvb\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -4422,6 +4427,7 @@ (define_insn \"mmx_pblendvb_<mode>\"\n vpblendvb\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -5040,6 +5046,7 @@ (define_insn \"sse4_1_<code>v4qiv4hi2\"\n \"%vpmov<extsuffix>bw\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -5072,6 +5079,7 @@ (define_insn \"sse4_1_<code>v2hiv2si2\"\n \"%vpmov<extsuffix>wd\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -5104,6 +5112,7 @@ (define_insn \"sse4_1_<code>v2qiv2si2\"\n \"%vpmov<extsuffix>bd\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -5130,6 +5139,7 @@ (define_insn \"sse4_1_<code>v2qiv2hi2\"\n \"%vpmov<extsuffix>bw\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -5306,6 +5316,7 @@ (define_insn \"*mmx_pinsrd\"\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"TI\")])\n@@ -5345,6 +5356,7 @@ (define_insn \"*mmx_pinsrw\"\n [(set_attr \"isa\" \"*,sse2_noavx,avx,sse4\")\n (set_attr \"mmx_isa\" \"native,*,*,*\")\n (set_attr \"type\" \"mmxcvt,sselog,sselog,sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"mode\" \"DI,TI,TI,TI\")])\n \n@@ -5395,6 +5407,7 @@ (define_insn \"*mmx_pinsrb\"\n }\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -5417,6 +5430,7 @@ (define_insn \"*mmx_pextrw\"\n (set_attr \"addr\" \"*,*,gpr16,*\")\n (set_attr \"mmx_isa\" \"native,*,*,*\")\n (set_attr \"type\" \"mmxcvt,sselog1,sselog1,sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_vex,maybe_vex,maybe_evex\")\n (set_attr \"mode\" \"DI,TI,TI,TI\")])\n@@ -5452,6 +5466,7 @@ (define_insn \"*mmx_pextrw<mode>\"\n (set_attr \"addr\" \"*,*,gpr16,*,*,*\")\n (set_attr \"mmx_isa\" \"native,*,*,*,*,*\")\n (set_attr \"type\" \"mmxcvt,sselog1,sselog1,sselog1,sseishft1,sseishft1\")\n+ (set_attr \"c86_attr\" \"extr,extr,extr,extr,*,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_vex,maybe_vex,maybe_evex,orig,maybe_evex\")\n (set_attr \"mode\" \"DI,TI,TI,TI,TI,TI\")])\n@@ -5470,6 +5485,7 @@ (define_insn \"*mmx_pextrw_zext\"\n [(set_attr \"isa\" \"*,sse2\")\n (set_attr \"mmx_isa\" \"native,*\")\n (set_attr \"type\" \"mmxcvt,sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_vex\")\n (set_attr \"mode\" \"DI,TI\")])\n@@ -5488,6 +5504,7 @@ (define_insn \"*mmx_pextrb\"\n [(set_attr \"isa\" \"noavx,noavx,avx,avx\")\n (set_attr \"addr\" \"*,gpr16,*,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -5503,6 +5520,7 @@ (define_insn \"*mmx_pextrb_zext\"\n \"%vpextrb\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -5629,6 +5647,7 @@ (define_insn \"*mmx_pblendw64\"\n vpblendw\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -5647,6 +5666,7 @@ (define_insn \"*mmx_pblendw32\"\n vpblendw\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -5829,6 +5849,7 @@ (define_insn \"*vec_extractv2si_1\"\n \t\t (const_string \"*\")))\n (set_attr \"mmx_isa\" \"native,*,*,*,*,native,*,*\")\n (set_attr \"type\" \"mmxcvt,ssemov,ssemov,sseshuf1,sseshuf1,mmxmov,ssemov,imov\")\n+ (set_attr \"c86_attr\" \"*,extr,extr,*,*,*,*,*\")\n (set (attr \"length_immediate\")\n (if_then_else (eq_attr \"alternative\" \"1,2,3,4\")\n \t\t (const_string \"1\")\n@@ -5856,6 +5877,7 @@ (define_insn \"*vec_extractv2si_1_zext\"\n \"%vpextrd\\t{$1, %1, %k0|%k0, %1, 1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -6010,6 +6032,7 @@ (define_insn \"*pinsrw\"\n }\n [(set_attr \"isa\" \"noavx,avx,sse4\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -6062,6 +6085,7 @@ (define_insn \"*pinsrb\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,vex\")\n@@ -6080,6 +6104,7 @@ (define_insn \"*pextrw\"\n [(set_attr \"isa\" \"*,sse4_noavx,avx\")\n (set_attr \"addr\" \"*,gpr16,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"TI\")])\n@@ -6113,6 +6138,7 @@ (define_insn \"*pextrw<mode>\"\n [(set_attr \"isa\" \"*,sse4_noavx,avx,noavx,avx\")\n (set_attr \"addr\" \"*,gpr16,*,*,*\")\n (set_attr \"type\" \"sselog1,sselog1,sselog1,sseishft1,sseishft1\")\n+ (set_attr \"c86_attr\" \"extr,extr,extr,*,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex,orig,maybe_evex,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -6126,6 +6152,7 @@ (define_insn \"*pextrw_zext\"\n \"TARGET_SSE2\"\n \"%vpextrw\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"TI\")])\n@@ -6144,6 +6171,7 @@ (define_insn \"*pextrb\"\n [(set_attr \"isa\" \"noavx,noavx,avx,avx\")\n (set_attr \"addr\" \"*,gpr16,*,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -6159,6 +6187,7 @@ (define_insn \"*pextrb_zext\"\n \"%vpextrb\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -6511,6 +6540,7 @@ (define_insn \"*mmx_psadbw\"\n [(set_attr \"isa\" \"*,sse2_noavx,avx\")\n (set_attr \"mmx_isa\" \"native,*,*\")\n (set_attr \"type\" \"mmxshft,sseiadd,sseiadd\")\n+ (set_attr \"c86_attr\" \"sadbw\")\n (set_attr \"mode\" \"DI,TI,TI\")])\n \n (define_expand \"reduc_<code>_scal_<mode>\"\n@@ -6890,6 +6920,7 @@ (define_insn \"*mmx_maskmovq\"\n \"maskmovq\\t{%2, %1|%1, %2}\"\n [(set_attr \"type\" \"mmxcvt\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"DI\")])\n \n (define_int_iterator EMMS\ndiff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md\nindex a3f68ad9c..16c20c0ea 100644\n--- a/gcc/config/i386/sse.md\n+++ b/gcc/config/i386/sse.md\n@@ -1794,6 +1794,11 @@ (define_insn \"<avx512>_blendm<mode>\"\n }\n }\n [(set_attr \"type\" \"ssemov\")\n+ (set (attr \"c86_attr\")\n+ (if_then_else (and (match_test \"REG_P (operands[1])\")\n+\t\t\t(match_test \"REGNO (operands[1]) != REGNO (operands[0])\"))\n+ (const_string \"blend\")\n+ (const_string \"*\")))\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -1808,6 +1813,7 @@ (define_insn \"<avx512>_blendm<mode>\"\n vmovdqu<ssescalarsize>\\t{%2, %0%{%3%}%N1|%0%{%3%}%N1, %2}\n vpblendm<sseintmodesuffix>\\t{%2, %1, %0%{%3%}|%0%{%3%}, %1, %2}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"*,blend\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -2034,6 +2040,7 @@ (define_insn \"sse2_movnti<mode>\"\n \"TARGET_SSE2\"\n \"movnti\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix_data16\" \"0\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -2045,6 +2052,7 @@ (define_insn \"<sse>_movnt<mode>\"\n \"TARGET_SSE\"\n \"%vmovnt<ssemodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -2060,6 +2068,7 @@ (define_insn \"<sse2>_movnt<mode>\"\n (match_test \"TARGET_AVX\")\n (const_string \"*\")\n (const_string \"1\")))\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -2359,6 +2368,7 @@ (define_insn \"ktest<mode>\"\n \"ktest<mskmodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"mode\" \"<MODE>\")\n (set_attr \"type\" \"msklog\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"prefix\" \"vex\")])\n \n (define_insn \"*kortest<mode>\"\n@@ -2371,6 +2381,7 @@ (define_insn \"*kortest<mode>\"\n \"kortest<mskmodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"mode\" \"<MODE>\")\n (set_attr \"type\" \"msklog\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"prefix\" \"vex\")])\n \n (define_insn \"kortest<mode>_ccc\"\n@@ -2939,6 +2950,7 @@ (define_insn \"<sse>_rcp<mode>2\"\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"atom_sse_attr\" \"rcp\")\n (set_attr \"btver2_sse_attr\" \"rcp\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -2958,6 +2970,7 @@ (define_insn \"sse_vmrcpv4sf2\"\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"atom_sse_attr\" \"rcp\")\n (set_attr \"btver2_sse_attr\" \"rcp\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"SF\")])\n \n@@ -2978,6 +2991,7 @@ (define_insn \"*sse_vmrcpv4sf2\"\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"atom_sse_attr\" \"rcp\")\n (set_attr \"btver2_sse_attr\" \"rcp\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"SF\")])\n \n@@ -3027,6 +3041,7 @@ (define_insn \"<mask_codefor>rcp14<mode><mask_name>\"\n \"TARGET_AVX512F\"\n \"vrcp14<ssemodesuffix>\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3041,6 +3056,7 @@ (define_insn \"srcp14<mode>\"\n \"TARGET_AVX512F\"\n \"vrcp14<ssescalarmodesuffix>\\t{%1, %2, %0|%0, %2, %<iptr>1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3058,6 +3074,7 @@ (define_insn \"srcp14<mode>_mask\"\n \"TARGET_AVX512F\"\n \"vrcp14<ssescalarmodesuffix>\\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3093,6 +3110,7 @@ (define_insn \"<sse>_sqrt<mode>2<mask_name><round_name>\"\n (set_attr \"type\" \"sse\")\n (set_attr \"atom_sse_attr\" \"sqrt\")\n (set_attr \"btver2_sse_attr\" \"sqrt\")\n+ (set_attr \"c86_attr\" \"sqrt\")\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3112,6 +3130,7 @@ (define_insn \"<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>\"\n (set_attr \"atom_sse_attr\" \"sqrt\")\n (set_attr \"prefix\" \"<round_scalar_prefix>\")\n (set_attr \"btver2_sse_attr\" \"sqrt\")\n+ (set_attr \"c86_attr\" \"sqrt\")\n (set_attr \"mode\" \"<ssescalarmode>\")])\n \n (define_insn \"*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>\"\n@@ -3131,6 +3150,7 @@ (define_insn \"*<sse>_vmsqrt<mode>2<mask_scalar_name><round_scalar_name>\"\n (set_attr \"atom_sse_attr\" \"sqrt\")\n (set_attr \"prefix\" \"<round_scalar_prefix>\")\n (set_attr \"btver2_sse_attr\" \"sqrt\")\n+ (set_attr \"c86_attr\" \"sqrt\")\n (set_attr \"mode\" \"<ssescalarmode>\")])\n \n (define_expand \"rsqrt<mode>2\"\n@@ -3181,6 +3201,7 @@ (define_insn \"<mask_codefor>rsqrt14<mode><mask_name>\"\n \"TARGET_AVX512F\"\n \"vrsqrt14<ssemodesuffix>\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3195,6 +3216,7 @@ (define_insn \"rsqrt14<mode>\"\n \"TARGET_AVX512F\"\n \"vrsqrt14<ssescalarmodesuffix>\\t{%1, %2, %0|%0, %2, %<iptr>1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3212,6 +3234,7 @@ (define_insn \"rsqrt14_<mode>_mask\"\n \"TARGET_AVX512F\"\n \"vrsqrt14<ssescalarmodesuffix>\\t{%1, %2, %0%{%4%}%N3|%0%{%4%}%N3, %2, %<iptr>1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"rcp\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3336,6 +3359,7 @@ (define_insn \"*<code><mode>3<mask_name><round_saeonly_name>\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd\")\n (set_attr \"btver2_sse_attr\" \"maxmin\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"<mask_prefix3>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3469,6 +3493,7 @@ (define_insn \"ieee_<ieee_maxmin><mode>3<mask_name><round_saeonly_name>\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd\")\n (set_attr \"btver2_sse_attr\" \"maxmin\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"<mask_prefix3>\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -3493,6 +3518,7 @@ (define_insn \"*ieee_<ieee_maxmin><mode>3\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd\")\n (set_attr \"btver2_sse_attr\" \"maxmin\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set (attr \"prefix\")\n (cond [(eq_attr \"alternative\" \"0\")\n \t (const_string \"orig\")\n@@ -3540,6 +3566,7 @@ (define_insn \"*<sse>_vm<code><mode>3<mask_scalar_name><round_saeonly_scalar_name\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sse\")\n (set_attr \"btver2_sse_attr\" \"maxmin\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"<round_saeonly_scalar_prefix>\")\n (set_attr \"mode\" \"<ssescalarmode>\")])\n \n@@ -3736,6 +3763,7 @@ (define_insn \"avx_h<insn>v4df3\"\n \"TARGET_AVX\"\n \"vh<plusminus_mnemonic>pd\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"V4DF\")])\n@@ -3781,6 +3809,7 @@ (define_insn \"*sse3_haddv2df3\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"type\" \"sseadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"V2DF\")])\n \n@@ -3803,6 +3832,7 @@ (define_insn \"sse3_hsubv2df3\"\n vhsubpd\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"V2DF\")])\n@@ -3823,6 +3853,7 @@ (define_insn \"*sse3_haddv2df3_low\"\n vhaddpd\\t{%1, %1, %0|%0, %1, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"V2DF\")])\n \n@@ -3841,6 +3872,7 @@ (define_insn \"*sse3_hsubv2df3_low\"\n vhsubpd\\t{%1, %1, %0|%0, %1, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"V2DF\")])\n \n@@ -3884,6 +3916,7 @@ (define_insn \"avx_h<insn>v8sf3\"\n \"TARGET_AVX\"\n \"vh<plusminus_mnemonic>ps\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"V8SF\")])\n@@ -3915,6 +3948,7 @@ (define_insn \"sse3_h<insn>v4sf3\"\n vh<plusminus_mnemonic>ps\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"*,gpr16\")\n (set_attr \"atom_unit\" \"complex\")\n (set_attr \"prefix\" \"orig,vex\")\n@@ -4253,6 +4287,7 @@ (define_insn \"<mask_codefor>reducep<mode><mask_name><round_saeonly_name>\"\n \"TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))\"\n \"vreduce<ssemodesuffix>\\t{%2, <round_saeonly_mask_op3>%1, %0<mask_operand3>|%0<mask_operand3>, %1<round_saeonly_mask_op3>, %2}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -4269,6 +4304,7 @@ (define_insn \"reduces<mode><mask_scalar_name><round_saeonly_scalar_name>\"\n \"TARGET_AVX512DQ || (VALID_AVX512FP16_REG_MODE (<MODE>mode))\"\n \"vreduce<ssescalarmodesuffix>\\t{%3, <round_saeonly_scalar_mask_op4>%2, %1, %0<mask_scalar_operand4>|%0<mask_scalar_operand4>, %1, %<iptr>2<round_saeonly_scalar_mask_op4>, %3}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -4937,6 +4973,7 @@ (define_insn \"*<avx512>_eq<mode>3<mask_scalar_merge_name>_1\"\n vpcmpeq<ssemodesuffix>\\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}\n vptestnm<ssemodesuffix>\\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}\"\n [(set_attr \"type\" \"ssecmp\")\n+ (set_attr \"c86_attr\" \"*,ptest\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -5026,6 +5063,7 @@ (define_insn \"*<avx512>_eq<mode>3<mask_scalar_merge_name>_1\"\n vpcmpeq<ssemodesuffix>\\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}\n vptestnm<ssemodesuffix>\\t{%1, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %1}\"\n [(set_attr \"type\" \"ssecmp\")\n+ (set_attr \"c86_attr\" \"*,ptest\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -5635,6 +5673,7 @@ (define_insn \"<sse>_andnot<mode>3<mask_name>\"\n [(set_attr \"isa\" \"noavx,avx_noavx512f,avx512dq,avx512f\")\n (set_attr \"addr\" \"*,gpr16,*,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"orig,maybe_vex,evex,evex\")\n (set (attr \"mode\")\n \t(cond [(and (match_test \"<mask_applied>\")\n@@ -5686,6 +5725,7 @@ (define_insn \"<sse>_andnot<mode>3<mask_name>\"\n return \"\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"evex\")\n (set (attr \"mode\")\n (if_then_else (match_test \"TARGET_AVX512DQ\")\n@@ -5762,6 +5802,7 @@ (define_insn \"*<code><mode>3<mask_name>\"\n }\n [(set_attr \"isa\" \"noavx,avx,avx512dq,avx512f\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"orig,maybe_evex,evex,evex\")\n (set (attr \"mode\")\n \t(cond [(and (match_test \"<mask_applied>\")\n@@ -5809,6 +5850,7 @@ (define_insn \"*<code><mode>3<mask_name>\"\n return \"\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"evex\")\n (set (attr \"mode\")\n (if_then_else (match_test \"TARGET_AVX512DQ\")\n@@ -5926,6 +5968,7 @@ (define_insn \"*andnot<mode>3\"\n }\n [(set_attr \"isa\" \"noavx,avx,avx512vl,avx512f\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"orig,vex,evex,evex\")\n (set (attr \"mode\")\n \t(cond [(eq_attr \"alternative\" \"2\")\n@@ -6056,6 +6099,7 @@ (define_insn \"<code><mode>3\"\n }\n [(set_attr \"isa\" \"noavx,avx,avx512vl,avx512f\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"orig,vex,evex,evex\")\n (set (attr \"mode\")\n \t(cond [(eq_attr \"alternative\" \"2\")\n@@ -6118,6 +6162,7 @@ (define_insn \"*<code>tf3\"\n }\n [(set_attr \"isa\" \"noavx,avx,avx512vl,avx512f\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (and (eq_attr \"alternative\" \"0\")\n@@ -8860,6 +8905,7 @@ (define_insn \"sse_cvtsi2ss<rex64namesuffix><round_name>\"\n (set_attr \"bdver1_decode\" \"double,direct,*\")\n (set_attr \"btver2_decode\" \"double,double,double\")\n (set_attr \"znver1_decode\" \"double,double,double\")\n+ (set_attr \"c86_decode\" \"double,double,double\")\n (set (attr \"length_vex\")\n \t(if_then_else\n \t (and (match_test \"<MODE>mode == DImode\")\n@@ -9321,6 +9367,7 @@ (define_insn \"sse2_cvtsi2sd\"\n (set_attr \"bdver1_decode\" \"double,direct,*\")\n (set_attr \"btver2_decode\" \"double,double,double\")\n (set_attr \"znver1_decode\" \"double,double,double\")\n+ (set_attr \"c86_decode\" \"double,double,double\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"DF\")])\n \n@@ -12250,6 +12297,10 @@ (define_insn \"vec_set<mode>_0\"\n \t (const_string \"ssemov2\")\n \t ]\n \t (const_string \"ssemov\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"9,10,11\")\n+\t\t (const_string \"insr\")\n+\t\t (const_string \"*\")))\n (set (attr \"addr\")\n (if_then_else (eq_attr \"alternative\" \"9,10\")\n \t\t (const_string \"gpr16\")\n@@ -12324,6 +12375,13 @@ (define_insn \"@vec_set<mode>_0\"\n (if_then_else (eq_attr \"alternative\" \"0,1,2,3,6,7,10\")\n \t\t (const_string \"ssemov\")\n \t\t (const_string \"sselog\")))\n+ (set (attr \"c86_attr\")\n+\t(cond [(eq_attr \"alternative\" \"6,7,10\")\n+\t\t (const_string \"blend\")\n+\t (eq_attr \"alternative\" \"4,5,8,9,11,12\")\n+\t\t (const_string \"insr\")\n+\t ]\n+\t (const_string \"*\")))\n (set (attr \"prefix_data16\")\n (if_then_else (eq_attr \"alternative\" \"4,5\")\n \t\t (const_string \"1\")\n@@ -12692,6 +12750,7 @@ (define_insn_and_split \"*sse4_1_extractps\"\n [(set_attr \"isa\" \"noavx,noavx,avx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*,*,*\")\n (set_attr \"type\" \"sselog,sselog,sselog,*,*\")\n+ (set_attr \"c86_attr\" \"extr,extr,extr,*,*\")\n (set_attr \"prefix_data16\" \"1,1,1,*,*\")\n (set_attr \"prefix_extra\" \"1,1,1,*,*\")\n (set_attr \"length_immediate\" \"1,1,1,*,*\")\n@@ -13591,6 +13650,7 @@ (define_insn \"*vec_extract<mode>\"\n [(set_attr \"isa\" \"*,sse4_noavx,avx,noavx,avx\")\n (set_attr \"addr\" \"*,gpr16,*,*,*\")\n (set_attr \"type\" \"sselog1,sselog1,sselog1,sseishft1,sseishft1\")\n+ (set_attr \"c86_attr\" \"extr,extr,extr,other,other\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -14381,6 +14441,7 @@ (define_insn \"<mask_codefor><avx512>_align<mode><mask_name>\"\n \"TARGET_AVX512F\"\n \"valign<ssemodesuffix>\\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}\";\n [(set_attr \"prefix\" \"evex\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n (define_mode_attr vec_extract_imm_predicate\n@@ -16996,6 +17057,7 @@ (define_insn \"avx512bw_pmaddwd512<mode><mask_name>\"\n \"TARGET_AVX512BW && <mask_mode512bit_condition>\"\n \"vpmaddwd\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\";\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -17067,6 +17129,7 @@ (define_insn \"*avx2_pmaddwd\"\n \"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))\"\n \"vpmaddwd\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"OI\")])\n \n@@ -17125,6 +17188,7 @@ (define_insn \"*sse2_pmaddwd\"\n vpmaddwd\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"atom_unit\" \"simul\")\n (set_attr \"prefix_data16\" \"1,*\")\n (set_attr \"prefix\" \"orig,vex\")\n@@ -17992,6 +18056,7 @@ (define_insn \"*avx2_<code><mode>3\"\n \"TARGET_AVX2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))\"\n \"vp<maxmin_int><ssemodesuffix>\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"OI\")])\n@@ -18033,6 +18098,7 @@ (define_insn \"*avx512f_<code><mode>3<mask_name>\"\n \"TARGET_AVX512F && !(MEM_P (operands[1]) && MEM_P (operands[2]))\"\n \"vp<maxmin_int><ssemodesuffix>\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -18044,6 +18110,7 @@ (define_insn \"*avx512bw_<code><mode>3<mask_name>\"\n \"TARGET_AVX512BW && !(MEM_P (operands[1]) && MEM_P (operands[2]))\"\n \"vp<maxmin_int><ssemodesuffix>\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -18142,6 +18209,7 @@ (define_insn \"*sse4_1_<code><mode>3<mask_name>\"\n vp<maxmin_int><ssemodesuffix>\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -18158,6 +18226,7 @@ (define_insn \"*<code>v8hi3\"\n vp<maxmin_int>w\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"TI\")])\n@@ -18226,6 +18295,7 @@ (define_insn \"*sse4_1_<code><mode>3<mask_name>\"\n vp<maxmin_int><ssemodesuffix>\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"prefix_extra\" \"1,1,*\")\n (set_attr \"prefix\" \"orig,orig,vex\")\n@@ -18243,6 +18313,7 @@ (define_insn \"*<code>v16qi3\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"maxmin\")\n (set_attr \"prefix\" \"orig,vex\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -18912,6 +18983,7 @@ (define_insn \"*andnot<mode>3\"\n [(set_attr \"isa\" \"noavx,avx_noavx512f,avx512f,*,*\")\n (set_attr \"addr\" \"*,gpr16,*,*,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (and (eq_attr \"alternative\" \"0\")\n@@ -19018,6 +19090,7 @@ (define_insn \"*andnot<mode>3_mask\"\n \"TARGET_AVX512F\"\n \"vpandn<ssemodesuffix>\\t{%2, %1, %0%{%4%}%N3|%0%{%4%}%N3, %1, %2}\";\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -19142,6 +19215,7 @@ (define_insn \"*<code><mode>3<mask_name>\"\n [(set_attr \"isa\" \"noavx,avx_noavx512f,avx512f\")\n (set_attr \"addr\" \"*,gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (and (eq_attr \"alternative\" \"0\")\n@@ -19239,6 +19313,7 @@ (define_insn \"*<code><mode>3\"\n [(set_attr \"isa\" \"noavx,avx_noavx512f,avx512f\")\n (set_attr \"addr\" \"*,gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (and (eq_attr \"alternative\" \"0\")\n@@ -19275,6 +19350,7 @@ (define_insn \"<code>v1ti3\"\n (set_attr \"prefix\" \"orig,vex,evex\")\n (set_attr \"prefix_data16\" \"1,*,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"sselogic\")\n (set_attr \"mode\" \"TI\")])\n \n (define_expand \"one_cmplv1ti2\"\n@@ -20250,6 +20326,7 @@ (define_insn \"<sse2p4_1>_pinsr<ssemodesuffix>\"\n }\n [(set_attr \"isa\" \"noavx,noavx,avx,avx,<pinsr_evex_isa>,<pinsr_evex_isa>,avx2\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insr\")\n (set (attr \"addr\")\n \t(if_then_else (eq_attr \"alternative\" \"0,1\")\n \t\t (const_string \"gpr16\")\n@@ -20363,6 +20440,7 @@ (define_insn \"*<extract_type>_vinsert<shuffletype><extract_suf>_0\"\n }\n }\n [(set_attr \"type\" \"sselog,ssemov,ssemov\")\n+ (set_attr \"c86_attr\" \"insertx,*,*\")\n (set_attr \"length_immediate\" \"1,0,0\")\n (set_attr \"prefix\" \"evex,vex,evex\")\n (set_attr \"mode\" \"<sseinsnmode>,<ssequarterinsnmode>,<ssequarterinsnmode>\")])\n@@ -20395,6 +20473,7 @@ (define_insn \"<mask_codefor><extract_type>_vinsert<shuffletype><extract_suf>_1<m\n return \"vinsert<shuffletype><extract_suf>\\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20433,6 +20512,7 @@ (define_insn \"vec_set_lo_<mode><mask_name>\"\n \"TARGET_AVX512DQ\"\n \"vinsert<shuffletype>32x8\\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20450,6 +20530,7 @@ (define_insn \"vec_set_hi_<mode><mask_name>\"\n \"TARGET_AVX512DQ\"\n \"vinsert<shuffletype>32x8\\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20465,6 +20546,7 @@ (define_insn \"vec_set_lo_<mode><mask_name>\"\n \"TARGET_AVX512F\"\n \"vinsert<shuffletype>64x4\\t{$0x0, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x0}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n@@ -20480,6 +20562,7 @@ (define_insn \"vec_set_hi_<mode><mask_name>\"\n \"TARGET_AVX512F\"\n \"vinsert<shuffletype>64x4\\t{$0x1, %2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2, 0x1}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n@@ -20529,6 +20612,7 @@ (define_insn \"<mask_codefor>avx512dq_shuf_<shuffletype>64x2_1<mask_name>\"\n return \"vshuf<shuffletype>64x2\\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n@@ -20592,6 +20676,7 @@ (define_insn \"avx512f_shuf_<shuffletype>64x2_1<mask_name>\"\n return \"vshuf<shuffletype>64x2\\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20628,6 +20713,7 @@ (define_insn \"*avx512f_shuf_<shuffletype>64x2_1<mask_name>_1\"\n return \"vshuf<shuffletype>64x2\\t{%2, %1, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %1, %2}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20691,6 +20777,7 @@ (define_insn \"avx512vl_shuf_<shuffletype>32x4_1<mask_name>\"\n return \"vshuf<shuffletype>32x4\\t{%3, %2, %1, %0<mask_operand11>|%0<mask_operand11>, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n@@ -20778,6 +20865,7 @@ (define_insn \"avx512f_shuf_<shuffletype>32x4_1<mask_name>\"\n return \"vshuf<shuffletype>32x4\\t{%3, %2, %1, %0<mask_operand19>|%0<mask_operand19>, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -20830,6 +20918,7 @@ (define_insn \"*avx512f_shuf_<shuffletype>32x4_1<mask_name>_1\"\n return \"vshuf<shuffletype>32x4\\t{%2, %1, %1, %0<mask_operand18>|%0<mask_operand18>, %1, %1, %2}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"shufx\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -21434,6 +21523,7 @@ (define_insn \"*vec_extract<mode>\"\n [(set_attr \"isa\" \"sse2_noavx,avx,sse4_noavx,avx\")\n (set_attr \"addr\" \"*,*,gpr16,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set (attr \"prefix_extra\")\n (if_then_else\n (eq (const_string \"<MODE>mode\") (const_string \"V8HImode\"))\n@@ -21455,6 +21545,7 @@ (define_insn \"*vec_extract<PEXTR_MODE12:mode>_zext\"\n \"%vpextr<PEXTR_MODE12:ssemodesuffix>\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set (attr \"prefix_extra\")\n (if_then_else\n (eq (const_string \"<PEXTR_MODE12:MODE>mode\") (const_string \"V8HImode\"))\n@@ -21475,6 +21566,7 @@ (define_insn \"*vec_extractv16qi_zext\"\n \"%vpextrb\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -21609,6 +21701,7 @@ (define_insn \"*vec_extractv4si\"\n }\n [(set_attr \"isa\" \"noavx,avx,avx512dq,noavx,noavx,avx\")\n (set_attr \"type\" \"sselog1,sselog1,sselog1,sseishft1,sseishft1,sseishft1\")\n+ (set_attr \"c86_attr\" \"extr,extr,*,*,*,*\")\n (set (attr \"addr\")\n \t(if_then_else (eq_attr \"alternative\" \"0\")\n \t\t (const_string \"gpr16\")\n@@ -21631,6 +21724,7 @@ (define_insn \"*vec_extractv4si_zext\"\n \"%vpextrd\\t{%2, %1, %k0|%k0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx,avx512dq\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"extr\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -21703,6 +21797,10 @@ (define_insn \"*vec_extractv2di_1\"\n \t (const_string \"imov\")\n \t ]\n \t (const_string \"sselog1\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"0,1,2\")\n+\t\t (const_string \"extr\")\n+\t\t (const_string \"other\")))\n (set (attr \"addr\")\n \t(if_then_else (eq_attr \"alternative\" \"0\")\n \t\t (const_string \"gpr16\")\n@@ -21868,6 +21966,10 @@ (define_insn \"*vec_concatv2si_sse4_1\"\n \t (const_string \"mmxmov\")\n \t ]\n \t (const_string \"sselog\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"0,1,2,3\")\n+\t\t (const_string \"insr\")\n+\t\t (const_string \"other\")))\n (set (attr \"addr\")\n (if_then_else (eq_attr \"alternative\" \"0,1\")\n \t\t (const_string \"gpr16\")\n@@ -22026,6 +22128,10 @@ (define_insn \"vec_concatv2di\"\n (eq_attr \"alternative\" \"0,1,2,3,4,5\")\n (const_string \"sselog\")\n (const_string \"ssemov2\")))\n+ (set (attr \"c86_attr\")\n+ (if_then_else (eq_attr \"alternative\" \"0,1,2,3\")\n+\t\t (const_string \"insr\")\n+\t\t (const_string \"other\")))\n (set (attr \"addr\")\n (if_then_else (eq_attr \"alternative\" \"0,1\")\n \t\t (const_string \"gpr16\")\n@@ -22245,6 +22351,7 @@ (define_insn \"*<sse2_avx2>_uavg<mode>3<mask_name>\"\n vpavg<ssemodesuffix>\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"avg\")\n (set_attr \"prefix_data16\" \"1,*\")\n (set_attr \"prefix\" \"orig,<mask_prefix>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -22273,6 +22380,7 @@ (define_insn \"*<sse2_avx2>_psadbw\"\n vpsadbw\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"sadbw\")\n (set_attr \"atom_unit\" \"simul\")\n (set_attr \"prefix_data16\" \"1,*\")\n (set_attr \"prefix\" \"orig,maybe_evex\")\n@@ -22287,6 +22395,7 @@ (define_insn \"<sse>_movmsk<ssemodesuffix><avxsizesuffix>\"\n \"%vmovmsk<ssemodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -22300,6 +22409,7 @@ (define_insn \"*<sse>_movmsk<ssemodesuffix><avxsizesuffix>_<u>ext\"\n \"%vmovmsk<ssemodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"<MODE>\")])\n \n@@ -22437,6 +22547,7 @@ (define_insn \"<sse2_avx2>_pmovmskb\"\n \"%vpmovmskb\\t{%1, %0|%0, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (match_test \"TARGET_AVX\")\n@@ -22455,6 +22566,7 @@ (define_insn \"*<sse2_avx2>_pmovmskb_zext\"\n \"%vpmovmskb\\t{%1, %k0|%k0, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (match_test \"TARGET_AVX\")\n@@ -22473,6 +22585,7 @@ (define_insn \"*sse2_pmovmskb_ext\"\n \"%vpmovmskb\\t{%1, %k0|%k0, %1}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set (attr \"prefix_data16\")\n (if_then_else\n (match_test \"TARGET_AVX\")\n@@ -22822,6 +22935,7 @@ (define_insn \"*sse2_maskmovdqu\"\n return \"%vmaskmovdqu\\t{%2, %1|%1, %2}\";\n }\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"prefix_data16\" \"1\")\n (set (attr \"length_address\")\n (symbol_ref (\"Pmode != word_mode\")))\n@@ -22830,6 +22944,7 @@ (define_insn \"*sse2_maskmovdqu\"\n (symbol_ref (\"3 + REX_SSE_REGNO_P (REGNO (operands[2]))\")))\n (set_attr \"prefix\" \"maybe_vex\")\n (set_attr \"znver1_decode\" \"vector\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"TI\")])\n \n (define_insn \"sse_ldmxcsr\"\n@@ -22922,6 +23037,7 @@ (define_insn \"avx2_ph<plusminus_mnemonic>wv16hi3\"\n \"TARGET_AVX2\"\n \"vph<plusminus_mnemonic>w\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -22948,6 +23064,7 @@ (define_insn \"ssse3_ph<plusminus_mnemonic>wv8hi3\"\n vph<plusminus_mnemonic>w\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"atom_unit\" \"complex\")\n (set_attr \"prefix_extra\" \"1\")\n@@ -22989,6 +23106,7 @@ (define_insn_and_split \"ssse3_ph<plusminus_mnemonic>wv4hi3\"\n }\n [(set_attr \"mmx_isa\" \"native,sse_noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"atom_unit\" \"complex\")\n (set_attr \"prefix_extra\" \"1\")\n (set (attr \"prefix_rex\") (symbol_ref \"x86_extended_reg_mentioned_p (insn)\"))\n@@ -23012,6 +23130,7 @@ (define_insn \"avx2_ph<plusminus_mnemonic>dv8si3\"\n \"TARGET_AVX2\"\n \"vph<plusminus_mnemonic>d\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -23036,6 +23155,7 @@ (define_insn \"ssse3_ph<plusminus_mnemonic>dv4si3\"\n vph<plusminus_mnemonic>d\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"atom_unit\" \"complex\")\n (set_attr \"prefix_data16\" \"1,*\")\n@@ -23076,6 +23196,7 @@ (define_insn_and_split \"ssse3_ph<plusminus_mnemonic>dv2si3\"\n }\n [(set_attr \"mmx_isa\" \"native,sse_noavx,avx\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"atom_unit\" \"complex\")\n (set_attr \"prefix_extra\" \"1\")\n@@ -23132,6 +23253,7 @@ (define_insn \"avx2_pmaddubsw256\"\n \"TARGET_AVX2\"\n \"vpmaddubsw\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"mode\" \"OI\")])\n@@ -23147,6 +23269,7 @@ (define_insn \"avx512bw_pmaddubsw512<mode><mask_name>\"\n \"TARGET_AVX512BW\"\n \"vpmaddubsw\\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}\";\n [(set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -23223,6 +23346,7 @@ (define_insn \"ssse3_pmaddubsw128\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"atom_unit\" \"simul\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,vex\")\n@@ -23259,6 +23383,7 @@ (define_insn \"ssse3_pmaddubsw\"\n [(set_attr \"isa\" \"*,noavx,avx\")\n (set_attr \"mmx_isa\" \"native,*,*\")\n (set_attr \"type\" \"sseiadd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"atom_unit\" \"simul\")\n (set_attr \"prefix_extra\" \"1\")\n (set (attr \"prefix_rex\") (symbol_ref \"x86_extended_reg_mentioned_p (insn)\"))\n@@ -23542,6 +23667,7 @@ (define_insn \"<ssse3_avx2>_psign<mode>3\"\n vpsign<ssemodesuffix>\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"sign\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,vex\")\n@@ -23561,6 +23687,7 @@ (define_insn \"ssse3_psign<mode>3\"\n [(set_attr \"isa\" \"*,noavx,avx\")\n (set_attr \"mmx_isa\" \"native,*,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"sign\")\n (set_attr \"prefix_extra\" \"1\")\n (set (attr \"prefix_rex\") (symbol_ref \"x86_extended_reg_mentioned_p (insn)\"))\n (set_attr \"mode\" \"DI,TI,TI\")])\n@@ -23710,6 +23837,7 @@ (define_insn \"*abs<mode>2\"\n (set_attr \"type\" \"sselog1\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n+ (set_attr \"c86_attr\" \"abs\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n (define_insn \"abs<mode>2_mask\"\n@@ -23722,6 +23850,7 @@ (define_insn \"abs<mode>2_mask\"\n \"TARGET_AVX512F\"\n \"vpabs<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"abs\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -23735,6 +23864,7 @@ (define_insn \"abs<mode>2_mask\"\n \"TARGET_AVX512BW\"\n \"vpabs<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"abs\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -23767,6 +23897,7 @@ (define_insn \"sse4a_movnt<mode>\"\n \"TARGET_SSE4A\"\n \"movnt<ssemodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"mode\" \"<MODE>\")])\n \n (define_insn \"sse4a_vmmovnt<mode>\"\n@@ -23779,6 +23910,7 @@ (define_insn \"sse4a_vmmovnt<mode>\"\n \"TARGET_SSE4A\"\n \"movnt<ssescalarmodesuffix>\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"mode\" \"<ssescalarmode>\")])\n \n (define_insn \"sse4a_extrqi\"\n@@ -23855,6 +23987,7 @@ (define_insn \"<sse4_1>_blend<ssemodesuffix><avxsizesuffix>\"\n vblend<ssemodesuffix>\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*\")\n@@ -23876,6 +24009,7 @@ (define_insn \"<sse4_1>_blendv<ssemodesuffix><avxsizesuffix>\"\n vblendv<ssemodesuffix>\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*\")\n@@ -23909,6 +24043,7 @@ (define_insn \"sse4_1_blendv<ssemodesuffix>\"\n }\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*\")\n (set_attr \"prefix_extra\" \"1\")\n@@ -24114,6 +24249,7 @@ (define_insn \"<sse4_1>_dp<ssemodesuffix><avxsizesuffix>\"\n (set_attr \"prefix\" \"orig,orig,vex\")\n (set_attr \"btver2_decode\" \"vector,vector,vector\")\n (set_attr \"znver1_decode\" \"vector,vector,vector\")\n+ (set_attr \"c86_decode\" \"vector,vector,vector\")\n (set_attr \"mode\" \"<MODE>\")])\n \n ;; Mode attribute used by `vmovntdqa' pattern\n@@ -24129,6 +24265,7 @@ (define_insn \"<vi8_sse4_1_avx2_avx512>_movntdqa\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"movnt\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -24153,6 +24290,7 @@ (define_insn \"<sse4_1_avx2>_mpsadbw\"\n (set_attr \"prefix\" \"orig,orig,vex\")\n (set_attr \"btver2_decode\" \"vector,vector,vector\")\n (set_attr \"znver1_decode\" \"vector,vector,vector\")\n+ (set_attr \"c86_decode\" \"vector,vector,vector\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n (define_insn \"avx10_2_mpsadbw<mask_name>\"\n@@ -24212,6 +24350,7 @@ (define_insn \"<sse4_1_avx2>_pblendvb\"\n vpblendvb\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blendv\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"*,*,1\")\n@@ -24353,6 +24492,7 @@ (define_insn \"sse4_1_pblend<ssemodesuffix>\"\n vpblendw\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -24425,6 +24565,7 @@ (define_insn \"*avx2_pblend<ssemodesuffix>\"\n return \"vpblendw\\t{%3, %2, %1, %0|%0, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -24440,6 +24581,7 @@ (define_insn \"avx2_pblendd<mode>\"\n \"TARGET_AVX2\"\n \"vpblendd\\t{%3, %2, %1, %0|%0, %1, %2, %3}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -24466,6 +24608,7 @@ (define_insn \"avx2_<code>v16qiv16hi2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512bw_condition> && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>bw\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -24520,6 +24663,7 @@ (define_insn \"avx512bw_<code>v32qiv32hi2<mask_name>\"\n \"TARGET_AVX512BW\"\n \"vpmov<extsuffix>bw\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -24579,6 +24723,7 @@ (define_insn \"sse4_1_<code>v8qiv8hi2<mask_name>\"\n \"%vpmov<extsuffix>bw\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -24595,6 +24740,7 @@ (define_insn \"*sse4_1_<code>v8qiv8hi2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -24741,6 +24887,7 @@ (define_insn \"<mask_codefor>avx512f_<code>v16qiv16si2<mask_name>\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>bd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -24762,6 +24909,7 @@ (define_insn \"avx2_<code>v8qiv8si2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>bd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -24773,6 +24921,7 @@ (define_insn \"*avx2_<code>v8qiv8si2<mask_name>_1\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"%vpmov<extsuffix>bd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -24850,6 +24999,7 @@ (define_insn \"sse4_1_<code>v4qiv4si2<mask_name>\"\n \"%vpmov<extsuffix>bd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -24863,6 +25013,7 @@ (define_insn \"*sse4_1_<code>v4qiv4si2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -24940,6 +25091,7 @@ (define_insn \"avx512f_<code>v16hiv16si2<mask_name>\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>wd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -24993,6 +25145,7 @@ (define_insn \"avx2_<code>v8hiv8si2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>wd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -25052,6 +25205,7 @@ (define_insn \"sse4_1_<code>v4hiv4si2<mask_name>\"\n \"%vpmov<extsuffix>wd\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25065,6 +25219,7 @@ (define_insn \"*sse4_1_<code>v4hiv4si2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25209,6 +25364,7 @@ (define_insn \"avx512f_<code>v8qiv8di2<mask_name>\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>bq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -25219,6 +25375,7 @@ (define_insn \"*avx512f_<code>v8qiv8di2<mask_name>_1\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>bq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -25292,6 +25449,7 @@ (define_insn \"avx2_<code>v4qiv4di2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>bq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -25303,6 +25461,7 @@ (define_insn \"*avx2_<code>v4qiv4di2<mask_name>_1\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>bq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -25383,6 +25542,7 @@ (define_insn \"sse4_1_<code>v2qiv2di2<mask_name>\"\n \"%vpmov<extsuffix>bq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25396,6 +25556,7 @@ (define_insn \"*sse4_1_<code>v2qiv2di2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,avx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25445,6 +25606,7 @@ (define_insn \"avx512f_<code>v8hiv8di2<mask_name>\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>wq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -25464,6 +25626,7 @@ (define_insn \"avx2_<code>v4hiv4di2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>wq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -25475,6 +25638,7 @@ (define_insn \"*avx2_<code>v4hiv4di2<mask_name>_1\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>wq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"mode\" \"OI\")])\n@@ -25547,6 +25711,7 @@ (define_insn \"sse4_1_<code>v2hiv2di2<mask_name>\"\n \"%vpmov<extsuffix>wq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25560,6 +25725,7 @@ (define_insn \"*sse4_1_<code>v2hiv2di2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25635,6 +25801,7 @@ (define_insn \"avx512f_<code>v8siv8di2<mask_name>\"\n \"TARGET_AVX512F\"\n \"vpmov<extsuffix>dq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -25686,6 +25853,7 @@ (define_insn \"avx2_<code>v4siv4di2<mask_name>\"\n \"TARGET_AVX2 && <mask_avx512vl_condition>\"\n \"vpmov<extsuffix>dq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix\" \"maybe_evex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"OI\")])\n@@ -25741,6 +25909,7 @@ (define_insn \"sse4_1_<code>v2siv2di2<mask_name>\"\n \"%vpmov<extsuffix>dq\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -25754,6 +25923,7 @@ (define_insn \"*sse4_1_<code>v2siv2di2<mask_name>_1\"\n [(set_attr \"isa\" \"noavx,noavx,avx\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"vpmovx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,orig,maybe_evex\")\n (set_attr \"mode\" \"TI\")])\n@@ -26206,6 +26376,7 @@ (define_insn \"sse4_1_round<ssescalarmodesuffix>\"\n }\n [(set_attr \"isa\" \"noavx,noavx,noavx512f,avx512f\")\n (set_attr \"type\" \"ssecvt\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,gpr16,gpr16,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*,*\")\n@@ -26243,6 +26414,7 @@ (define_insn \"*sse4_1_round<ssescalarmodesuffix>\"\n }\n [(set_attr \"isa\" \"noavx,noavx,noavx512f,avx512f\")\n (set_attr \"type\" \"ssecvt\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,gpr16,gpr16,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix_data16\" \"1,1,*,*\")\n@@ -26512,6 +26684,7 @@ (define_insn \"sse4_2_pcmpestri\"\n \"TARGET_SSE4_2\"\n \"%vpcmpestri\\t{%5, %3, %1|%1, %3, %5}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -26540,6 +26713,7 @@ (define_insn \"sse4_2_pcmpestrm\"\n \"TARGET_SSE4_2\"\n \"%vpcmpestrm\\t{%5, %3, %1|%1, %3, %5}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -26566,6 +26740,7 @@ (define_insn \"sse4_2_pcmpestr_cconly\"\n %vpcmpestri\\t{%6, %4, %2|%2, %4, %6}\n %vpcmpestri\\t{%6, %4, %2|%2, %4, %6}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -26643,6 +26818,7 @@ (define_insn \"sse4_2_pcmpistri\"\n \"TARGET_SSE4_2\"\n \"%vpcmpistri\\t{%3, %2, %1|%1, %2, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -26667,6 +26843,7 @@ (define_insn \"sse4_2_pcmpistrm\"\n \"TARGET_SSE4_2\"\n \"%vpcmpistrm\\t{%3, %2, %1|%1, %2, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -26691,6 +26868,7 @@ (define_insn \"sse4_2_pcmpistr_cconly\"\n %vpcmpistri\\t{%4, %3, %2|%2, %3, %4}\n %vpcmpistri\\t{%4, %3, %2|%2, %3, %4}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"cmpestr\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -26877,6 +27055,7 @@ (define_insn \"xop_phadd<u>bw\"\n \"TARGET_XOP\"\n \"vphadd<u>bw\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -26909,6 +27088,7 @@ (define_insn \"xop_phadd<u>bd\"\n \"TARGET_XOP\"\n \"vphadd<u>bd\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -26957,6 +27137,7 @@ (define_insn \"xop_phadd<u>bq\"\n \"TARGET_XOP\"\n \"vphadd<u>bq\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -26977,6 +27158,7 @@ (define_insn \"xop_phadd<u>wd\"\n \"TARGET_XOP\"\n \"vphadd<u>wd\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27005,6 +27187,7 @@ (define_insn \"xop_phadd<u>wq\"\n \"TARGET_XOP\"\n \"vphadd<u>wq\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27023,6 +27206,7 @@ (define_insn \"xop_phadd<u>dq\"\n \"TARGET_XOP\"\n \"vphadd<u>dq\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27047,6 +27231,7 @@ (define_insn \"xop_phsubbw\"\n \"TARGET_XOP\"\n \"vphsubbw\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27067,6 +27252,7 @@ (define_insn \"xop_phsubwd\"\n \"TARGET_XOP\"\n \"vphsubwd\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27085,6 +27271,7 @@ (define_insn \"xop_phsubdq\"\n \"TARGET_XOP\"\n \"vphsubdq\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sseiadd1\")\n+ (set_attr \"c86_attr\" \"hplus\")\n (set_attr \"prefix\" \"vex\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"mode\" \"TI\")])\n@@ -27791,6 +27978,7 @@ (define_insn \"aesenc\"\n vaesenc\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_evex,evex\")\n@@ -27809,6 +27997,7 @@ (define_insn \"aesenclast\"\n vaesenclast\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_evex,evex\")\n@@ -27827,6 +28016,7 @@ (define_insn \"aesdec\"\n vaesdec\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"isa\" \"noavx,avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_evex,evex\")\n@@ -27846,6 +28036,7 @@ (define_insn \"aesdeclast\"\n [(set_attr \"isa\" \"noavx,avx,vaes_avx512vl\")\n (set_attr \"addr\" \"gpr16,gpr16,*\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"orig,maybe_evex,evex\")\n (set_attr \"btver2_decode\" \"double,double,double\")\n@@ -27858,6 +28049,7 @@ (define_insn \"aesimc\"\n \"TARGET_AES\"\n \"%vaesimc\\t{%1, %0|%0, %1}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"maybe_vex\")\n@@ -27871,6 +28063,7 @@ (define_insn \"aeskeygenassist\"\n \"TARGET_AES\"\n \"%vaeskeygenassist\\t{%2, %1, %0|%0, %1, %2}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -27894,6 +28087,7 @@ (define_insn \"pclmulqdq\"\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"orig,vex,evex\")\n+ (set_attr \"c86_decode\" \"*,vector,vector\")\n (set_attr \"mode\" \"TI\")])\n \n (define_expand \"avx_vzeroall\"\n@@ -28011,6 +28205,7 @@ (define_insn \"<avx2_avx512>_permvar<mode><mask_name>\"\n return \"vperm<ssemodesuffix>\\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm\")\n (set_attr \"prefix\" \"<mask_prefix2>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28023,6 +28218,7 @@ (define_insn \"<avx512>_permvar<mode><mask_name>\"\n \"TARGET_AVX512VBMI && <mask_mode512bit_condition>\"\n \"vperm<ssemodesuffix>\\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm\")\n (set_attr \"prefix\" \"<mask_prefix2>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28035,6 +28231,7 @@ (define_insn \"<avx512>_permvar<mode><mask_name>\"\n \"TARGET_AVX512BW && <mask_mode512bit_condition>\"\n \"vpermw\\t{%1, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm\")\n (set_attr \"prefix\" \"<mask_prefix2>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28253,6 +28450,7 @@ (define_insn \"avx2_perm<mode>_1<mask_name>\"\n return \"vperm<ssemodesuffix>\\t{%2, %1, %0<mask_operand6>|%0<mask_operand6>, %1, %2}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm\")\n (set_attr \"prefix\" \"<mask_prefix2>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28328,6 +28526,7 @@ (define_insn \"avx512f_perm<mode>_1<mask_name>\"\n return \"vperm<ssemodesuffix>\\t{%2, %1, %0<mask_operand10>|%0<mask_operand10>, %1, %2}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm\")\n (set_attr \"prefix\" \"<mask_prefix2>\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28434,6 +28633,7 @@ (define_insn \"<mask_codefor>avx512f_broadcast<mode><mask_name>\"\n vshuf<shuffletype>32x4\\t{$0x0, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x0}\n vbroadcast<shuffletype>32x4\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"shufx,*\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28446,6 +28646,7 @@ (define_insn \"<mask_codefor>avx512f_broadcast<mode><mask_name>\"\n vshuf<shuffletype>64x2\\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}\n vbroadcast<shuffletype>64x4\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"shufx,*\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28698,6 +28899,7 @@ (define_insn \"avx_vbroadcastf128_<mode>\"\n vinsert<shuffletype>32x4\\t{$1, %1, %0, %0|%0, %0, %1, 1}\"\n [(set_attr \"isa\" \"noavx512vl,*,*,avx512dq,avx512dq,avx512vl,avx512vl\")\n (set_attr \"type\" \"ssemov,sselog1,sselog1,ssemov,sselog1,ssemov,sselog1\")\n+ (set_attr \"c86_attr\" \"*,insertx,*,*,insertx,*,insertx\")\n (set (attr \"addr\")\n \t(if_then_else (eq_attr \"alternative\" \"0\")\n \t\t (const_string \"gpr16\")\n@@ -28756,6 +28958,7 @@ (define_insn \"<mask_codefor>avx512vl_broadcast<mode><mask_name>_1\"\n vshuf<shuffletype>32x4\\t{$0x0, %t1, %t1, %0<mask_operand2>|%0<mask_operand2>, %t1, %t1, 0x0}\n vbroadcast<shuffletype>32x4\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"shufx,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -28769,6 +28972,7 @@ (define_insn \"<mask_codefor>avx512dq_broadcast<mode><mask_name>_1\"\n vshuf<shuffletype>32x4\\t{$0x44, %g1, %g1, %0<mask_operand2>|%0<mask_operand2>, %g1, %g1, 0x44}\n vbroadcast<shuffletype>32x8\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"shufx,*\")\n (set_attr \"length_immediate\" \"1,*\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -28786,6 +28990,7 @@ (define_insn \"<mask_codefor>avx512dq_broadcast<mode><mask_name>_1\"\n vshuf<shuffletype>64x2\\t{$0x0, %<xtg_mode>1, %<xtg_mode>1, %0<mask_operand2>|%0<mask_operand2>, %<xtg_mode>1, %<xtg_mode>1, 0x0}\n vbroadcast<shuffletype>64x2\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"shufx,*\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -28883,6 +29088,7 @@ (define_insn \"*<avx512>_vpermi2var<mode>3_mask\"\n \"TARGET_AVX512F\"\n \"vpermi2<ssemodesuffix>\\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm2\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28899,6 +29105,7 @@ (define_insn \"*<avx512>_vpermi2var<mode>3_mask\"\n \"TARGET_AVX512F\"\n \"vpermi2<ssemodesuffix>\\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm2\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28928,6 +29135,7 @@ (define_insn \"<avx512>_vpermt2var<mode>3<sd_maskz_name>\"\n vpermt2<ssemodesuffix>\\t{%3, %1, %0<sd_mask_op4>|%0<sd_mask_op4>, %1, %3}\n vpermi2<ssemodesuffix>\\t{%3, %2, %0<sd_mask_op4>|%0<sd_mask_op4>, %2, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm2\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -28959,6 +29167,7 @@ (define_insn \"<avx512>_vpermt2var<mode>3_mask\"\n \"TARGET_AVX512F\"\n \"vpermt2<ssemodesuffix>\\t{%3, %1, %0%{%4%}|%0%{%4%}, %1, %3}\"\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"perm2\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -29037,6 +29246,7 @@ (define_insn \"*avx_vperm2f128<mode>_nozero\"\n return \"vperm2<i128>\\t{%3, %2, %1, %0|%0, %1, %2, %3}\";\n }\n [(set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -29144,6 +29354,7 @@ (define_insn \"vec_set_lo_<mode><mask_name>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29168,6 +29379,7 @@ (define_insn \"vec_set_hi_<mode><mask_name>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29191,6 +29403,7 @@ (define_insn \"vec_set_lo_<mode><mask_name>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29214,6 +29427,7 @@ (define_insn \"vec_set_hi_<mode><mask_name>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29236,6 +29450,7 @@ (define_insn \"vec_set_lo_<mode>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex,evex\")\n@@ -29258,6 +29473,7 @@ (define_insn \"vec_set_hi_<mode>\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex,evex\")\n@@ -29283,6 +29499,7 @@ (define_insn \"vec_set_lo_v32qi\"\n vinserti32x4\\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n@@ -29310,6 +29527,7 @@ (define_insn \"vec_set_hi_v32qi\"\n [(set_attr \"isa\" \"noavx512vl,avx512vl\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"type\" \"sselog\")\n+ (set_attr \"c86_attr\" \"insertx\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"vex,evex\")\n@@ -29329,6 +29547,7 @@ (define_insn \"<avx_avx2>_maskload<ssemodesuffix><avxsizesuffix>\"\n return \"vmaskmov<ssefltmodesuffix>\\t{%1, %2, %0|%0, %2, %1}\";\n }\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29350,6 +29569,7 @@ (define_insn \"<avx_avx2>_maskstore<ssemodesuffix><avxsizesuffix>\"\n return \"vmaskmov<ssefltmodesuffix>\\t{%2, %1, %0|%0, %1, %2}\";\n }\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"blend\")\n (set_attr \"addr\" \"gpr16\")\n (set_attr \"prefix_extra\" \"1\")\n (set_attr \"prefix\" \"vex\")\n@@ -29745,6 +29965,7 @@ (define_insn \"avx_vec_concat<mode>\"\n [(set_attr \"isa\" \"noavx512f,avx512f,*,*\")\n (set_attr \"addr\" \"gpr16,*,*,*\")\n (set_attr \"type\" \"sselog,sselog,ssemov,ssemov\")\n+ (set_attr \"c86_attr\" \"insertx,insertx,*,*\")\n (set_attr \"prefix_extra\" \"1,1,*,*\")\n (set_attr \"length_immediate\" \"1,1,*,*\")\n (set_attr \"prefix\" \"maybe_evex\")\n@@ -30355,6 +30576,7 @@ (define_insn \"<avx512>_compress<mode>_mask\"\n \"TARGET_AVX512F\"\n \"v<sseintprefix>compress<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"compress\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -30368,6 +30590,7 @@ (define_insn \"compress<mode>_mask\"\n \"TARGET_AVX512VBMI2\"\n \"vpcompress<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"compress\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -30381,6 +30604,7 @@ (define_insn \"<avx512>_compressstore<mode>_mask\"\n \"TARGET_AVX512F\"\n \"v<sseintprefix>compress<ssemodesuffix>\\t{%1, %0%{%2%}|%0%{%2%}, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"compress\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"memory\" \"store\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30395,6 +30619,7 @@ (define_insn \"compressstore<mode>_mask\"\n \"TARGET_AVX512VBMI2\"\n \"vpcompress<ssemodesuffix>\\t{%1, %0%{%2%}|%0%{%2%}, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"compress\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"memory\" \"store\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30419,6 +30644,7 @@ (define_insn \"expand<mode>_mask\"\n \"TARGET_AVX512F\"\n \"v<sseintprefix>expand<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"expand\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"memory\" \"none,load\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30433,6 +30659,7 @@ (define_insn \"expand<mode>_mask\"\n \"TARGET_AVX512VBMI2\"\n \"v<sseintprefix>expand<ssemodesuffix>\\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}\"\n [(set_attr \"type\" \"ssemov\")\n+ (set_attr \"c86_attr\" \"expand\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"memory\" \"none,load\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30625,6 +30852,7 @@ (define_insn \"<mask_codefor>avx512bw_dbpsadbw<mode><mask_name>\"\n \"TARGET_AVX512BW\"\n \"vdbpsadbw\\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3}\"\n [(set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"sadbw\")\n (set_attr \"length_immediate\" \"1\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30636,6 +30864,7 @@ (define_insn \"clz<mode>2<mask_name>\"\n \"TARGET_AVX512CD\"\n \"vplzcnt<ssemodesuffix>\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"sse\")\n+ (set_attr \"c86_attr\" \"abs\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -30648,6 +30877,7 @@ (define_insn \"<mask_codefor>conflict<mode><mask_name>\"\n \"vpconflict<ssemodesuffix>\\t{%1, %0<mask_operand2>|%0<mask_operand2>, %1}\"\n [(set_attr \"type\" \"sse\")\n (set_attr \"prefix\" \"evex\")\n+ (set_attr \"c86_decode\" \"vector\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n (define_insn \"sha1msg1\"\n@@ -30910,6 +31140,7 @@ (define_insn \"vpmadd52<vpmadd52type>v8di\"\n \"TARGET_AVX512IFMA\"\n \"vpmadd52<vpmadd52type>\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr \"type\" \"ssemuladd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"XI\")])\n \n@@ -30926,6 +31157,7 @@ (define_insn \"vpmadd52<vpmadd52type><mode>\"\n vpmadd52<vpmadd52type>\\t{%3, %2, %0|%0, %2, %3}\"\n [(set_attr \"isa\" \"avxifma,avx512ifmavl\")\n (set_attr \"type\" \"ssemuladd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"prefix\" \"vex,evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n@@ -30943,6 +31175,7 @@ (define_insn \"vpmadd52<vpmadd52type><mode>_maskz_1\"\n \"TARGET_AVX512IFMA\"\n \"vpmadd52<vpmadd52type>\\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3}\"\n [(set_attr \"type\" \"ssemuladd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -30959,6 +31192,7 @@ (define_insn \"vpmadd52<vpmadd52type><mode>_mask\"\n \"TARGET_AVX512IFMA\"\n \"vpmadd52<vpmadd52type>\\t{%3, %2, %0%{%4%}|%0%{%4%}, %2, %3}\"\n [(set_attr \"type\" \"ssemuladd\")\n+ (set_attr \"c86_attr\" \"madd\")\n (set_attr \"prefix\" \"evex\")\n (set_attr \"mode\" \"<sseinsnmode>\")])\n \n@@ -31562,6 +31796,7 @@ (define_insn \"vaesdec_<mode>\"\n }\n [(set_attr \"isa\" \"avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -31580,6 +31815,7 @@ (define_insn \"vaesdeclast_<mode>\"\n }\n [(set_attr \"isa\" \"avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -31598,6 +31834,7 @@ (define_insn \"vaesenc_<mode>\"\n }\n [(set_attr \"isa\" \"avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"mode\" \"TI\")])\n \n@@ -31616,6 +31853,7 @@ (define_insn \"vaesenclast_<mode>\"\n }\n [(set_attr \"isa\" \"avx,vaes_avx512vl\")\n (set_attr \"type\" \"sselog1\")\n+ (set_attr \"c86_attr\" \"aes\")\n (set_attr \"addr\" \"gpr16,*\")\n (set_attr \"mode\" \"TI\")])\n \ndiff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h\nindex 99d97ab03..7819fdf7c 100644\n--- a/gcc/config/i386/x86-tune-costs.h\n+++ b/gcc/config/i386/x86-tune-costs.h\n@@ -4420,3 +4420,303 @@ struct processor_costs core_cost = {\n COSTS_N_INSNS (2),\t\t\t/* Branch mispredict scale. */\n };\n \n+/* C86_4G_M4 has optimized REP instruction for medium sized blocks, but for\n+ very small blocks it is better to use loop. For large blocks, libcall\n+ can do nontemporary accesses and beat inline considerably. */\n+static stringop_algs c86_4g_m4_memcpy[2] = {\n+ /* 32-bit tuning. */\n+ {libcall, {{6, loop, false},\n+\t {14, unrolled_loop, false},\n+\t {-1, libcall, false}}},\n+ /* 64-bit tuning. */\n+ {libcall, {{16, loop, false},\n+\t {128, rep_prefix_8_byte, false},\n+\t {-1, libcall, false}}}};\n+static stringop_algs c86_4g_m4_memset[2] = {\n+ /* 32-bit tuning. */\n+ {libcall, {{8, loop, false},\n+\t {24, unrolled_loop, false},\n+\t {128, rep_prefix_4_byte, false},\n+\t {-1, libcall, false}}},\n+ /* 64-bit tuning. */\n+ {libcall, {{48, unrolled_loop, false},\n+\t {128, rep_prefix_8_byte, false},\n+\t {-1, libcall, false}}}};\n+static const\n+struct processor_costs c86_4g_m4_cost = {\n+ {\n+ /* Start of register allocator costs. integer->integer move cost is 2. */\n+\n+ /* reg-reg moves are done by renaming and thus they are even cheaper than\n+ 1 cycle. Because reg-reg move cost is 2 and the following tables\n+ correspond to doubles of latencies, we do not model this correctly.\n+ It does not seem to make practical difference to bump prices up even\n+ more. */\n+ 6,\t\t\t\t\t/* cost for loading QImode using\n+\t\t\t\t\t movzbl. */\n+ {6, 6, 6},\t\t\t\t/* cost of loading integer registers\n+\t\t\t\t\t in QImode, HImode and SImode.\n+\t\t\t\t\t Relative to reg-reg move (2). */\n+ {8, 8, 8},\t\t\t\t/* cost of storing integer\n+\t\t\t\t\t registers. */\n+ 2,\t\t\t\t\t/* cost of reg,reg fld/fst. */\n+ {6, 6, 16},\t\t\t\t/* cost of loading fp registers\n+\t\t\t\t\t in SFmode, DFmode and XFmode. */\n+ {8, 8, 16},\t\t\t\t/* cost of storing fp registers\n+\t\t\t\t\t in SFmode, DFmode and XFmode. */\n+ 2,\t\t\t\t\t/* cost of moving MMX register. */\n+ {6, 6},\t\t\t\t/* cost of loading MMX registers\n+\t\t\t\t\t in SImode and DImode. */\n+ {8, 8},\t\t\t\t/* cost of storing MMX registers\n+\t\t\t\t\t in SImode and DImode. */\n+ 2, 3, 6,\t\t\t\t/* cost of moving XMM,YMM,ZMM register. */\n+ {6, 6, 6, 12, 24},\t\t\t/* cost of loading SSE registers\n+\t\t\t\t\t in 32,64,128,256 and 512-bit. */\n+ {8, 8, 8, 16, 32},\t\t\t/* cost of storing SSE registers\n+\t\t\t\t\t in 32,64,128,256 and 512-bit. */\n+ 6, 6,\t\t\t\t/* SSE->integer and integer->SSE moves. */\n+ 8, 8,\t\t\t\t/* mask->integer and integer->mask moves */\n+ {6, 6, 6},\t\t\t\t/* cost of loading mask register\n+\t\t\t\t\t in QImode, HImode, SImode. */\n+ {8, 8, 8},\t\t\t\t/* cost if storing mask register\n+\t\t\t\t\t in QImode, HImode, SImode. */\n+ 2,\t\t\t\t\t/* cost of moving mask register. */\n+ /* End of register allocator costs. */\n+ },\n+\n+ COSTS_N_INSNS (1),\t\t\t/* cost of an add instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of a lea instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* variable shift costs. */\n+ COSTS_N_INSNS (1),\t\t\t/* constant shift costs. */\n+ {COSTS_N_INSNS (3),\t\t\t/* cost of starting multiply for QI. */\n+ COSTS_N_INSNS (3),\t\t\t/*\t\t\t\t HI. */\n+ COSTS_N_INSNS (3),\t\t\t/*\t\t\t\t SI. */\n+ COSTS_N_INSNS (3),\t\t\t/*\t\t\t\t DI. */\n+ COSTS_N_INSNS (3)},\t\t\t/*\t\t\t other. */\n+ 0,\t\t\t\t\t/* cost of multiply per each bit\n+\t\t\t\t\t set. */\n+ /* Depending on parameters, idiv can get faster on HYGON. This is upper\n+ bound. */\n+ {COSTS_N_INSNS (16),\t\t\t/* cost of a divide/mod for QI. */\n+ COSTS_N_INSNS (22),\t\t\t/*\t\t\t HI. */\n+ COSTS_N_INSNS (30),\t\t\t/*\t\t\t SI. */\n+ COSTS_N_INSNS (45),\t\t\t/*\t\t\t DI. */\n+ COSTS_N_INSNS (45)},\t\t\t/*\t\t\t other. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of movsx. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of movzx. */\n+ 8,\t\t\t\t\t/* \"large\" insn. */\n+ 9,\t\t\t\t\t/* MOVE_RATIO. */\n+ 6,\t\t\t\t\t/* CLEAR_RATIO */\n+ {6, 6, 6},\t\t\t\t/* cost of loading integer registers\n+\t\t\t\t\t in QImode, HImode and SImode.\n+\t\t\t\t\t Relative to reg-reg move (2). */\n+ {8, 8, 8},\t\t\t\t/* cost of storing integer\n+\t\t\t\t\t registers. */\n+ {6, 6, 6, 12, 24},\t\t\t/* cost of loading SSE register\n+\t\t\t\t\t in 32bit, 64bit, 128bit, 256bit and 512bit */\n+ {8, 8, 8, 16, 32},\t\t\t/* cost of storing SSE register\n+\t\t\t\t\t in 32bit, 64bit, 128bit, 256bit and 512bit */\n+ {6, 6, 6, 12, 24},\t\t\t/* cost of unaligned loads. */\n+ {8, 8, 8, 16, 32},\t\t\t/* cost of unaligned stores. */\n+ 2, 3, 6,\t\t\t\t/* cost of moving XMM,YMM,ZMM register. */\n+ 6,\t\t\t\t\t/* cost of moving SSE register to integer. */\n+ 6,\t\t\t\t\t/* cost of moving integer register to SSE. */\n+\n+ 18, 8,\t\t\t\t/* Gather load static, per_elt. */\n+ 18, 10,\t\t\t\t/* Gather store static, per_elt. */\n+ 32,\t\t\t\t\t/* size of l1 cache. */\n+ 512,\t\t\t\t\t/* size of l2 cache. */\n+ 64,\t\t\t\t\t/* size of prefetch block. */\n+ /* C86_4G_M4 processors never drop prefetches; if they cannot be performed\n+ immediately, they are queued. We set number of simultaneous prefetches\n+ to a large constant to reflect this (it probably is not a good idea not\n+ to limit number of prefetches at all, as their execution also takes some\n+ time). */\n+ 100,\t\t\t\t\t/* number of parallel prefetches. */\n+ 3,\t\t\t\t\t/* Branch cost. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FADD and FSUB insns. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FMUL instruction. */\n+\n+ COSTS_N_INSNS (15),\t\t\t/* cost of FDIV instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of FABS instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of FCHS instruction. */\n+\n+ COSTS_N_INSNS (10),\t\t\t/* cost of FSQRT instruction. */\n+\n+ COSTS_N_INSNS (1),\t\t\t/* cost of cheap SSE instruction. */\n+ COSTS_N_INSNS (3),\t\t\t/* cost of ADDSS/SD SUBSS/SD insns. */\n+ COSTS_N_INSNS (3),\t\t\t/* cost of MULSS instruction. */\n+ COSTS_N_INSNS (4),\t\t\t/* cost of MULSD instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FMA SS instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FMA SD instruction. */\n+ COSTS_N_INSNS (10),\t\t\t/* cost of DIVSS instruction. */\n+\n+ COSTS_N_INSNS (13),\t\t\t/* cost of DIVSD instruction. */\n+ COSTS_N_INSNS (10),\t\t\t/* cost of SQRTSS instruction. */\n+ COSTS_N_INSNS (15),\t\t\t/* cost of SQRTSD instruction. */\n+\n+ COSTS_N_INSNS (4),\t\t\t/* cost of CVTSS2SD etc. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of 256bit VCVTPS2PD etc. */\n+ COSTS_N_INSNS (10),\t\t\t/* cost of 512bit VCVTPS2PD etc. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVTSI2SS instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVT(T)SS2SI instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVTPI2PS instruction. */\n+ COSTS_N_INSNS (4),\t\t\t/* cost of CVT(T)PS2PI instruction. */\n+\n+ 4, 4, 3, 6,\t\t\t\t/* reassoc int, fp, vec_int, vec_fp. */\n+ {8, 1, 6},\t\t\t\t/* latency times throughput of\n+\t\t\t\t\t FMA/DOT_PROD_EXPR/SAD_EXPR,\n+\t\t\t\t\t it's used to determine unroll\n+\t\t\t\t\t factor in the vectorizer. */\n+ 4,\t\t\t\t\t/* Limit how much the autovectorizer\n+\t\t\t\t\t may unroll a loop. */\n+ c86_4g_m4_memcpy,\n+ c86_4g_m4_memset,\n+ COSTS_N_INSNS (4),\t\t\t/* cond_taken_branch_cost. */\n+ COSTS_N_INSNS (2),\t\t\t/* cond_not_taken_branch_cost. */\n+ \"16\",\t\t\t\t\t/* Loop alignment. */\n+ \"16\",\t\t\t\t\t/* Jump alignment. */\n+ \"0:0:8\",\t\t\t\t/* Label alignment. */\n+ \"16\",\t\t\t\t\t/* Func alignment. */\n+ 4,\t\t\t\t\t/* Small unroll limit. */\n+ 2,\t\t\t\t\t/* Small unroll factor. */\n+ COSTS_N_INSNS (2),\t\t\t/* Branch mispredict scale. */\n+};\n+\n+struct processor_costs c86_4g_m6_cost = c86_4g_m4_cost;\n+\n+struct processor_costs c86_4g_m7_cost = {\n+ {\n+ /* Start of register allocator costs. integer->integer move cost is 2. */\n+\n+ /* reg-reg moves are done by renaming and thus they are even cheaper than\n+ 1 cycle. Because reg-reg move cost is 2 and following tables correspond\n+ to doubles of latencies, we do not model this correctly. It does not\n+ seem to make practical difference to bump prices up even more. */\n+ 6,\t\t\t\t\t/* cost for loading QImode using\n+\t\t\t\t\t movzbl. */\n+ {6, 6, 6},\t\t\t\t/* cost of loading integer registers\n+\t\t\t\t\t in QImode, HImode and SImode.\n+\t\t\t\t\t Relative to reg-reg move (2). */\n+ {8, 8, 8},\t\t\t\t/* cost of storing integer\n+\t\t\t\t\t registers. */\n+ 2,\t\t\t\t\t/* cost of reg,reg fld/fst. */\n+ {14, 14, 17},\t\t\t\t/* cost of loading fp registers\n+\t\t\t\t\t in SFmode, DFmode and XFmode. */\n+ {12, 12, 16},\t\t\t\t/* cost of storing fp registers\n+\t\t\t\t\t in SFmode, DFmode and XFmode. */\n+ 2,\t\t\t\t\t/* cost of moving MMX register. */\n+ {6, 6},\t\t\t\t/* cost of loading MMX registers\n+\t\t\t\t\t in SImode and DImode. */\n+ {8, 8},\t\t\t\t/* cost of storing MMX registers\n+\t\t\t\t\t in SImode and DImode. */\n+ 2, 2, 3,\t\t\t\t/* cost of moving XMM,YMM,ZMM\n+\t\t\t\t\t register. */\n+ {6, 6, 10, 10, 12},\t\t\t/* cost of loading SSE registers\n+\t\t\t\t\t in 32,64,128,256 and 512-bit. */\n+ {8, 8, 8, 12, 12},\t\t\t/* cost of storing SSE registers\n+\t\t\t\t\t in 32,64,128,256 and 512-bit. */\n+ 6, 8,\t\t\t\t\t/* SSE->integer and integer->SSE\n+\t\t\t\t\t moves. */\n+ 8, 8,\t\t\t\t\t/* mask->integer and integer->mask moves */\n+ {6, 6, 6},\t\t\t\t/* cost of loading mask register\n+\t\t\t\t\t in QImode, HImode, SImode. */\n+ {8, 8, 8},\t\t\t\t/* cost if storing mask register\n+\t\t\t\t\t in QImode, HImode, SImode. */\n+ 2,\t\t\t\t\t/* cost of moving mask register. */\n+ /* End of register allocator costs. */\n+ },\n+\n+ COSTS_N_INSNS (1),\t\t\t/* cost of an add instruction. */\n+\n+ COSTS_N_INSNS (1),\t\t\t/* cost of a lea instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* variable shift costs. */\n+ COSTS_N_INSNS (1),\t\t\t/* constant shift costs. */\n+ {COSTS_N_INSNS (3),\t\t\t/* cost of starting multiply for QI. */\n+ COSTS_N_INSNS (3),\t\t\t/* \t\t\t\t HI. */\n+ COSTS_N_INSNS (3),\t\t\t/*\t\t\t\t SI. */\n+ COSTS_N_INSNS (3),\t\t\t/*\t\t\t\t DI. */\n+ COSTS_N_INSNS (3)},\t\t\t/*\t\t\tother. */\n+ 0,\t\t\t\t\t/* cost of multiply per each bit\n+\t\t\t\t\t set. */\n+ {COSTS_N_INSNS (15),\t\t\t/* cost of a divide/mod for QI. */\n+ COSTS_N_INSNS (17),\t\t\t/* \t\t\t HI. */\n+ COSTS_N_INSNS (25),\t\t\t/*\t\t\t SI. */\n+ COSTS_N_INSNS (41),\t\t\t/*\t\t\t DI. */\n+ COSTS_N_INSNS (41)},\t\t\t/*\t\t\t other. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of movsx. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of movzx. */\n+ 8,\t\t\t\t\t/* \"large\" insn. */\n+ 9,\t\t\t\t\t/* MOVE_RATIO. */\n+ 6,\t\t\t\t\t/* CLEAR_RATIO */\n+ {6, 6, 6},\t\t\t\t/* cost of loading integer registers\n+\t\t\t\t\t in QImode, HImode and SImode.\n+\t\t\t\t\t Relative to reg-reg move (2). */\n+ {8, 8, 8},\t\t\t\t/* cost of storing integer\n+\t\t\t\t\t registers. */\n+ {6, 6, 10, 10, 12},\t\t\t/* cost of loading SSE registers\n+\t\t\t\t\t in 32bit, 64bit, 128bit, 256bit and 512bit */\n+ {8, 8, 8, 12, 12},\t\t\t/* cost of storing SSE register\n+\t\t\t\t\t in 32bit, 64bit, 128bit, 256bit and 512bit */\n+ {6, 6, 10, 10, 12},\t\t\t/* cost of unaligned loads. */\n+ {8, 8, 8, 12, 12},\t\t\t/* cost of unaligned stores. */\n+ 2, 2, 3,\t\t\t\t/* cost of moving XMM,YMM,ZMM\n+\t\t\t\t\t register. */\n+ 6,\t\t\t\t\t/* cost of moving SSE register to integer. */\n+ 6,\t\t\t\t\t/* cost of moving integer register to SSE. */\n+\n+ 14, 10,\t\t\t\t/* Gather load static, per_elt. */\n+ 14, 20,\t\t\t\t/* Gather store static, per_elt. */\n+ 32,\t\t\t\t\t/* size of l1 cache. */\n+ 512,\t\t\t\t\t/* size of l2 cache. */\n+ 64,\t\t\t\t\t/* size of prefetch block. */\n+\n+ 100,\t\t\t\t\t/* number of parallel prefetches. */\n+ 3,\t\t\t\t\t/* Branch cost. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FADD and FSUB insns. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of FMUL instruction. */\n+\n+ COSTS_N_INSNS (15),\t\t\t/* cost of FDIV instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of FABS instruction. */\n+ COSTS_N_INSNS (1),\t\t\t/* cost of FCHS instruction. */\n+\n+ COSTS_N_INSNS (22),\t\t\t/* cost of FSQRT instruction. */\n+\n+ COSTS_N_INSNS (1),\t\t\t/* cost of cheap SSE instruction. */\n+ COSTS_N_INSNS (3),\t\t\t/* cost of ADDSS/SD SUBSS/SD insns. */\n+ COSTS_N_INSNS (3),\t\t\t/* cost of MULSS instruction. */\n+ COSTS_N_INSNS (3),\t\t\t/* cost of MULSD instruction. */\n+ COSTS_N_INSNS (4),\t\t\t/* cost of FMA SS instruction. */\n+ COSTS_N_INSNS (4),\t\t\t/* cost of FMA SD instruction. */\n+ COSTS_N_INSNS (13),\t\t\t/* cost of DIVSS instruction. */\n+\n+ COSTS_N_INSNS (10),\t\t\t/* cost of DIVSD instruction. */\n+ COSTS_N_INSNS (14),\t\t\t/* cost of SQRTSS instruction. */\n+ COSTS_N_INSNS (20),\t\t\t/* cost of SQRTSD instruction. */\n+\n+ COSTS_N_INSNS (4),\t\t\t/* cost of CVTSS2SD etc. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of 256bit VCVTPS2PD etc. */\n+ COSTS_N_INSNS (10),\t\t\t/* cost of 512bit VCVTPS2PD etc. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVTSI2SS instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVT(T)SS2SI instruction. */\n+ COSTS_N_INSNS (5),\t\t\t/* cost of CVTPI2PS instruction. */\n+ COSTS_N_INSNS (4),\t\t\t/* cost of CVT(T)PS2PI instruction. */\n+ 4, 4, 3, 6,\t\t\t\t/* reassoc int, fp, vec_int, vec_fp. */\n+ {8, 8, 6},\t\t\t\t/* latency times throughput of\n+\t\t\t\t\t FMA/DOT_PROD_EXPR/SAD_EXPR,\n+\t\t\t\t\t it's used to determine unroll\n+\t\t\t\t\t factor in the vectorizer. */\n+ 4,\t\t\t\t\t/* Limit how much the autovectorizer\n+\t\t\t\t\t may unroll a loop. */\n+ c86_4g_m4_memcpy,\n+ c86_4g_m4_memset,\n+ COSTS_N_INSNS (4),\t\t\t/* cond_taken_branch_cost. */\n+ COSTS_N_INSNS (2),\t\t\t/* cond_not_taken_branch_cost. */\n+ \"16\",\t\t\t\t\t/* Loop alignment. */\n+ \"16\",\t\t\t\t\t/* Jump alignment. */\n+ \"0:0:8\",\t\t\t\t/* Label alignment. */\n+ \"16\",\t\t\t\t\t/* Func alignment. */\n+ 4,\t\t\t\t\t/* Small unroll limit. */\n+ 2,\t\t\t\t\t/* Small unroll factor. */\n+ COSTS_N_INSNS (2),\t\t\t/* Branch mispredict scale. */\n+};\ndiff --git a/gcc/config/i386/x86-tune-sched.cc b/gcc/config/i386/x86-tune-sched.cc\nindex e22676577..4fc955a12 100644\n--- a/gcc/config/i386/x86-tune-sched.cc\n+++ b/gcc/config/i386/x86-tune-sched.cc\n@@ -91,6 +91,9 @@ ix86_issue_rate (void)\n is limits of the decoders. */\n case PROCESSOR_ZNVER5:\n case PROCESSOR_ZNVER6:\n+ case PROCESSOR_C86_4G_M4:\n+ case PROCESSOR_C86_4G_M6:\n+ case PROCESSOR_C86_4G_M7:\n return 4;\n \n case PROCESSOR_ICELAKE_CLIENT:\n@@ -440,6 +443,9 @@ ix86_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, int cost,\n case PROCESSOR_ZNVER4:\n case PROCESSOR_ZNVER5:\n case PROCESSOR_ZNVER6:\n+ case PROCESSOR_C86_4G_M4:\n+ case PROCESSOR_C86_4G_M6:\n+ case PROCESSOR_C86_4G_M7:\n /* Stack engine allows to execute push&pop instructions in parall. */\n if ((insn_type == TYPE_PUSH || insn_type == TYPE_POP)\n \t && (dep_insn_type == TYPE_PUSH || dep_insn_type == TYPE_POP))\ndiff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def\nindex 53cf1a194..abc5ee47f 100644\n--- a/gcc/config/i386/x86-tune.def\n+++ b/gcc/config/i386/x86-tune.def\n@@ -42,7 +42,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see\n DEF_TUNE (X86_TUNE_SCHEDULE, \"schedule\",\n m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT\n \t | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT\n-\t | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM\n+\t | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G\n \t | m_GENERIC)\n \n /* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming\n@@ -53,7 +53,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, \"partial_reg_dependency\",\n m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2\n \t | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL\n \t | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID\n-\t | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store\n destinations to be 128bit to allow register renaming on 128bit SSE units,\n@@ -64,7 +64,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, \"partial_reg_dependency\",\n DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, \"sse_partial_reg_dependency\",\n m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10\n \t | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID\n-\t | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids\n partial write to the destination in scalar SSE conversion from FP\n@@ -73,7 +73,7 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,\n \t \"sse_partial_reg_fp_converts_dependency\",\n \t m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10\n \t | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM\n-\t | m_GENERIC)\n+\t | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial\n write to the destination in scalar SSE conversion from integer to FP. */\n@@ -81,7 +81,7 @@ DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,\n \t \"sse_partial_reg_converts_dependency\",\n \t m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10\n \t | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM\n-\t | m_GENERIC)\n+\t | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before\n several insns to break false dependency on the dest register for GLC\n@@ -113,32 +113,33 @@ DEF_TUNE (X86_TUNE_MOVX, \"movx\",\n m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE\n \t | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL\n \t | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN\n-\t | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM\n+\t | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by\n full sized loads. */\n DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, \"memory_mismatch_stall\",\n m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL\n \t | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN\n-\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent\n conditional jump instruction for 32 bit TARGET. */\n DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, \"fuse_cmp_and_branch_32\",\n-\t m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)\n+\t m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent\n conditional jump instruction for TARGET_64BIT. */\n DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, \"fuse_cmp_and_branch_64\",\n \t m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER\n-\t | m_ZNVER | m_ZHAOXIN | m_GENERIC)\n+\t | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a\n subsequent conditional jump instruction when the condition jump\n check sign flag (SF) or overflow flag (OF). */\n DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, \"fuse_cmp_and_branch_soflags\",\n \t m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER\n-\t | m_ZNVER | m_ZHAOXIN | m_GENERIC)\n+\t | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional\n jump instruction when the alu instruction produces the CCFLAG consumed by\n@@ -201,14 +202,15 @@ DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, \"epilogue_using_move\",\n /* X86_TUNE_USE_LEAVE: Use \"leave\" instruction in epilogues where it fits. */\n DEF_TUNE (X86_TUNE_USE_LEAVE, \"use_leave\",\n \t m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN\n-\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_PUSH_MEMORY: Enable generation of \"push mem\" instructions.\n Some chips, like 486 and Pentium works faster with separate load\n and push instructions. */\n DEF_TUNE (X86_TUNE_PUSH_MEMORY, \"push_memory\",\n m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE\n-\t | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G\n+\t | m_GENERIC)\n \n /* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred\n over esp subtraction. */\n@@ -292,7 +294,7 @@ DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, \"integer_dfmode_moves\",\n ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT\n \t | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT\n \t | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM\n-\t | m_GENERIC))\n+\t | m_C86_4G | m_GENERIC))\n \n /* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag\n will impact LEA instruction selection. */\n@@ -339,14 +341,14 @@ DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,\n DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,\n \t \"misaligned_move_string_pro_epilogues\",\n \t m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT\n-\t | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_USE_SAHF: Controls use of SAHF. */\n DEF_TUNE (X86_TUNE_USE_SAHF, \"use_sahf\",\n \t m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT\n \t | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER\n \t | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT\n-\t | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */\n DEF_TUNE (X86_TUNE_USE_CLTD, \"use_cltd\",\n@@ -357,7 +359,7 @@ DEF_TUNE (X86_TUNE_USE_CLTD, \"use_cltd\",\n DEF_TUNE (X86_TUNE_USE_BT, \"use_bt\",\n \t m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT\n \t | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS\n-\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency\n for bit-manipulation instructions. */\n@@ -391,7 +393,7 @@ DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, \"one_if_conv_insn\",\n /* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */\n DEF_TUNE (X86_TUNE_AVOID_MFENCE, \"avoid_mfence\",\n \t m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID\n-\t | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by\n generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -\n@@ -415,10 +417,11 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, \"use_simode_fiop\",\n ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL\n \t | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT\n \t | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM\n-\t | m_GENERIC))\n+\t | m_C86_4G | m_GENERIC))\n \n /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */\n-DEF_TUNE (X86_TUNE_USE_FFREEP, \"use_ffreep\", m_AMD_MULTIPLE | m_ZHAOXIN)\n+DEF_TUNE (X86_TUNE_USE_FFREEP, \"use_ffreep\", m_AMD_MULTIPLE | m_ZHAOXIN\n+\t | m_C86_4G)\n \n /* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */\n DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, \"ext_80387_constants\",\n@@ -442,30 +445,31 @@ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, \"sse_unaligned_load_optimal\",\n \t m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL\n \t | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID\n \t | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN\n-\t | m_GENERIC)\n+\t | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores\n instead of a sequence loading registers by parts. */\n DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, \"sse_unaligned_store_optimal\",\n \t m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT\n \t | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID\n-\t | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)\n+\t | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single\n precision 128bit instructions instead of double where possible. */\n DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, \"sse_packed_single_insn_optimal\",\n-\t m_BDVER | m_ZNVER)\n+\t m_BDVER | m_ZNVER | m_C86_4G)\n \n /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */\n DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, \"sse_typeless_stores\",\n \t m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID\n-\t | m_CORE_ATOM | m_GENERIC)\n+\t | m_CORE_ATOM | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to\n xorps/xorpd and other variants. */\n DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, \"sse_load0_by_pxor\",\n \t m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER\n-\t | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)\n+\t | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM\n+\t | m_C86_4G | m_GENERIC)\n \n /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer\n to SSE registers. If disabled, the moves will be done by storing\n@@ -531,46 +535,49 @@ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, \"avoid_4byte_prefixes\",\n elements. */\n DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, \"use_gather_2parts\",\n \t ~(m_ZNVER | m_CORE_HYBRID\n-\t | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))\n+\t | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS\n+\t | m_C86_4G))\n \n /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2\n elements. */\n DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, \"use_scatter_2parts\",\n-\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))\n+\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))\n+\n \n /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4\n elements. */\n DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, \"use_gather_4parts\",\n \t ~(m_ZNVER | m_CORE_HYBRID\n-\t | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))\n+\t | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS\n+\t | m_C86_4G))\n \n /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4\n elements. */\n DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, \"use_scatter_4parts\",\n-\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))\n+\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))\n \n /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more\n elements. */\n DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, \"use_gather_8parts\",\n \t ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM\n-\t | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))\n+\t | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS | m_C86_4G))\n \n /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more\n elements. */\n DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, \"use_scatter_8parts\",\n-\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))\n+\t ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7))\n \n /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or\n smaller FMA chain. */\n DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, \"avoid_fma_chains\", m_ZNVER\n- | m_YONGFENG | m_SHIJIDADAO | m_GENERIC)\n+\t | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_C86_4G)\n \n /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or\n smaller FMA chain. */\n DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, \"avoid_fma256_chains\",\n \t m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_CORE_HYBRID\n \t | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D\n-\t | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC)\n+\t | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC | m_C86_4G)\n \n /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or\n smaller FMA chain. */\n@@ -593,7 +600,7 @@ DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV,\n /* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,\n V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */\n DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,\n- \"sse_reduction_prefer_pshuf\", m_ZNVER4 | m_ZNVER5)\n+ \"sse_reduction_prefer_pshuf\", m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)\n \n /*****************************************************************************/\n /* AVX instruction selection tuning (some of SSE flags affects AVX, too) */\n@@ -628,19 +635,21 @@ DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM,\n \t \"avx256_avoid_vec_perm\", m_CORE_ATOM)\n \n /* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops. */\n-DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, \"avx512_split_regs\", m_ZNVER4)\n+DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, \"avx512_split_regs\", m_ZNVER4\n+\t | m_C86_4G_M7)\n \n /* It's better to align MOVE_MAX with prefer_vector_width to reduce\n risk of STLF stalls(small store followed by big load.) */\n /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit\n AVX instructions. */\n DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, \"avx256_move_by_pieces\",\n-\t m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)\n+\t m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3\n+\t | m_C86_4G_M4 | m_C86_4G_M6)\n \n /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit\n AVX instructions. */\n DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, \"avx512_move_by_pieces\",\n-\t m_ZNVER4 | m_ZNVER5 | m_ZNVER6)\n+\t m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_C86_4G_M7)\n \n /* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit\n vectorized loops. */\n@@ -650,7 +659,7 @@ DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES, \"avx512_two_epilogues\",\n /* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues\n when fit. */\n DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, \"avx512_masked_epilogues\",\n-\t m_ZNVER4 | m_ZNVER5)\n+\t m_ZNVER4 | m_ZNVER5 | m_C86_4G_M7)\n \n /*****************************************************************************/\n /*****************************************************************************/\n@@ -792,4 +801,4 @@ DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, \"promote_qi_regs\", m_NONE)\n DEF_TUNE (X86_TUNE_SLOW_STC, \"slow_stc\", m_PENT4)\n \n /* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd. */\n-DEF_TUNE (X86_TUNE_USE_RCR, \"use_rcr\", m_AMD_MULTIPLE)\n+DEF_TUNE (X86_TUNE_USE_RCR, \"use_rcr\", m_AMD_MULTIPLE | m_C86_4G)\ndiff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi\nindex 47b0bdf13..5383da19b 100644\n--- a/gcc/doc/extend.texi\n+++ b/gcc/doc/extend.texi\n@@ -29046,6 +29046,18 @@ AMD Family 1ah Zen version 5.\n \n @item znver6\n AMD Family 1ah Zen version 6.\n+\n+@item hygonfam18h\n+HYGON Family 18h CPU.\n+\n+@item c86-4g-m4\n+HYGON Family 18h model 4 dharma CPU.\n+\n+@item c86-4g-m6\n+HYGON Family 18h model 6 shanghai CPU.\n+\n+@item c86-4g-m7\n+HYGON Family 18h model 7 chengdu CPU.\n @end table\n \n Here is an example:\ndiff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi\nindex 00f470a0d..d7bf3fc60 100644\n--- a/gcc/doc/invoke.texi\n+++ b/gcc/doc/invoke.texi\n@@ -35311,6 +35311,27 @@ instruction set support.\n \n @item geode\n AMD Geode embedded processor with MMX and 3DNow!@: instruction set support.\n+\n+@item c86-4g-m4\n+HYGON c86-4g-m4 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,\n+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,\n+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,\n+CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.\n+\n+@item c86-4g-m6\n+HYGON c86-4g-m6 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,\n+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,\n+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,\n+CLFLUSHOPT, XSAVES, LZCNT, POPCNT instruction set support.\n+\n+@item c86-4g-m7\n+HYGON c86-4g-m7 CPU with x86-64, MMX, SSE, SSE2, SSE3, SSE4A, CX16, ABM, SSSE3,\n+SSE4.1, SSE4.2, AES, PCLMUL, AVX, AVX2, BMI, BMI2, F16C, FMA, PRFCHW, FXSR, SHA,\n+XSAVE, XSAVEOPT, XSAVEC, FSGSBASE, RDRND, MOVBE, MWAITX, ADX, RDSEED, CLZERO,\n+CLFLUSHOPT, XSAVES, LZCNT, POPCNT, AVX512F, AVX512DQ, AVX512IFMA, AVX512CD,\n+AVX512BW, AVX512VL, AVX512BF16, AVX512VBMI, AVX512VBMI2, GFNI, AVX512VNNI, VAES,\n+AVX512BITALG, AVX512VPOPCNTDQ, AVX512VP2INTERSECT, AVXVNNI, VPCLMULQDQ,\n+WBNOINVD instruction set support.\n @end table\n \n @opindex mtune\ndiff --git a/gcc/testsuite/g++.target/i386/mv33.C b/gcc/testsuite/g++.target/i386/mv33.C\nnew file mode 100644\nindex 000000000..8591690d2\n--- /dev/null\n+++ b/gcc/testsuite/g++.target/i386/mv33.C\n@@ -0,0 +1,42 @@\n+// Test that dispatching can choose the right multiversion\n+// for HYGON CPUs with the same internal GCC processor id\n+\n+// { dg-do run }\n+// { dg-require-ifunc \"\" }\n+// { dg-options \"-O2\" }\n+\n+#include <assert.h>\n+\n+int __attribute__ ((target(\"default\")))\n+foo ()\n+{\n+ return 0;\n+}\n+\n+int __attribute__ ((target(\"arch=c86-4g-m4\"))) foo () {\n+ return 1;\n+}\n+\n+int __attribute__ ((target(\"arch=c86-4g-m6\"))) foo () {\n+ return 2;\n+}\n+\n+int __attribute__ ((target(\"arch=c86-4g-m7\"))) foo () {\n+ return 3;\n+}\n+\n+int main ()\n+{\n+ int val = foo ();\n+\n+ if (__builtin_cpu_is (\"c86-4g-m4\"))\n+ assert (val == 1);\n+ else if (__builtin_cpu_is (\"c86-4g-m6\"))\n+ assert (val == 2);\n+ else if (__builtin_cpu_is (\"c86-4g-m7\"))\n+ assert (val == 3);\n+ else\n+ assert (val == 0);\n+\n+ return 0;\n+}\ndiff --git a/gcc/testsuite/gcc.target/i386/builtin_target.c b/gcc/testsuite/gcc.target/i386/builtin_target.c\nindex 45554d877..f26ba2be4 100644\n--- a/gcc/testsuite/gcc.target/i386/builtin_target.c\n+++ b/gcc/testsuite/gcc.target/i386/builtin_target.c\n@@ -54,6 +54,10 @@ check_detailed ()\n assert (__builtin_cpu_is (\"amd\"));\n get_amd_cpu (&cpu_model, &cpu_model2, cpu_features2);\n break;\n+ case VENDOR_HYGON:\n+ assert (__builtin_cpu_is (\"hygon\"));\n+ get_hygon_cpu (&cpu_model, &cpu_model2, cpu_features2);\n+ break;\n default:\n break;\n }\n@@ -127,6 +131,8 @@ quick_check ()\n \n assert (__builtin_cpu_is (\"bdver2\") >= 0);\n \n+ assert (__builtin_cpu_is (\"c86-4g-m4\") >= 0);\n+\n return 0;\n }\n \ndiff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\nindex aa395185b..43ccaa9d9 100644\n--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc\n@@ -239,6 +239,9 @@ extern void test_arch_znver3 (void) __attribute__((__target__(\"arch=\n extern void test_arch_znver4 (void) __attribute__((__target__(\"arch=znver4\")));\n extern void test_arch_znver5 (void) __attribute__((__target__(\"arch=znver5\")));\n extern void test_arch_znver6 (void) __attribute__((__target__(\"arch=znver6\")));\n+extern void test_arch_c86_4g_m4 (void) __attribute__((__target__(\"arch=c86-4g-m4\")));\n+extern void test_arch_c86_4g_m6 (void) __attribute__((__target__(\"arch=c86-4g-m6\")));\n+extern void test_arch_c86_4g_m7 (void) __attribute__((__target__(\"arch=c86-4g-m7\")));\n \n extern void test_tune_nocona (void)\t\t__attribute__((__target__(\"tune=nocona\")));\n extern void test_tune_core2 (void)\t\t__attribute__((__target__(\"tune=core2\")));\n@@ -267,6 +270,9 @@ extern void test_tune_znver3 (void) __attribute__((__target__(\"tune=\n extern void test_tune_znver4 (void) __attribute__((__target__(\"tune=znver4\")));\n extern void test_tune_znver5 (void) __attribute__((__target__(\"tune=znver5\")));\n extern void test_tune_znver6 (void) __attribute__((__target__(\"tune=znver6\")));\n+extern void test_tune_c86_4g_m4 (void) __attribute__((__target__(\"tune=c86-4g-m4\")));\n+extern void test_tune_c86_4g_m6 (void) __attribute__((__target__(\"tune=c86-4g-m6\")));\n+extern void test_tune_c86_4g_m7 (void) __attribute__((__target__(\"tune=c86-4g-m7\")));\n \n extern void test_fpmath_sse (void)\t\t__attribute__((__target__(\"sse2,fpmath=sse\")));\n extern void test_fpmath_387 (void)\t\t__attribute__((__target__(\"sse2,fpmath=387\")));\n", "prefixes": [ "v2" ] }