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GET /api/1.1/patches/2229798/?format=api
{ "id": 2229798, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229798/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428182454.464655-3-fabio.m.de.francesco@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.1/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428182454.464655-3-fabio.m.de.francesco@linux.intel.com>", "date": "2026-04-28T18:24:35", "name": "[2/2] cxl/core: Recover from PM Init failure via cxl_reset_bus_function()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7c755e52ac10c731ed428c96ecf1395376c1d053", "submitter": { "id": 88588, "url": "http://patchwork.ozlabs.org/api/1.1/people/88588/?format=api", "name": "Fabio M. De Francesco", "email": "fabio.m.de.francesco@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260428182454.464655-3-fabio.m.de.francesco@linux.intel.com/mbox/", "series": [ { "id": 501923, "url": "http://patchwork.ozlabs.org/api/1.1/series/501923/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=501923", "date": "2026-04-28T18:24:34", "name": "[1/2] PCI/CXL: Allow PM Init to complete on cxl_bus reset if ACS SV enabled", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501923/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229798/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229798/checks/", "tags": {}, "headers": { "Return-Path": "\n <linux-pci+bounces-53348-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=XGp54Pk+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=\"81927223\"", "E=Sophos;i=\"6.23,204,1770624000\";\n d=\"scan'208\";a=\"81927223\"", "E=Sophos;i=\"6.23,204,1770624000\";\n d=\"scan'208\";a=\"257352905\"" ], "X-ExtLoop1": "1", "From": "\"Fabio M. De Francesco\" <fabio.m.de.francesco@linux.intel.com>", "To": "linux-cxl@vger.kernel.org", "Cc": "Davidlohr Bueso <dave@stgolabs.net>,\n\tJonathan Cameron <jonathan.cameron@huawei.com>,\n\tDave Jiang <dave.jiang@intel.com>,\n\tAlison Schofield <alison.schofield@intel.com>,\n\tVishal Verma <vishal.l.verma@intel.com>,\n\tIra Weiny <ira.weiny@intel.com>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tBjorn Helgaas <bhelgaas@google.com>,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org,\n\t\"Fabio M. De Francesco\" <fabio.m.de.francesco@linux.intel.com>", "Subject": "[PATCH 2/2] cxl/core: Recover from PM Init failure via\n cxl_reset_bus_function()", "Date": "Tue, 28 Apr 2026 20:24:35 +0200", "Message-ID": "<20260428182454.464655-3-fabio.m.de.francesco@linux.intel.com>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260428182454.464655-1-fabio.m.de.francesco@linux.intel.com>", "References": "<20260428182454.464655-1-fabio.m.de.francesco@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "CXL r4.0 sec 8.1.5.1 Implementation Note describes a scenario in which a\nSecondary Bus Reset, a Link Down, or Downstream Port Containment on a\nCXL Downstream Port prevents Port PM Init from completing when ACS\nSource Validation is enabled.\n\nDuring CXL enumeration, for each CXL Downstream Port in a memdev's\nancestry, check whether PM Init has completed. If it has not, invoke\ncxl_reset_bus_function() which is exported for use by CXL.\n\nSigned-off-by: Fabio M. De Francesco <fabio.m.de.francesco@linux.intel.com>\n---\n drivers/cxl/core/pci.c | 30 ++++++++++++++++++++++++++++++\n drivers/cxl/core/port.c | 22 ++++++++++++++++++++++\n drivers/cxl/cxlpci.h | 3 +++\n drivers/pci/pci.c | 3 ++-\n include/linux/pci.h | 1 +\n include/uapi/linux/pci_regs.h | 2 ++\n 6 files changed, 60 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c\nindex d1f487b3d809..de6a317df650 100644\n--- a/drivers/cxl/core/pci.c\n+++ b/drivers/cxl/core/pci.c\n@@ -926,3 +926,33 @@ int cxl_port_get_possible_dports(struct cxl_port *port)\n \n \treturn ctx.count;\n }\n+\n+/**\n+ * cxl_port_pm_init_is_complete - check the downstream port's PM Init Complete\n+ * @pdev: downstream port\n+ *\n+ * Read the Port Power Management Initialization Complete bit in the\n+ * Downstream Port's CXL DVSEC Port Extended Status register.\n+ *\n+ * Return: false only when the bit is observably clear. Return true when PM\n+ * init is complete, when @pdev is not a CXL port (no Port DVSEC), or when\n+ * the status register cannot be read.\n+ */\n+bool cxl_port_pm_init_is_complete(struct pci_dev *pdev)\n+{\n+\tu16 status;\n+\tu16 dvsec;\n+\tint rc;\n+\n+\tdvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,\n+\t\t\t\t\t PCI_DVSEC_CXL_PORT);\n+\tif (!dvsec)\n+\t\treturn true;\n+\n+\trc = pci_read_config_word(pdev, dvsec + PCI_DVSEC_CXL_PORT_EXT_STATUS,\n+\t\t\t\t &status);\n+\tif (rc || PCI_POSSIBLE_ERROR(status))\n+\t\treturn true;\n+\n+\treturn !!FIELD_GET(PCI_DVSEC_CXL_PORT_EXT_STATUS_PM_INIT_COMP, status);\n+}\ndiff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c\nindex c5aacd7054f1..a91841855d3b 100644\n--- a/drivers/cxl/core/port.c\n+++ b/drivers/cxl/core/port.c\n@@ -1825,6 +1825,28 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd)\n \t\tif (is_cxl_host_bridge(dport_dev))\n \t\t\treturn 0;\n \n+\t\t/*\n+\t\t * Check the downstream port's PM init status, and if it has\n+\t\t * failed retry PM init according to CXL Spec. 4.0 Sect. 8.1.5.1\n+\t\t * - Implementation Note\n+\t\t */\n+\t\tif (dev_is_pci(dport_dev) && dev_is_pci(iter->parent)) {\n+\t\t\tstruct pci_dev *dport_pdev = to_pci_dev(dport_dev);\n+\n+\t\t\tif (!cxl_port_pm_init_is_complete(dport_pdev)) {\n+\t\t\t\tdev_dbg(&cxlmd->dev,\n+\t\t\t\t\t\"PM init failed for %s, retrying PM init\\n\",\n+\t\t\t\t\tdev_name(dport_dev));\n+\n+\t\t\t\tcxl_reset_bus_function(to_pci_dev(iter->parent), false);\n+\n+\t\t\t\tif (!cxl_port_pm_init_is_complete(dport_pdev))\n+\t\t\t\t\tdev_dbg(&cxlmd->dev,\n+\t\t\t\t\t\t\"PM init failed retry for %s\\n\",\n+\t\t\t\t\t\tdev_name(dport_dev));\n+\t\t\t}\n+\t\t}\n+\n \t\tuport_dev = dport_dev->parent;\n \t\tif (!uport_dev) {\n \t\t\tdev_warn(dev, \"at %s no parent for dport: %s\\n\",\ndiff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h\nindex b826eb53cf7b..c66ff2ce82a3 100644\n--- a/drivers/cxl/cxlpci.h\n+++ b/drivers/cxl/cxlpci.h\n@@ -114,4 +114,7 @@ static inline void devm_cxl_port_ras_setup(struct cxl_port *port)\n \n int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,\n \t\t struct cxl_register_map *map);\n+\n+bool cxl_port_pm_init_is_complete(struct pci_dev *pdev);\n+\n #endif /* __CXL_PCI_H__ */\ndiff --git a/drivers/pci/pci.c b/drivers/pci/pci.c\nindex 047d3b4508a5..ae30da22daf4 100644\n--- a/drivers/pci/pci.c\n+++ b/drivers/pci/pci.c\n@@ -4974,7 +4974,7 @@ static void cxl_restore_acs_sv_bme(struct pci_dev *bridge, u16 saved_cmd,\n * Return: 0 on success, -ENOTTY if the reset cannot be issued, or an\n * errno from the reset path.\n */\n-static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)\n+int cxl_reset_bus_function(struct pci_dev *dev, bool probe)\n {\n \tstruct pci_dev *bridge;\n \tu16 dvsec, reg, val;\n@@ -5023,6 +5023,7 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)\n \tpci_dev_reset_iommu_done(dev);\n \treturn rc;\n }\n+EXPORT_SYMBOL_NS_GPL(cxl_reset_bus_function, \"CXL\");\n \n void pci_dev_lock(struct pci_dev *dev)\n {\ndiff --git a/include/linux/pci.h b/include/linux/pci.h\nindex 2c4454583c11..1fb1360d41e8 100644\n--- a/include/linux/pci.h\n+++ b/include/linux/pci.h\n@@ -1477,6 +1477,7 @@ int pci_probe_reset_slot(struct pci_slot *slot);\n int pci_probe_reset_bus(struct pci_bus *bus);\n int pci_reset_bus(struct pci_dev *dev);\n void pci_reset_secondary_bus(struct pci_dev *dev);\n+int cxl_reset_bus_function(struct pci_dev *dev, bool probe);\n void pcibios_reset_secondary_bus(struct pci_dev *dev);\n void pci_update_resource(struct pci_dev *dev, int resno);\n int __must_check pci_assign_resource(struct pci_dev *dev, int i);\ndiff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h\nindex 14f634ab9350..7e2579f89041 100644\n--- a/include/uapi/linux/pci_regs.h\n+++ b/include/uapi/linux/pci_regs.h\n@@ -1369,6 +1369,8 @@\n \n /* CXL r4.0, 8.1.5: Extensions DVSEC for Ports */\n #define PCI_DVSEC_CXL_PORT\t\t\t\t3\n+#define PCI_DVSEC_CXL_PORT_EXT_STATUS\t\t\t0x0A\n+#define PCI_DVSEC_CXL_PORT_EXT_STATUS_PM_INIT_COMP\t_BITUL(0)\n #define PCI_DVSEC_CXL_PORT_CTL\t\t\t\t0x0c\n #define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR\t\t0x00000001\n \n", "prefixes": [ "2/2" ] }