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GET /api/1.1/patches/2229797/?format=api
{ "id": 2229797, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229797/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/d504361c-a3eb-40d7-b7e7-2a7c865ab73f@oss.qualcomm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/1.1/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<d504361c-a3eb-40d7-b7e7-2a7c865ab73f@oss.qualcomm.com>", "date": "2026-04-28T18:25:47", "name": "[V3,to-be-committed,RISC-V,PR,target/124760] Promote SI to DI in some cases to encourage shNadd insns", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "419dfebace89317906285a65d4b53160c26c647a", "submitter": { "id": 92310, "url": "http://patchwork.ozlabs.org/api/1.1/people/92310/?format=api", "name": "Jeffrey Law", "email": "jeffrey.law@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/d504361c-a3eb-40d7-b7e7-2a7c865ab73f@oss.qualcomm.com/mbox/", "series": [ { "id": 501924, "url": "http://patchwork.ozlabs.org/api/1.1/series/501924/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=501924", "date": "2026-04-28T18:25:47", "name": "[V3,to-be-committed,RISC-V,PR,target/124760] Promote SI to DI in some cases to encourage shNadd insns", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/501924/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229797/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229797/checks/", "tags": {}, "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=FtEC9XJz;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=Q1z5COoN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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boundary=\"------------UjYvEfNcK0S0aOq30yQyCzfU\"", "Message-ID": "<d504361c-a3eb-40d7-b7e7-2a7c865ab73f@oss.qualcomm.com>", "Date": "Tue, 28 Apr 2026 12:25:47 -0600", "MIME-Version": "1.0", "User-Agent": "Mozilla Thunderbird", "Content-Language": "en-US", "To": "'GCC Patches' <gcc-patches@gcc.gnu.org>", "From": "Jeffrey Law <jeffrey.law@oss.qualcomm.com>", "Subject": "[V3][to-be-committed][RISC-V][PR target/124760] Promote SI to DI in\n some cases to encourage shNadd insns", "X-Authority-Analysis": "v=2.4 cv=abJRWxot c=1 sm=1 tr=0 ts=69f0fbaf cx=c_pps\n a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=asGLMfRmzhnGNxaIYohjRg==:17\n a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22\n a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=r77TgQKjGQsHNAKrUKIA:9\n a=m8iliXWHfpSA1kiA3gIA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10\n a=-d7-HylfX6lhVPyK7WUA:9 a=B2y7HmGcmWMA:10 a=6Ab_bkdmUrQuMsNx7PHu:22", "X-Proofpoint-GUID": "JOL9rUiVgzlEAbF59mBVLktMfMGV68nl", "X-Proofpoint-ORIG-GUID": "JOL9rUiVgzlEAbF59mBVLktMfMGV68nl", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwNDI4MDE3OSBTYWx0ZWRfX+Sww9AsIsbdN\n EYQF69VSWdDEBAXVELYn1mJX6XjyML9uvrePJaQBWs3j9moruTrD/aoJS3zxRZgTGzzSO/TLr67\n oNivqGb+Jdp6QK48IA6S5UEDZxfi4DqGP9/2vC0elBTZlfFuoXsqIaNBoilX+l4ZOORpHYrAg10\n u40koVdzwrYmhTyiiddmwEC2UAryA9GQSpK0gus4nB4Jxh/aM7g3b120kO/S94ylibjpyPWGkvu\n LzWDTosJQpCfD+MiKZJRLJ1mumbVY/sVaSfopYJ2Zr5QWoiVM+Iag+FXSpfM0rZAat1Zj1Qb+LJ\n jgmZ3CYO1AhgIkP8RxJ8XtL30V4rn1zP6TduG9k21Bjj5Y0uKcehEH9j9KctSvuuH2Rjb1u5ho/\n /7OIICdB1Zc1Go8Q6Q8JKKpHvyLfV3blNOgbTRVlnqT4EMpOhcoZvHdKxYdkv429WzahhCQBuJn\n ZFOmMd0waJXzzmizjbw==", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0\n phishscore=0 bulkscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280179", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "OK. Pre-commit CI is picking up patches for testing again. Of course \nthe baseline moved and the patch in question doesn't apply anymore. So \nI've regenerated the patch and I'm throwing it back at the pre-commit \ntester.\n\n--\n\n\nSo for this testcase:\n\n\nint foo (int t)\n {\n return 3 * t - 1;\n }\n\nWe currently generate:\n\n\n slliw a5,a0,1\n addw a0,a5,a0\n addiw a0,a0,-1\n ret\n\n\nIntuitively we can see we're doing a 32->64 sign extension at each step \nand we could drop the intermediate sign extensions. In fact, not only \ncan we drop the intermediate sign extensions, we can safely \"promote\" \nthe intermediate operations from SI to DI with a final sign extending \nadd. Conceptually that unlocks combining the first shift+add into a \nshNadd insn resulting in this code:\n\n sh1add a0, a0, a0\n addiw a0, a0, -1\n ret\n\nThe patch, but not the testcase, has been in my tree for a while, so \nit's been through bootstrap & regression testing on the BPI and Pioneer \nas well as testing on riscv32-elf and riscv64-elf. Obviously I'll wait \nfor pre-commit CI to do its thing before pushing.\n\nJeff\nPR target/124760\ngcc/\n\t* config/riscv/bitmanip.md (SI->DI promoting shadd pattern): Promote\n\tintermediate SI ops to DI ops when there's a final extending op.\n\ngcc/testsuite\n\n\t* gcc.target/riscv/pr124760.c: New test.", "diff": "diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md\nindex 1ca9f82b363f..c9561b0b6228 100644\n--- a/gcc/config/riscv/bitmanip.md\n+++ b/gcc/config/riscv/bitmanip.md\n@@ -1426,3 +1426,18 @@ (define_split\n [(set (match_dup 2) (plus:X (match_dup 1) (const_int -1)))\n (set (match_dup 0) (and:X (not:X (match_dup 1)) (match_dup 2)))])\n \n+(define_split\n+ [(set (match_operand:DI 0 \"register_operand\")\n+\t(sign_extend:DI (plus:SI (plus:SI (ashift:SI (match_operand:SI 1 \"register_operand\")\n+\t\t\t\t\t\t (match_operand 2 \"imm123_operand\"))\n+\t\t\t\t\t (match_operand:SI 3 \"register_operand\"))\n+\t\t\t\t (match_operand:SI 4 \"arith_operand\"))))\n+ (clobber (match_operand:DI 5 \"register_operand\"))]\n+ \"TARGET_64BIT && TARGET_ZBA\"\n+ [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))\n+ (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 6) (match_dup 4))))]\n+ {\n+ operands[1] = gen_lowpart (DImode, operands[1]);\n+ operands[3] = gen_lowpart (DImode, operands[3]);\n+ operands[6] = gen_lowpart (SImode, operands[5]);\n+ })\ndiff --git a/gcc/testsuite/gcc.target/riscv/pr124760.c b/gcc/testsuite/gcc.target/riscv/pr124760.c\nnew file mode 100644\nindex 000000000000..0c4768ff0474\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/riscv/pr124760.c\n@@ -0,0 +1,14 @@\n+/* { dg-do compile { target rv64 } } */\n+/* { dg-additional-options \"-march=rv64gcb_zicond -mabi=lp64d\" } */\n+/* { dg-skip-if \"\" { *-*-* } { \"-O0\" \"-Og\" \"-Os\" \"-Oz\" } } */\n+\n+\n+int foo (int t)\n+{\n+ return 3 * t - 1;\n+}\n+\n+/* { dg-final { scan-assembler-not \"slliw\\t\" } } */\n+/* { dg-final { scan-assembler-not \"addw\\t\" } } */\n+/* { dg-final { scan-assembler-times \"sh1add\\t\" 1 } } */\n+/* { dg-final { scan-assembler-times \"addiw\\t\" 1 } } */\n", "prefixes": [ "V3", "to-be-committed", "RISC-V", "PR", "target/124760" ] }