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GET /api/1.1/patches/2229743/?format=api
{ "id": 2229743, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229743/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163950.9BB2668D09@verein.lst.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428163950.9BB2668D09@verein.lst.de>", "date": "2026-04-28T16:39:50", "name": "[v2,9/9] pci: brcmstb: Adapt to AXI bridge", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b4b12c02b7fe684157b45b34824b1ca36bcdb849", "submitter": { "id": 2722, "url": "http://patchwork.ozlabs.org/api/1.1/people/2722/?format=api", "name": "Torsten Duwe", "email": "duwe@lst.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163950.9BB2668D09@verein.lst.de/mbox/", "series": [ { "id": 501902, "url": "http://patchwork.ozlabs.org/api/1.1/series/501902/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501902", "date": "2026-04-28T16:23:19", "name": "ARM: RPi5: Enable PCIe", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501902/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229743/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229743/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=lst.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=lst.de", "phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mW16n64z1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 02:44:45 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 8FC1D846A2;\n\tTue, 28 Apr 2026 18:43:25 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 3186A84656; Tue, 28 Apr 2026 18:39:54 +0200 (CEST)", "from verein.lst.de (verein.lst.de [213.95.11.211])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3CC6284612\n for <u-boot@lists.denx.de>; Tue, 28 Apr 2026 18:39:52 +0200 (CEST)", "by verein.lst.de (Postfix, from userid 2005)\n id 9BB2668D09; Tue, 28 Apr 2026 18:39:50 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "Subject": "[PATCH v2 9/9] pci: brcmstb: Adapt to AXI bridge", "To": "Peter Robinson <pbrobinson@gmail.com>,\n Matthias Brugger <mbrugger@suse.com>", "Cc": "=?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=\n\t=?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?=\n\t=?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?=\n\t=?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?=\n\t=?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?=\n\t=?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?=\n\t=?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?=\n\t=?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?=\n\t=?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?=\n\t=?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?=\n\t=?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?=\n\t=?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?=\n\t=?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?=\n\t=?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?=\n\t=?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?=\n\t=?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?=\n\t=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=\n\t=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=\n\t=?unknown-8bit?q?=2Ede?=", "In-Reply-To": "<20260428162319.99B4268B05@verein.lst.de>", "Message-Id": "<20260428163950.9BB2668D09@verein.lst.de>", "Date": "Tue, 28 Apr 2026 18:39:50 +0200 (CEST)", "From": "duwe@lst.de (Torsten Duwe)", "X-Mailman-Approved-At": "Tue, 28 Apr 2026 18:43:21 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Torsten Duwe <duwe@suse.de>\n\nFix-ups for the BCM root complex when it is located behind an AXI\nbridge and clocked with 54MHz. Some are from kernel commit\n377bced88c326, some where picked by Oleksii off a now-stale older\nbranch. All reworked for the simpler setup code in U-Boot.\n\nSigned-off-by: Torsten Duwe <duwe@suse.de>\nCo-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>\nTested-by: Pedro Falcato <pfalcato@suse.de>\n\n---\n .../mach-bcm283x/include/mach/acpi/bcm2711.h | 1 +\n drivers/pci/pcie_brcmstb.c | 64 ++++++++++++++++++-\n 2 files changed, 64 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\nindex 6eb5389b858..869482eaffe 100644\n--- a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\n+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h\n@@ -54,6 +54,7 @@\n #define MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000\n #define MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000\n #define MISC_CTRL_MAX_BURST_SIZE_128 0x0\n+#define MISC_CTRL_MAX_BURST_SIZE_128_2712\t\t0x100000\n #define MISC_CTRL_SCB0_SIZE_MASK 0xf8000000\n \n #define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c\ndiff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c\nindex 05b80a45b50..f0b0f1cc117 100644\n--- a/drivers/pci/pcie_brcmstb.c\n+++ b/drivers/pci/pcie_brcmstb.c\n@@ -551,6 +551,30 @@ static void brcm_pcie_set_inbound_windows(struct udevice *dev)\n \t}\n }\n \n+static void brcm_pcie_munge_pll(struct brcm_pcie *pcie)\n+{\n+\tu32 tmp;\n+\tint ret, i;\n+\tu8 regs[] = { 0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e };\n+\tu16 data[] = { 0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007 };\n+\n+\tret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET,\n+\t\t\t\t 0x1600);\n+\tfor (i = 0; i < ARRAY_SIZE(regs); i++) {\n+\t\tbrcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);\n+\t\tdebug(\"PCIE MDIO pre_refclk 0x%02x = 0x%04x\\n\",\n+\t\t regs[i], tmp);\n+\t}\n+\tfor (i = 0; i < ARRAY_SIZE(regs); i++) {\n+\t\tbrcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]);\n+\t\tbrcm_pcie_mdio_read(pcie->base, MDIO_PORT0, regs[i], &tmp);\n+\t\tdebug(\"PCIE MDIO post_refclk 0x%02x = 0x%04x\\n\",\n+\t\t regs[i], tmp);\n+\t}\n+\n+\tudelay(200);\n+}\n+\n static int brcm_pcie_probe(struct udevice *dev)\n {\n \tstruct udevice *ctlr = pci_get_controller(dev);\n@@ -592,12 +616,27 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t/* Wait for SerDes to be stable */\n \tudelay(100);\n \n+\tif (pcie->pcie_cfg->type == BCM2712) {\n+\t\t/* Allow a 54MHz (xosc) refclk source */\n+\t\tbrcm_pcie_munge_pll(pcie);\n+\t\t/* Fix for L1SS errata */\n+\t\ttmp = readl(base + PCIE_RC_PL_PHY_CTL_15);\n+\t\ttmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;\n+\t\t/* PM clock period is 18.52ns (round down) */\n+\t\ttmp |= 0x12;\n+\t\twritel(tmp, base + PCIE_RC_PL_PHY_CTL_15);\n+\t}\n+\n+\ttmp = (pcie->pcie_cfg->type == BCM2712) ?\n+\t\t\tMISC_CTRL_MAX_BURST_SIZE_128_2712 :\n+\t\t\tMISC_CTRL_MAX_BURST_SIZE_128;\n \t/* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */\n \tclrsetbits_le32(base + PCIE_MISC_MISC_CTRL,\n \t\t\tMISC_CTRL_MAX_BURST_SIZE_MASK,\n \t\t\tMISC_CTRL_SCB_ACCESS_EN_MASK |\n \t\t\tMISC_CTRL_CFG_READ_UR_MODE_MASK |\n-\t\t\tMISC_CTRL_MAX_BURST_SIZE_128);\n+\t\t\tMISC_CTRL_PCIE_RCB_MPS_MODE_MASK |\n+\t\t\ttmp);\n \n \ttmp = readl(base + PCIE_MISC_MISC_CTRL);\n \tif (pcie->pcie_cfg->type == BCM2712) {\n@@ -617,6 +656,29 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t}\n \twritel(tmp, base + PCIE_MISC_MISC_CTRL);\n \n+\tif (pcie->pcie_cfg->type == BCM2712) {\n+\t\t/* Suppress AXI error responses and return 1s for read failures */\n+\t\ttmp = readl(base + PCIE_MISC_UBUS_CTRL);\n+\t\tu32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK);\n+\t\tu32p_replace_bits(&tmp, 1, PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK);\n+\t\twritel(tmp, base + PCIE_MISC_UBUS_CTRL);\n+\t\twritel(0xffffffff, base + PCIE_MISC_AXI_READ_ERROR_DATA);\n+\n+\t\t/*\n+\t\t * Adjust timeouts. The UBUS timeout also affects CRS\n+\t\t * completion retries, as the request will get terminated if\n+\t\t * either timeout expires, so both have to be a large value\n+\t\t * (in clocks of 750MHz).\n+\t\t * Set UBUS timeout to 250ms, then set RC config retry timeout\n+\t\t * to be ~240ms.\n+\t\t *\n+\t\t * Setting CRSVis=1 will stop the core from blocking on a CRS\n+\t\t * response, but does require the device to be well-behaved...\n+\t\t */\n+\t\twritel(0xB2D0000, base + PCIE_MISC_UBUS_TIMEOUT);\n+\t\twritel(0xABA0000, base + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);\n+\t}\n+\n \t/* Disable the PCIe->GISB memory window (RC_BAR1) */\n \tclrbits_le32(base + PCIE_MISC_RC_BAR1_CONFIG_LO,\n \t\t RC_BAR1_CONFIG_LO_SIZE_MASK);\n", "prefixes": [ "v2", "9/9" ] }