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GET /api/1.1/patches/2229742/?format=api
{ "id": 2229742, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163946.42D4368D12@verein.lst.de/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<20260428163946.42D4368D12@verein.lst.de>", "date": "2026-04-28T16:39:46", "name": "[v2,8/9] pci: brcmstb: rework iBAR handling", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f9d826e3dfd46044d581d68df9dacdf6c703fd3d", "submitter": { "id": 2722, "url": "http://patchwork.ozlabs.org/api/1.1/people/2722/?format=api", "name": "Torsten Duwe", "email": "duwe@lst.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163946.42D4368D12@verein.lst.de/mbox/", "series": [ { "id": 501902, "url": "http://patchwork.ozlabs.org/api/1.1/series/501902/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501902", "date": "2026-04-28T16:23:19", "name": "ARM: RPi5: Enable PCIe", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501902/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229742/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229742/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=lst.de", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n dmarc=fail (p=none dis=none) header.from=lst.de", "phobos.denx.de; spf=pass smtp.mailfrom=duwe@lst.de" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g4mVr1fFhz1yHv\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 29 Apr 2026 02:44:36 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 5B6528469E;\n\tTue, 28 Apr 2026 18:43:25 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 0F3038464E; Tue, 28 Apr 2026 18:39:50 +0200 (CEST)", "from verein.lst.de (verein.lst.de [213.95.11.211])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id F29FE8460E\n for <u-boot@lists.denx.de>; Tue, 28 Apr 2026 18:39:47 +0200 (CEST)", "by verein.lst.de (Postfix, from userid 2005)\n id 42D4368D12; Tue, 28 Apr 2026 18:39:46 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-1.9 required=5.0 tests=BAYES_00,\n RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham\n autolearn_force=no version=3.4.2", "Subject": "[PATCH v2 8/9] pci: brcmstb: rework iBAR handling", "To": "Peter Robinson <pbrobinson@gmail.com>,\n Matthias Brugger <mbrugger@suse.com>", "Cc": "=?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=\n\t=?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?=\n\t=?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?=\n\t=?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?=\n\t=?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?=\n\t=?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?=\n\t=?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?=\n\t=?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?=\n\t=?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?=\n\t=?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?=\n\t=?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?=\n\t=?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?=\n\t=?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?=\n\t=?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?=\n\t=?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?=\n\t=?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?=\n\t=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=\n\t=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=\n\t=?unknown-8bit?q?=2Ede?=", "In-Reply-To": "<20260428162319.99B4268B05@verein.lst.de>", "Message-Id": "<20260428163946.42D4368D12@verein.lst.de>", "Date": "Tue, 28 Apr 2026 18:39:46 +0200 (CEST)", "From": "duwe@lst.de (Torsten Duwe)", "X-Mailman-Approved-At": "Tue, 28 Apr 2026 18:43:21 +0200", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Torsten Duwe <duwe@suse.de>\n\nRework the setup of inbound PCIe windows: use the convenience functions\nfrom Linux kernel commit ae6476c6de187 to calculate the BAR offsets and\nfactor out the setup code into a separate function.\n\nThe Linux kernel first allocates and populates an array of inbound_win[]\nand sets the BARs from it later, while U-Boot does it all on the fly,\nin one go, so the code is not 1:1 comparable.\n\nSigned-off-by: Torsten Duwe <duwe@suse.de>\nTested-by: Pedro Falcato <pfalcato@suse.de>\n\n---\n drivers/pci/pcie_brcmstb.c | 150 ++++++++++++++++++++++++++++++++-----\n 1 file changed, 131 insertions(+), 19 deletions(-)", "diff": "diff --git a/drivers/pci/pcie_brcmstb.c b/drivers/pci/pcie_brcmstb.c\nindex 8a25fb04563..05b80a45b50 100644\n--- a/drivers/pci/pcie_brcmstb.c\n+++ b/drivers/pci/pcie_brcmstb.c\n@@ -50,6 +50,29 @@\n #define SSC_STATUS_PLL_LOCK_MASK\t\t\t0x800\n #define SSC_STATUS_PLL_LOCK_SHIFT\t\t\t11\n \n+#define PCIE_RC_PL_PHY_CTL_15\t\t\t\t0x184c\n+#define PCIE_RC_PL_PHY_CTL_15_DIS_PLL_PD_MASK\t\t0x400000\n+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK\t0xff\n+\n+#define PCIE_MISC_UBUS_CTRL\t\t\t\t0x40a4\n+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK\tBIT(13)\n+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK\tBIT(19)\n+#define PCIE_MISC_AXI_READ_ERROR_DATA\t\t\t0x4170\n+#define PCIE_MISC_UBUS_TIMEOUT\t\t\t\t0x40A8\n+#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT\t\t0x405c\n+#define PCIE_MISC_RC_BAR4_CONFIG_LO\t\t\t0x40d4\n+#define PCIE_MISC_RC_BAR4_CONFIG_HI\t\t\t0x40d8\n+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK\t\t0xff\n+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI\t\t0x4110\n+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE\t\t0x1\n+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK\t\t0xfffff000\n+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO\t\t0x410c\n+\n+#define PCIE_MISC_UBUS_BAR1_CONFIG_REMAP\t\t0x40ac\n+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP\t\t0x40b4\n+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK\tBIT(0)\n+#define MISC_CTRL_PCIE_RCB_MPS_MODE_MASK\t\t0x400\n+\n enum {\n \tRGR1_SW_INIT_1,\n \tEXT_CFG_INDEX,\n@@ -437,17 +460,105 @@ static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,\n \twritel(tmp, base + PCIE_MEM_WIN0_LIMIT_HI(win));\n }\n \n+static u32 brcm_bar_reg_offset(int bar)\n+{\n+\tif (bar <= 3)\n+\t\treturn PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1);\n+\telse\n+\t\treturn PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4);\n+}\n+\n+static u32 brcm_ubus_reg_offset(int bar)\n+{\n+\tif (bar <= 3)\n+\t\treturn PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1);\n+\telse\n+\t\treturn PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO + 8 * (bar - 4);\n+}\n+\n+/*\n+ * Round size up to the next power of two, as required by\n+ * brcm_pcie_encode_ibar_size(). If size is already a power of two\n+ * fls64(size - 1) still gives the correct result because the hardware\n+ * encodes the exponent, not the raw value.\n+ */\n+static u64 brcm_ibar_round_size(u64 size)\n+{\n+\treturn 1ULL << fls64(size - 1);\n+}\n+\n+static void brcm_pcie_set_inbound_windows(struct udevice *dev)\n+{\n+\tstruct brcm_pcie *pcie = dev_get_priv(dev);\n+\tvoid __iomem *base = pcie->base;\n+\tbool is_2712 = (pcie->pcie_cfg->type == BCM2712);\n+\tint i, ibar_no, ret;\n+\tu32 tmp;\n+\n+\tibar_no = 0;\n+\t/* pre-2712 chips leave the first entry empty */\n+\tif (pcie->pcie_cfg->type != BCM2712)\n+\t\tibar_no++;\n+\n+\t/* program inbound windows from OF property \"dma-regions\" */\n+\tfor (i = 0; i < 7; i++, ibar_no++) {\n+\t\tu64 bar_cpu, bar_size, bar_pci;\n+\t\tstruct pci_region region;\n+\t\tint ubus_bar_offset, rc_bar_offset;\n+\n+\t\tret = pci_get_dma_regions(dev, ®ion, i);\n+\t\tif (ret)\t/* no region #i? Then we're done. */\n+\t\t\tbreak;\n+\t\tubus_bar_offset = brcm_ubus_reg_offset(ibar_no + 1);\n+\t\trc_bar_offset = brcm_bar_reg_offset(ibar_no + 1);\n+\n+\t\tbar_pci = region.bus_start;\n+\t\tbar_cpu = region.phys_start;\n+\t\tbar_size = region.size;\n+\n+\t\tif (is_2712) {\n+\t\t\t/* BCM2712: BAR holds raw PCI address; UBUS remap\n+\t\t\t * registers supply the CPU-side translation. */\n+\t\t\ttmp = lower_32_bits(bar_pci);\n+\t\t\tu32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size),\n+\t\t\t\t\t RC_BAR2_CONFIG_LO_SIZE_MASK);\n+\t\t\twritel(tmp, base + rc_bar_offset);\n+\t\t\twritel(upper_32_bits(bar_pci), base + rc_bar_offset + 4);\n+\n+\t\t\ttmp = lower_32_bits(bar_cpu) &\n+\t\t\t\t\tPCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK;\n+\t\t\ttmp |= PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE;\n+\t\t\twritel(tmp, base + ubus_bar_offset);\n+\n+\t\t\ttmp = upper_32_bits(bar_cpu) &\n+\t\t\t\tPCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK;\n+\t\t\twritel(tmp, base + ubus_bar_offset + 4);\n+\t\t} else {\n+\t\t\t/* Pre-BCM2712 (e.g. BCM2711 / RPi4): the BAR config\n+\t\t\t * register holds the offset (bus_start - phys_start),\n+\t\t\t * not the raw PCI address. The size must be rounded\n+\t\t\t * up to the next power of two before encoding. */\n+\t\t\tu64 bar_offset = bar_pci - bar_cpu;\n+\t\t\tu64 bar_size_po2 = brcm_ibar_round_size(bar_size);\n+\n+\t\t\ttmp = lower_32_bits(bar_offset);\n+\t\t\tu32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(bar_size_po2),\n+\t\t\t\t\t RC_BAR2_CONFIG_LO_SIZE_MASK);\n+\t\t\twritel(tmp, base + rc_bar_offset);\n+\t\t\twritel(upper_32_bits(bar_offset), base + rc_bar_offset + 4);\n+\t\t\t/* UBUS remap registers are not used on pre-2712 hardware. */\n+\t\t}\n+\t}\n+}\n+\n static int brcm_pcie_probe(struct udevice *dev)\n {\n \tstruct udevice *ctlr = pci_get_controller(dev);\n \tstruct pci_controller *hose = dev_get_uclass_priv(ctlr);\n \tstruct brcm_pcie *pcie = dev_get_priv(dev);\n \tvoid __iomem *base = pcie->base;\n-\tstruct pci_region region;\n \tbool ssc_good = false;\n \tint num_out_wins = 0;\n-\tu64 rc_bar2_offset, rc_bar2_size;\n-\tunsigned int scb_size_val;\n \tint i, ret;\n \tu16 nlw, cls, lnksta;\n \tu32 tmp;\n@@ -488,23 +599,22 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t\t\tMISC_CTRL_CFG_READ_UR_MODE_MASK |\n \t\t\tMISC_CTRL_MAX_BURST_SIZE_128);\n \n-\tpci_get_dma_regions(dev, ®ion, 0);\n-\trc_bar2_offset = region.bus_start - region.phys_start;\n-\trc_bar2_size = 1ULL << fls64(region.size - 1);\n-\n-\ttmp = lower_32_bits(rc_bar2_offset);\n-\tu32p_replace_bits(&tmp, brcm_pcie_encode_ibar_size(rc_bar2_size),\n-\t\t\t RC_BAR2_CONFIG_LO_SIZE_MASK);\n-\twritel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);\n-\twritel(upper_32_bits(rc_bar2_offset),\n-\t base + PCIE_MISC_RC_BAR2_CONFIG_HI);\n-\n-\tscb_size_val = rc_bar2_size ?\n-\t\t ilog2(rc_bar2_size) - 15 : 0xf; /* 0xf is 1GB */\n-\n \ttmp = readl(base + PCIE_MISC_MISC_CTRL);\n-\tu32p_replace_bits(&tmp, scb_size_val,\n-\t\t\t MISC_CTRL_SCB0_SIZE_MASK);\n+\tif (pcie->pcie_cfg->type == BCM2712) {\n+\t\t/* BCM2712: fixed 32GB SCB0 window */\n+\t\tu32p_replace_bits(&tmp, 20, MISC_CTRL_SCB0_SIZE_MASK);\n+\t} else {\n+\t\t/* Pre-BCM2712: size SCB0 to match the actual DMA region.\n+\t\t * rc_bar2_size must be a power of two; ilog2(size) - 15\n+\t\t * gives the hardware encoding (e.g. 1GB -> 15). */\n+\t\tstruct pci_region region;\n+\t\tu64 rc_bar2_size;\n+\n+\t\tpci_get_dma_regions(dev, ®ion, 0);\n+\t\trc_bar2_size = brcm_ibar_round_size(region.size);\n+\t\tu32p_replace_bits(&tmp, rc_bar2_size ? ilog2(rc_bar2_size) - 15 : 0xf,\n+\t\t\t\t MISC_CTRL_SCB0_SIZE_MASK);\n+\t}\n \twritel(tmp, base + PCIE_MISC_MISC_CTRL);\n \n \t/* Disable the PCIe->GISB memory window (RC_BAR1) */\n@@ -521,6 +631,8 @@ static int brcm_pcie_probe(struct udevice *dev)\n \t/* Clear any interrupts we find on boot */\n \twritel(0xffffffff, base + PCIE_MSI_INTR2_CLR);\n \n+\tbrcm_pcie_set_inbound_windows(dev);\n+\n \tif (pcie->gen)\n \t\tbrcm_pcie_set_gen(pcie, pcie->gen);\n \n", "prefixes": [ "v2", "8/9" ] }