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GET /api/1.1/patches/2229734/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2229734,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229734/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163918.C5D4268C4E@verein.lst.de/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null
    },
    "msgid": "<20260428163918.C5D4268C4E@verein.lst.de>",
    "date": "2026-04-28T16:39:18",
    "name": "[v2,1/9] ARM: bcm283x: Add bcm2712 PCIe memory window",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "5de9309b23ecca0c3990e7050e146d332478ff6a",
    "submitter": {
        "id": 2722,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/2722/?format=api",
        "name": "Torsten Duwe",
        "email": "duwe@lst.de"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260428163918.C5D4268C4E@verein.lst.de/mbox/",
    "series": [
        {
            "id": 501902,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501902/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501902",
            "date": "2026-04-28T16:23:19",
            "name": "ARM: RPi5: Enable PCIe",
            "version": 2,
            "mbox": "http://patchwork.ozlabs.org/series/501902/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2229734/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2229734/checks/",
    "tags": {},
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
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        ],
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            "by phobos.denx.de (Postfix, from userid 109)\n id 65D5F845D8; Tue, 28 Apr 2026 18:39:24 +0200 (CEST)",
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            "by verein.lst.de (Postfix, from userid 2005)\n id C5D4268C4E; Tue, 28 Apr 2026 18:39:18 +0200 (CEST)"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
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        "Subject": "[PATCH v2 1/9] ARM: bcm283x: Add bcm2712 PCIe memory window",
        "To": "Peter Robinson <pbrobinson@gmail.com>,\n Matthias Brugger <mbrugger@suse.com>",
        "Cc": "=?unknown-8bit?q?Tom_Rini_=3Ctrini=40konsulko=2Ecom=3E=2C=22Jan_=C4=8Cer?=\n\t=?unknown-8bit?q?m=C3=A1k=22_=3Csairon=40sairon=2Ecz=3E=2CAndrea_della_Port?=\n\t=?unknown-8bit?q?a_=3Candrea=2Eporta=40suse=2Ecom=3E=2C=22Ivan_T=2E_Ivanov?=\n\t=?unknown-8bit?q?=22_=3Ciivanov=40suse=2Ede=3E=2C_Stanimir_Varbanov_=3Cstan?=\n\t=?unknown-8bit?q?imir=2Evarbanov=40suse=2Ecom=3E=2C_Oleksii_Moisieiev_=3COl?=\n\t=?unknown-8bit?q?eksii=5FMoisieiev=40epam=2Ecom=3E=2C_Volodymyr_Babchuk_=3C?=\n\t=?unknown-8bit?q?volodymyr=5Fbabchuk=40epam=2Ecom=3E=2C_Marek_Vasut_=3Cmare?=\n\t=?unknown-8bit?q?k=2Evasut+renesas=40mailbox=2Eorg=3E=2CPaul_Barker_=3Cpaul?=\n\t=?unknown-8bit?q?=2Ebarker=2Ect=40bp=2Erenesas=2Ecom=3E=2CPatrice_Chotard_?=\n\t=?unknown-8bit?q?=3Cpatrice=2Echotard=40foss=2Est=2Ecom=3E=2CChristian_Mara?=\n\t=?unknown-8bit?q?ngi_=3Cansuelsmth=40gmail=2Ecom=3E=2CPatrick_Delaunay_=3Cp?=\n\t=?unknown-8bit?q?atrick=2Edelaunay=40foss=2Est=2Ecom=3E=2CHuan_Zhou_=3Cme?=\n\t=?unknown-8bit?q?=40per1cycle=2Eorg=3E=2CGabriel_Fernandez_=3Cgabriel=2Efer?=\n\t=?unknown-8bit?q?nandez=40foss=2Est=2Ecom=3E=2CKever_Yang_=3Ckever=2Eyang?=\n\t=?unknown-8bit?q?=40rock-chips=2Ecom=3E=2CJonas_Karlman_=3Cjonas=40kwiboo?=\n\t=?unknown-8bit?q?=2Ese=3E=2CJoseph_Chen_=3Cchenjh=40rock-chips=2Ecom=3E=2CE?=\n\t=?unknown-8bit?q?laine_Zhang_=3Czhangqing=40rock-chips=2Ecom=3E=2C_Pedro_Fa?=\n\t=?unknown-8bit?q?lcato_=3Cpfalcato=40suse=2Ede=3E=2Cu-boot=40lists=2Edenx?=\n\t=?unknown-8bit?q?=2Ede?=",
        "In-Reply-To": "<20260428162319.99B4268B05@verein.lst.de>",
        "Message-Id": "<20260428163918.C5D4268C4E@verein.lst.de>",
        "Date": "Tue, 28 Apr 2026 18:39:18 +0200 (CEST)",
        "From": "duwe@lst.de (Torsten Duwe)",
        "X-Mailman-Approved-At": "Tue, 28 Apr 2026 18:43:21 +0200",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.39",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
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        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "From: Torsten Duwe <duwe@suse.de>\n\nAdd a mapping region for the PCIe bus address spaces to the BCM2712\nmemory controller setup. Generously merging the PCIe address spaces\nworks sufficiently well for a boot loader.\n\nSigned-off-by: Torsten Duwe <duwe@suse.de>\nCo-authored-by: Oleksii Moisieiev <oleksii_moisieiev@epam.com>\nTested-by: Pedro Falcato <pfalcato@suse.de>\n---\n arch/arm/mach-bcm283x/init.c | 10 +++++++++-\n 1 file changed, 9 insertions(+), 1 deletion(-)",
    "diff": "diff --git a/arch/arm/mach-bcm283x/init.c b/arch/arm/mach-bcm283x/init.c\nindex 7a1de22e0ae..7a2faaa4de6 100644\n--- a/arch/arm/mach-bcm283x/init.c\n+++ b/arch/arm/mach-bcm283x/init.c\n@@ -18,7 +18,7 @@\n #ifdef CONFIG_ARM64\n #include <asm/armv8/mmu.h>\n \n-#define MEM_MAP_MAX_ENTRIES (4)\n+#define MEM_MAP_MAX_ENTRIES (5)\n \n static struct mm_region bcm283x_mem_map[MEM_MAP_MAX_ENTRIES] = {\n \t{\n@@ -83,6 +83,14 @@ static struct mm_region bcm2712_mem_map[MEM_MAP_MAX_ENTRIES] = {\n \t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t}, {\n+\t\t/* Whole PCIe section */\n+\t\t.virt = 0x1800000000UL,\n+\t\t.phys = 0x1800000000UL,\n+\t\t.size = 0x0800000000UL,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n \t}, {\n \t\t/* SoC bus */\n \t\t.virt = 0x107c000000UL,\n",
    "prefixes": [
        "v2",
        "1/9"
    ]
}