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GET /api/1.1/patches/2229693/?format=api
{ "id": 2229693, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229693/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-4-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428160103.3551125-4-jim.shu@sifive.com>", "date": "2026-04-28T16:01:02", "name": "[3/4] hw/intc: riscv_imsic: Add reset API to IMSIC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6050aadf3d74e4a9f66c77600533cbe870e54ece", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/1.1/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-4-jim.shu@sifive.com/mbox/", "series": [ { "id": 501889, "url": "http://patchwork.ozlabs.org/api/1.1/series/501889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501889", "date": "2026-04-28T16:01:00", "name": "Minor fixes and enhancements of RISC-V AIA devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501889/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229693/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229693/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=DO/m0Oqe;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x434.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Clearing IMSIC registers and qemu_irq in the reset function\n\nSigned-off-by: Jim Shu <jim.shu@sifive.com>\n---\n hw/intc/riscv_imsic.c | 19 +++++++++++++++++++\n 1 file changed, 19 insertions(+)", "diff": "diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c\nindex 7c9a0120335..ac59496c22b 100644\n--- a/hw/intc/riscv_imsic.c\n+++ b/hw/intc/riscv_imsic.c\n@@ -342,6 +342,23 @@ static const MemoryRegionOps riscv_imsic_ops = {\n }\n };\n \n+static void riscv_imsic_reset_enter(Object *obj, ResetType type)\n+{\n+ RISCVIMSICState *imsic = RISCV_IMSIC(obj);\n+ int i;\n+\n+ memset(imsic->eidelivery, 0, sizeof(uint32_t) * imsic->num_pages);\n+ memset(imsic->eithreshold, 0, sizeof(uint32_t) * imsic->num_pages);\n+\n+ for (i = 0; i < imsic->num_eistate; i++) {\n+ imsic->eistate[i] &= ~IMSIC_EISTATE_ENABLED;\n+ }\n+\n+ for (i = 0; i < imsic->num_pages; i++) {\n+ qemu_irq_lower(imsic->external_irqs[i]);\n+ }\n+}\n+\n static void riscv_imsic_realize(DeviceState *dev, Error **errp)\n {\n RISCVIMSICState *imsic = RISCV_IMSIC(dev);\n@@ -425,9 +442,11 @@ static const VMStateDescription vmstate_riscv_imsic = {\n static void riscv_imsic_class_init(ObjectClass *klass, const void *data)\n {\n DeviceClass *dc = DEVICE_CLASS(klass);\n+ ResettableClass *rc = RESETTABLE_CLASS(klass);\n \n device_class_set_props(dc, riscv_imsic_properties);\n dc->realize = riscv_imsic_realize;\n+ rc->phases.enter = riscv_imsic_reset_enter;\n dc->vmsd = &vmstate_riscv_imsic;\n }\n \n", "prefixes": [ "3/4" ] }