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GET /api/1.1/patches/2229690/?format=api
{ "id": 2229690, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229690/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-5-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428160103.3551125-5-jim.shu@sifive.com>", "date": "2026-04-28T16:01:03", "name": "[4/4] hw/intc: riscv_aplic: add trace events of APLIC read/write function", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ef989ab025e8aebd920e3a9950caeccf04fd9f4d", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/1.1/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-5-jim.shu@sifive.com/mbox/", "series": [ { "id": 501889, "url": "http://patchwork.ozlabs.org/api/1.1/series/501889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501889", "date": "2026-04-28T16:01:00", "name": "Minor fixes and enhancements of RISC-V AIA devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501889/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229690/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229690/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=I6cf0xLZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x42f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add the trace events for APLIC read/write functions.\n\nSigned-off-by: Jim Shu <jim.shu@sifive.com>\n---\n hw/intc/riscv_aplic.c | 63 ++++++++++++++++++++++++++-----------------\n hw/intc/trace-events | 4 +++\n 2 files changed, 42 insertions(+), 25 deletions(-)", "diff": "diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c\nindex a04e0e1a898..55515d1a085 100644\n--- a/hw/intc/riscv_aplic.c\n+++ b/hw/intc/riscv_aplic.c\n@@ -35,6 +35,7 @@\n #include \"system/tcg.h\"\n #include \"kvm/kvm_riscv.h\"\n #include \"migration/vmstate.h\"\n+#include \"trace.h\"\n \n #define APLIC_MAX_IDC (1UL << 14)\n #define APLIC_MAX_SOURCE 1024\n@@ -626,6 +627,7 @@ static void riscv_aplic_request(void *opaque, int irq, int level)\n static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)\n {\n uint32_t irq, word, idc;\n+ uint64_t val;\n RISCVAPLICState *aplic = opaque;\n \n /* Reads must be 4 byte words */\n@@ -634,18 +636,18 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)\n }\n \n if (addr == APLIC_DOMAINCFG) {\n- return APLIC_DOMAINCFG_RDONLY | aplic->domaincfg |\n- (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);\n+ val = APLIC_DOMAINCFG_RDONLY | aplic->domaincfg |\n+ (aplic->msimode ? APLIC_DOMAINCFG_DM : 0);\n } else if ((APLIC_SOURCECFG_BASE <= addr) &&\n (addr < (APLIC_SOURCECFG_BASE + (aplic->num_irqs - 1) * 4))) {\n irq = ((addr - APLIC_SOURCECFG_BASE) >> 2) + 1;\n- return aplic->sourcecfg[irq];\n+ val = aplic->sourcecfg[irq];\n } else if (aplic->mmode && aplic->msimode &&\n (addr == APLIC_MMSICFGADDR)) {\n- return aplic->mmsicfgaddr;\n+ val = aplic->mmsicfgaddr;\n } else if (aplic->mmode && aplic->msimode &&\n (addr == APLIC_MMSICFGADDRH)) {\n- return aplic->mmsicfgaddrH;\n+ val = aplic->mmsicfgaddrH;\n } else if (aplic->mmode && aplic->msimode &&\n (addr == APLIC_SMSICFGADDR)) {\n /*\n@@ -657,65 +659,74 @@ static uint64_t riscv_aplic_read(void *opaque, hwaddr addr, unsigned size)\n * only zero in at least one of the supervisor-level child\n * domains).\n */\n- return (aplic->num_children) ? aplic->smsicfgaddr : 0;\n+ val = (aplic->num_children) ? aplic->smsicfgaddr : 0;\n } else if (aplic->mmode && aplic->msimode &&\n (addr == APLIC_SMSICFGADDRH)) {\n- return (aplic->num_children) ? aplic->smsicfgaddrH : 0;\n+ val = (aplic->num_children) ? aplic->smsicfgaddrH : 0;\n } else if ((APLIC_SETIP_BASE <= addr) &&\n (addr < (APLIC_SETIP_BASE + aplic->bitfield_words * 4))) {\n word = (addr - APLIC_SETIP_BASE) >> 2;\n- return riscv_aplic_read_pending_word(aplic, word);\n+ val = riscv_aplic_read_pending_word(aplic, word);\n } else if (addr == APLIC_SETIPNUM) {\n- return 0;\n+ val = 0;\n } else if ((APLIC_CLRIP_BASE <= addr) &&\n (addr < (APLIC_CLRIP_BASE + aplic->bitfield_words * 4))) {\n word = (addr - APLIC_CLRIP_BASE) >> 2;\n- return riscv_aplic_read_input_word(aplic, word);\n+ val = riscv_aplic_read_input_word(aplic, word);\n } else if (addr == APLIC_CLRIPNUM) {\n- return 0;\n+ val = 0;\n } else if ((APLIC_SETIE_BASE <= addr) &&\n (addr < (APLIC_SETIE_BASE + aplic->bitfield_words * 4))) {\n word = (addr - APLIC_SETIE_BASE) >> 2;\n- return riscv_aplic_read_enabled_word(aplic, word);\n+ val = riscv_aplic_read_enabled_word(aplic, word);\n } else if (addr == APLIC_SETIENUM) {\n- return 0;\n+ val = 0;\n } else if ((APLIC_CLRIE_BASE <= addr) &&\n (addr < (APLIC_CLRIE_BASE + aplic->bitfield_words * 4))) {\n- return 0;\n+ val = 0;\n } else if (addr == APLIC_CLRIENUM) {\n- return 0;\n+ val = 0;\n } else if (addr == APLIC_SETIPNUM_LE) {\n- return 0;\n+ val = 0;\n } else if (addr == APLIC_SETIPNUM_BE) {\n- return 0;\n+ val = 0;\n } else if (addr == APLIC_GENMSI) {\n- return (aplic->msimode) ? aplic->genmsi : 0;\n+ val = (aplic->msimode) ? aplic->genmsi : 0;\n } else if ((APLIC_TARGET_BASE <= addr) &&\n (addr < (APLIC_TARGET_BASE + (aplic->num_irqs - 1) * 4))) {\n irq = ((addr - APLIC_TARGET_BASE) >> 2) + 1;\n if (!riscv_aplic_source_active(aplic, irq)) {\n- return 0;\n+ val = 0;\n+ } else {\n+ val = aplic->target[irq];\n }\n- return aplic->target[irq];\n } else if (!aplic->msimode && (APLIC_IDC_BASE <= addr) &&\n (addr < (APLIC_IDC_BASE + aplic->num_harts * APLIC_IDC_SIZE))) {\n idc = (addr - APLIC_IDC_BASE) / APLIC_IDC_SIZE;\n switch (addr - (APLIC_IDC_BASE + idc * APLIC_IDC_SIZE)) {\n case APLIC_IDC_IDELIVERY:\n- return aplic->idelivery[idc];\n+ val = aplic->idelivery[idc];\n+ break;\n case APLIC_IDC_IFORCE:\n- return aplic->iforce[idc];\n+ val = aplic->iforce[idc];\n+ break;\n case APLIC_IDC_ITHRESHOLD:\n- return aplic->ithreshold[idc];\n+ val = aplic->ithreshold[idc];\n+ break;\n case APLIC_IDC_TOPI:\n- return riscv_aplic_idc_topi(aplic, idc);\n+ val = riscv_aplic_idc_topi(aplic, idc);\n+ break;\n case APLIC_IDC_CLAIMI:\n- return riscv_aplic_idc_claimi(aplic, idc);\n+ val = riscv_aplic_idc_claimi(aplic, idc);\n+ break;\n default:\n goto err;\n };\n }\n \n+ trace_riscv_aplic_read(addr, size, val);\n+ return val;\n+\n err:\n qemu_log_mask(LOG_GUEST_ERROR,\n \"%s: Invalid register read 0x%\" HWADDR_PRIx \"\\n\",\n@@ -734,6 +745,8 @@ static void riscv_aplic_write(void *opaque, hwaddr addr, uint64_t value,\n goto err;\n }\n \n+ trace_riscv_aplic_write(addr, size, value);\n+\n if (addr == APLIC_DOMAINCFG) {\n /* Only IE bit writable at the moment */\n value &= APLIC_DOMAINCFG_IE;\ndiff --git a/hw/intc/trace-events b/hw/intc/trace-events\nindex 018c609ca5e..36ea75049ab 100644\n--- a/hw/intc/trace-events\n+++ b/hw/intc/trace-events\n@@ -330,3 +330,7 @@ loongarch_msi_set_irq(int irq_num) \"set msi irq %d\"\n loongarch_extioi_setirq(int irq, int level) \"set extirq irq %d level %d\"\n loongarch_extioi_readw(uint64_t addr, uint64_t val) \"addr: 0x%\"PRIx64 \"val: 0x%\" PRIx64\n loongarch_extioi_writew(uint64_t addr, uint64_t val) \"addr: 0x%\"PRIx64 \"val: 0x%\" PRIx64\n+\n+# riscv_aplic.c\n+riscv_aplic_read(uint64_t offset, unsigned size, uint64_t value) \"offset: 0x%\" PRIx64 \", size: %u, value: 0x%\" PRIx64\n+riscv_aplic_write(uint64_t offset, unsigned size, uint64_t value) \"offset: 0x%\" PRIx64 \", size: %u, value: 0x%\" PRIx64\n", "prefixes": [ "4/4" ] }