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GET /api/1.1/patches/2229688/?format=api
{ "id": 2229688, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229688/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-2-jim.shu@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.1/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "" }, "msgid": "<20260428160103.3551125-2-jim.shu@sifive.com>", "date": "2026-04-28T16:01:00", "name": "[1/4] hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "307c8265bc8a7b90089507e479bf7bfb67b374be", "submitter": { "id": 83153, "url": "http://patchwork.ozlabs.org/api/1.1/people/83153/?format=api", "name": "Jim Shu", "email": "jim.shu@sifive.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260428160103.3551125-2-jim.shu@sifive.com/mbox/", "series": [ { "id": 501889, "url": "http://patchwork.ozlabs.org/api/1.1/series/501889/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=501889", "date": "2026-04-28T16:01:00", "name": "Minor fixes and enhancements of RISC-V AIA devices", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501889/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229688/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229688/checks/", "tags": {}, "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=ZXIVJ875;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pf1-x42d.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "According to the AIA spec ch4.7 (\"Precise effects on interrupt-pending\nbits\"), pending bit of APLIC should be set/cleared whenever the\nrectified input value is high/low in the both level-trigger mode\nand direct delivery mode.\n\nCurrently, QEMU APLIC only clears the pending bit when interrupt is\nclaimed in APLIC, but not clears it when the rectified input value is\nlow. (e.g. IRQ source signal is low in the LEVEL_HIGH/Level1 mode).\nThe software may receive an additional IRQ if the peripheral\ntriggers one after the software clears the APLIC IRQ but before it\nclears the peripheral's IRQ.\n\nThus, we also clear the pending bit via the rectified input value in the\nlevel-trigger mode.\n\nThis change doesn't affect MSI delivery mode. Calling\nriscv_aplic_msi_irq_update() when IRQ pending is low will do nothing.\n\nSigned-off-by: Jim Shu <jim.shu@sifive.com>\n---\n hw/intc/riscv_aplic.c | 8 ++++----\n 1 file changed, 4 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c\nindex 8f700431114..791e0b01b96 100644\n--- a/hw/intc/riscv_aplic.c\n+++ b/hw/intc/riscv_aplic.c\n@@ -591,14 +591,14 @@ static void riscv_aplic_request(void *opaque, int irq, int level)\n }\n break;\n case APLIC_SOURCECFG_SM_LEVEL_HIGH:\n- if ((level > 0) && !(state & APLIC_ISTATE_PENDING)) {\n- riscv_aplic_set_pending_raw(aplic, irq, true);\n+ if ((level > 0) != !!(state & APLIC_ISTATE_PENDING)) {\n+ riscv_aplic_set_pending_raw(aplic, irq, level > 0);\n update = true;\n }\n break;\n case APLIC_SOURCECFG_SM_LEVEL_LOW:\n- if ((level <= 0) && !(state & APLIC_ISTATE_PENDING)) {\n- riscv_aplic_set_pending_raw(aplic, irq, true);\n+ if ((level <= 0) != !!(state & APLIC_ISTATE_PENDING)) {\n+ riscv_aplic_set_pending_raw(aplic, irq, level <= 0);\n update = true;\n }\n break;\n", "prefixes": [ "1/4" ] }