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GET /api/1.1/patches/2229558/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 2229558,
    "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229558/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-8-fangyu.yu@linux.alibaba.com/",
    "project": {
        "id": 70,
        "url": "http://patchwork.ozlabs.org/api/1.1/projects/70/?format=api",
        "name": "Linux KVM RISC-V",
        "link_name": "kvm-riscv",
        "list_id": "kvm-riscv.lists.infradead.org",
        "list_email": "kvm-riscv@lists.infradead.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": ""
    },
    "msgid": "<20260428131359.34872-8-fangyu.yu@linux.alibaba.com>",
    "date": "2026-04-28T13:13:55",
    "name": "[RFC,07/11] iommupt: Don't preset D when RISC-V IOMMU dirty tracking on",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "ca12854eb2a9b80bd711b41cb77f11a50c827702",
    "submitter": {
        "id": 91416,
        "url": "http://patchwork.ozlabs.org/api/1.1/people/91416/?format=api",
        "name": null,
        "email": "fangyu.yu@linux.alibaba.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/kvm-riscv/patch/20260428131359.34872-8-fangyu.yu@linux.alibaba.com/mbox/",
    "series": [
        {
            "id": 501850,
            "url": "http://patchwork.ozlabs.org/api/1.1/series/501850/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/kvm-riscv/list/?series=501850",
            "date": "2026-04-28T13:13:48",
            "name": "iommu/riscv: Add hardware dirty tracking for second-stage domains",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/501850/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2229558/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2229558/checks/",
    "tags": {},
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        ],
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        "From": "fangyu.yu@linux.alibaba.com",
        "To": "joro@8bytes.org,\n\twill@kernel.org,\n\trobin.murphy@arm.com,\n\tpjw@kernel.org,\n\tpalmer@dabbelt.com,\n\taou@eecs.berkeley.edu,\n\talex@ghiti.fr,\n\ttjeznach@rivosinc.com,\n\tjgg@ziepe.ca,\n\tkevin.tian@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tvasant.hegde@amd.com,\n\tanup@brainfault.org,\n\tatish.patra@linux.dev,\n\tskhawaja@google.com,\n\tjgg@nvidia.com",
        "Cc": "guoren@kernel.org,\n\tkvm@vger.kernel.org,\n\tiommu@lists.linux.dev,\n\tkvm-riscv@lists.infradead.org,\n\tlinux-riscv@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org,\n\tFangyu Yu <fangyu.yu@linux.alibaba.com>",
        "Subject": "[RFC PATCH 07/11] iommupt: Don't preset D when RISC-V IOMMU dirty\n tracking on",
        "Date": "Tue, 28 Apr 2026 21:13:55 +0800",
        "Message-Id": "<20260428131359.34872-8-fangyu.yu@linux.alibaba.com>",
        "X-Mailer": "git-send-email 2.39.3 (Apple Git-146)",
        "In-Reply-To": "<20260428131359.34872-1-fangyu.yu@linux.alibaba.com>",
        "References": "<20260428131359.34872-1-fangyu.yu@linux.alibaba.com>",
        "MIME-Version": "1.0",
        "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ",
        "X-CRM114-CacheID": "sfid-20260428_061434_732124_1B95B3A7 ",
        "X-CRM114-Status": "GOOD (  10.70  )",
        "X-Spam-Score": "-17.6 (-----------------)",
        "X-Spam-Report": "Spam detection software,\n running on the system \"bombadil.infradead.org\",\n has NOT identified this incoming email as spam.  The original\n message has been attached to this so you can view it or label\n similar future email.  If you have any questions, see\n the administrator of that system for details.\n Content preview:  From: Fangyu Yu <fangyu.yu@linux.alibaba.com> When mapping\n    writable pages,\n the RISC-V format code currently pre-sets the PTE D bit unconditionally.\n    If hardware dirty tracking is active (DC.tc.GADE set),\n the IOMMU sets D autonomously\n    on the first write. Pre-setting D makes every new mapping appear dirty\n immediately\n    and breaks dirty tracking.\n Content analysis details:   (-17.6 points, 5.0 required)\n  pts rule name              description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE     RBL: Sender listed at https://www.dnswl.org/, no\n                             trust\n                             [115.124.30.110 listed in list.dnswl.org]\n -7.5 USER_IN_DEF_SPF_WL     From: address is in the default SPF welcome-list\n  0.0 SPF_HELO_NONE          SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS               SPF: sender matches SPF record\n -7.5 USER_IN_DEF_DKIM_WL    From: address is in the default DKIM welcome-list\n -0.1 DKIM_VALID_EF          Message has a valid DKIM or DK signature from\n                             envelope-from domain\n  0.1 DKIM_SIGNED            Message has a DKIM or DK signature,\n not necessarily valid\n -0.1 DKIM_VALID             Message has at least one valid DKIM or DK\n signature\n -0.1 DKIM_VALID_AU          Message has a valid DKIM or DK signature from\n author's\n                             domain\n -1.9 BAYES_00               BODY: Bayes spam probability is 0 to 1%\n                             [score: 0.0000]\n  0.0 UNPARSEABLE_RELAY      Informational: message has unparseable relay\n lines\n -0.5 ENV_AND_HDR_SPF_MATCH  Env and Hdr From used in default SPF WL Match",
        "X-BeenThere": "kvm-riscv@lists.infradead.org",
        "X-Mailman-Version": "2.1.34",
        "Precedence": "list",
        "List-Id": "<kvm-riscv.lists.infradead.org>",
        "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=unsubscribe>",
        "List-Archive": "<http://lists.infradead.org/pipermail/kvm-riscv/>",
        "List-Post": "<mailto:kvm-riscv@lists.infradead.org>",
        "List-Help": "<mailto:kvm-riscv-request@lists.infradead.org?subject=help>",
        "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/kvm-riscv>,\n <mailto:kvm-riscv-request@lists.infradead.org?subject=subscribe>",
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        "Content-Transfer-Encoding": "7bit",
        "Sender": "\"kvm-riscv\" <kvm-riscv-bounces@lists.infradead.org>",
        "Errors-To": "kvm-riscv-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org"
    },
    "content": "From: Fangyu Yu <fangyu.yu@linux.alibaba.com>\n\nWhen mapping writable pages, the RISC-V format code currently\npre-sets the PTE D bit unconditionally.\n\nIf hardware dirty tracking is active (DC.tc.GADE set), the IOMMU\nsets D autonomously on the first write. Pre-setting D makes every\nnew mapping appear dirty immediately and breaks dirty tracking.\n\nIntroduce PT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE and, when set, leave\nD cleared for new writable mappings so hardware can capture the\nfirst write. Keep pre-setting D when dirty tracking is inactive.\n\nOnly meaningful for second-stage (iohgatp) page tables.\n\nSigned-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>\n---\n drivers/iommu/generic_pt/fmt/riscv.h | 13 +++++++++++--\n include/linux/generic_pt/common.h    |  8 ++++++++\n 2 files changed, 19 insertions(+), 2 deletions(-)",
    "diff": "diff --git a/drivers/iommu/generic_pt/fmt/riscv.h b/drivers/iommu/generic_pt/fmt/riscv.h\nindex 4fe645e60375..0281356cfaf6 100644\n--- a/drivers/iommu/generic_pt/fmt/riscv.h\n+++ b/drivers/iommu/generic_pt/fmt/riscv.h\n@@ -248,8 +248,17 @@ static inline int riscvpt_iommu_set_prot(struct pt_common *common,\n \tu64 pte;\n \n \tpte = RISCVPT_A | RISCVPT_U;\n-\tif (iommu_prot & IOMMU_WRITE)\n-\t\tpte |= RISCVPT_W | RISCVPT_R | RISCVPT_D;\n+\tif (iommu_prot & IOMMU_WRITE) {\n+\t\tpte |= RISCVPT_W | RISCVPT_R;\n+\t\t/*\n+\t\t * When hardware dirty tracking is active (GADE set), the IOMMU\n+\t\t * sets the D bit autonomously on the first write access.\n+\t\t *\n+\t\t */\n+\t\tif (!(common->features &\n+\t\t      BIT(PT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE)))\n+\t\t\tpte |= RISCVPT_D;\n+\t}\n \tif (iommu_prot & IOMMU_READ)\n \t\tpte |= RISCVPT_R;\n \tif (!(iommu_prot & IOMMU_NOEXEC))\ndiff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h\nindex e82dff33ece8..4606c7464c27 100644\n--- a/include/linux/generic_pt/common.h\n+++ b/include/linux/generic_pt/common.h\n@@ -193,6 +193,14 @@ enum {\n \t * Support the 64k contiguous page size following the Svnapot extension.\n \t */\n \tPT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START,\n+\t/*\n+\t * Hardware dirty tracking is currently active: DC.tc.GADE is set and\n+\t * the IOMMU will set the D bit in PTEs autonomously on write access.\n+\t * When this flag is set, new mappings must not pre-set the D bit so\n+\t * that every write is correctly captured by hardware.\n+\t * Only meaningful for second-stage (iohgatp) page tables.\n+\t */\n+\tPT_FEAT_RISCV_DIRTY_TRACKING_ACTIVE,\n \n };\n \n",
    "prefixes": [
        "RFC",
        "07/11"
    ]
}