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GET /api/1.1/patches/2229471/?format=api
{ "id": 2229471, "url": "http://patchwork.ozlabs.org/api/1.1/patches/2229471/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/3ac593a8c6893151f6f86eafcc4b9b3e3f9f1ebf.1777368885.git.weijie.gao@mediatek.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.1/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null }, "msgid": "<3ac593a8c6893151f6f86eafcc4b9b3e3f9f1ebf.1777368885.git.weijie.gao@mediatek.com>", "date": "2026-04-28T09:39:33", "name": "[v2,6/7] mtd: spi-nor-ids: Reorder winbond parts with part families", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "447e23ed21ae6c1dfb7b6477386627031e08138f", "submitter": { "id": 75269, "url": "http://patchwork.ozlabs.org/api/1.1/people/75269/?format=api", "name": "Weijie Gao", "email": "weijie.gao@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/3ac593a8c6893151f6f86eafcc4b9b3e3f9f1ebf.1777368885.git.weijie.gao@mediatek.com/mbox/", "series": [ { "id": 501807, "url": "http://patchwork.ozlabs.org/api/1.1/series/501807/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=501807", "date": "2026-04-28T09:39:06", "name": "Fix and add some spi-nor flash parts (v2)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/501807/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2229471/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2229471/checks/", "tags": {}, "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256\n header.s=dk header.b=hT56ssQx;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=mediatek.com;\n s=dk;\n h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;\n bh=UPsLkD0178b1SFjrnQbf4fBEefwxUzhGQJ1wCOK7MAk=;\n b=hT56ssQxlqKlCAJVLJbp0i1qo+YC1eN5TyWvrp3LuT/ZDt03pGEx877/WJh2kW8pFDE4eKkhJA7BK3dgp2vh08tzJQ7NdbWsZsjHPSdCfnFlSTd6iIBJf7i89vjBQneGGmIWkFc+QGKR86uCbf58mYWCKCQpBwdjHnjun/ng6UI=;", "X-CID-P-RULE": "Release_Ham", "X-CID-O-INFO": "VERSION:1.3.12, REQID:4c771894-ac11-4694-85ec-fba36f97993d,\n IP:0,\n U\n RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO\n N:release,TS:-25", "X-CID-META": "VersionHash:e7bac3a, CLOUDID:c9a0cc44-8360-4d24-8500-9b9380fa4b0d,\n B\n ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102|836|865|888|898,TC:-5,Cont\n ent:0|15|50,EDM:-3,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL:0\n ,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0", "X-CID-BVR": "2,SSN|SDN", "X-CID-BAS": "2,SSN|SDN,0,_", "X-CID-FACTOR": "TF_CID_SPAM_SNR", "X-CID-RHF": "D41D8CD98F00B204E9800998ECF8427E", "From": "Weijie Gao <weijie.gao@mediatek.com>", "To": "<u-boot@lists.denx.de>", "CC": "GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>, Tom Rini\n <trini@konsulko.com>, Vignesh R <vigneshr@ti.com>, Takahiro Kuwano\n <takahiro.kuwano@infineon.com>, Marek Vasut\n <marek.vasut+renesas@mailbox.org>, Tudor Ambarus <tudor.ambarus@linaro.org>,\n Jeffrey Yu <jeyu@issi.com>, Christoph Reiter <christoph.reiter@evk.biz>,\n Miquel Raynal <miquel.raynal@bootlin.com>, Shiji Yang\n <yangshiji66@outlook.com>, Bernhard Messerklinger\n <bernhard.messerklinger@at.abb.com>, Vaishnav Achath <vaishnav.a@ti.com>,\n Prasad Kummari <prasad.kummari@amd.com>, Weijie Gao <weijie.gao@mediatek.com>", "Subject": "[PATCH v2 6/7] mtd: spi-nor-ids: Reorder winbond parts with part\n families", "Date": "Tue, 28 Apr 2026 17:39:33 +0800", "Message-ID": "\n <3ac593a8c6893151f6f86eafcc4b9b3e3f9f1ebf.1777368885.git.weijie.gao@mediatek.com>", "X-Mailer": "git-send-email 2.17.0", "In-Reply-To": "<cover.1777368885.git.weijie.gao@mediatek.com>", "References": "<cover.1777368885.git.weijie.gao@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This patch reorders winbond parts with families (0xef20xx, 0xef30xx, ...).\nAlso, parts in the same family are sorted by size.\nSome parts are renamed to match their families.\n\nRenamed parts:\n\n1. Removed suffixes due to multiple suffixes matches with the same ID:\nw25q80bl -> w25q80\nw25q16cl -> w25q16\nw25q64cv -> w25q64\n\n2. Add suffix to match their family:\nw25q80 -> w25q80bw\nw25q01jv -> w25q01jv-q\nw25q256jw -> w25q256jw-q\nw25q16jv -> w25q16jv-m\nw25q32jv -> w25q32jv-m\nw25q128jv -> w25q128jv-m\nw25q02jv -> w25q02jv-m\nw25q128jw -> w25q128jw-m\n\n3. Change to uniform suffix:\nw25q01nw-iq -> w25q01nw-q\nw25q01jvfim -> w25q01jv-m\nw25q01nw-im -> w25q01nw-m\nw25q02nw-im -> w25q02nw-m\n\nSigned-off-by: Weijie Gao <weijie.gao@mediatek.com>\n---\nv2: new\n---\n drivers/mtd/spi/spi-nor-ids.c | 157 +++++++++++-----------------------\n 1 file changed, 50 insertions(+), 107 deletions(-)", "diff": "diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c\nindex 492411a90f5..befe6d69e0b 100644\n--- a/drivers/mtd/spi/spi-nor-ids.c\n+++ b/drivers/mtd/spi/spi-nor-ids.c\n@@ -551,123 +551,66 @@ const struct flash_info spi_nor_ids[] = {\n \t{ INFO(\"w25x40\", 0xef3013, 0, 64 * 1024, 8, SECT_4K) },\n \t{ INFO(\"w25x16\", 0xef3015, 0, 64 * 1024, 32, SECT_4K) },\n \t{ INFO(\"w25x32\", 0xef3016, 0, 64 * 1024, 64, SECT_4K) },\n-\t{ INFO(\"w25q20cl\", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },\n-\t{ INFO(\"w25q20bw\", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },\n-\t{ INFO(\"w25q20ew\", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },\n-\t{\n-\t\tINFO(\"w25q16dw\", 0xef6015, 0, 64 * 1024, 32,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q32dw\", 0xef6016, 0, 64 * 1024, 64,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q16jv\", 0xef7015, 0, 64 * 1024, 32,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)\n-\t},\n-\t{\n-\t\tINFO(\"w25q32jv\", 0xef7016, 0, 64 * 1024, 64,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q32jwm\", 0xef8016, 0, 64 * 1024, 64,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q256jwm\", 0xef8019, 0, 64 * 1024, 512,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n \t{ INFO(\"w25x64\", 0xef3017, 0, 64 * 1024, 128, SECT_4K) },\n-\t{\n-\t\tINFO(\"w25q64dw\", 0xef6017, 0, 64 * 1024, 128,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q64jv\", 0xef7017, 0, 64 * 1024, 128,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q128fw\", 0xef6018, 0, 64 * 1024, 256,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q128jv\", 0xef7018, 0, 64 * 1024, 256,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q128jw\", 0xef8018, 0, 64 * 1024, 256,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q256jw\", 0xef6019, 0, 64 * 1024, 512,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q512nwq\", 0xef6020, 0, 64 * 1024, 1024,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q512nwm\", 0xef8020, 0, 64 * 1024, 1024,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q512jvq\", 0xef4020, 0, 64 * 1024, 1024,\n-\t\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q01jv\", 0xef4021, 0, 64 * 1024, 2048,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q01jvfim\", 0xef7021, 0, 64 * 1024, 2048,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{\n-\t\tINFO(\"w25q02jv\", 0xef7022, 0, 64 * 1024, 4096,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n-\t{ INFO(\"w25q80\", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },\n-\t{ INFO(\"w25q80bl\", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{\n-\t\tINFO(\"w25q16cl\", 0xef4015, 0, 64 * 1024, 32,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n+\t{ INFO(\"w25q20cl\", 0xef4012, 0, 64 * 1024, 4, SECT_4K) },\n+\t{ INFO(\"w25q80\", 0xef4014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q16\", 0xef4015, 0, 64 * 1024, 32,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ INFO(\"w25q32\", 0xef4016, 0, 64 * 1024, 64, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{ INFO(\"w25q64cv\", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q64\", 0xef4017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25q128\", 0xef4018, 0, 64 * 1024, 256,\n-\t\t\tSECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |\n-\t\t\tSPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)\n-\t},\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ INFO(\"w25q256\", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q512jv-q\", 0xef4020, 0, 64 * 1024, 1024,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q01jv-q\", 0xef4021, 0, 64 * 1024, 2048,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q20bw\", 0xef5012, 0, 64 * 1024, 4, SECT_4K) },\n+\t{ INFO(\"w25q80bw\", 0xef5014, 0, 64 * 1024, 16, SECT_4K) },\n+\t{ INFO(\"w25q20ew\", 0xef6012, 0, 64 * 1024, 4, SECT_4K) },\n+\t{ INFO(\"w25q16dw\", 0xef6015, 0, 64 * 1024, 32,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q32dw\", 0xef6016, 0, 64 * 1024, 64,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q64dw\", 0xef6017, 0, 64 * 1024, 128,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q128fw\", 0xef6018, 0, 64 * 1024, 256,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q256jw-q\", 0xef6019, 0, 64 * 1024, 512,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q512nw-q\", 0xef6020, 0, 64 * 1024, 1024,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q01nw-q\", 0xef6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25m512jw\", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q16jv-m\", 0xef7015, 0, 64 * 1024, 32,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q32jv-m\", 0xef7016, 0, 64 * 1024, 64,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q64jv-m\", 0xef7017, 0, 64 * 1024, 128,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q128jv-m\", 0xef7018, 0, 64 * 1024, 256,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q01jv-m\", 0xef7021, 0, 64 * 1024, 2048,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q02jv-m\", 0xef7022, 0, 64 * 1024, 4096,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n \t{ INFO(\"w25m512jv\", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q32jw-m\", 0xef8016, 0, 64 * 1024, 64,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q128jw-m\", 0xef8018, 0, 64 * 1024, 256,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q256jw-m\", 0xef8019, 0, 64 * 1024, 512,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q512nw-m\", 0xef8020, 0, 64 * 1024, 1024,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) },\n+\t{ INFO(\"w25q01nw-m\", 0xef8021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n+\t{ INFO(\"w25q02nw-m\", 0xef8022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25h02jv\", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25h512nw-am\", 0xefa020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25h01nw-am\", 0xefa021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n \t{ INFO(\"w25h02nw-am\", 0xefa022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{ INFO(\"w25q01nw-iq\", 0xef6021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{ INFO(\"w25q01nw-im\", 0xef8021, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{ INFO(\"w25q02nw-im\", 0xef8022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },\n-\t{ INFO(\"w77q51nw\", 0xef8a1a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },\n+\t{ INFO(\"w77q51nw\", 0xef8a1a, 0, 64 * 1024, 1024,\n+\t SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },\n #endif\n #ifdef CONFIG_SPI_FLASH_XMC\n \t/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */\n", "prefixes": [ "v2", "6/7" ] }